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21. VDAT 2017: Roorkee, India
- Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh:
VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers. Communications in Computer and Information Science 711, Springer 2017, ISBN 978-981-10-7469-1
Digital Design
- M. Mohamed Asan Basiri
, Sandeep K. Shukla:
Flexible Composite Galois Field GF((2^m)^2) Multiplier Designs. 3-14 - Manan Mewada, Mazad Zaveri
Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions. 15-23 - Mohd. Tasleem Khan, Shaik Rafi Ahamed:
VLSI Implementation of Throughput Efficient Distributed Arithmetic Based LMS Adaptive Filter. 24-35 - K. Dheepika, K. S. Jevasankari, Vippin Chandhar, Binsu J. Kailath
Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder. 36-47 - Pravin Zode, Raghavendra B. Deshmukh, Abdus Samad:
Fast Architecture of Modular Inversion Using Itoh-Tsujii Algorithm. 48-55 - Jatindeep Singh, Satyajit Mohapatra, Nihar Ranjan Mohapatra:
Performance Optimized 64b/66b Line Encoding Technique for High Speed SERDES Devices. 56-61 - Naman Govil, Rahul Shrestha, Shubhajit Roy Chowdhury:
A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications. 62-68 - Moumita Das, Ansuman Banerjee, Bhaskar Sardar:
A Framework for Branch Predictor Selection with Aggregation on Multiple Parameters. 69-74 - Thilagavathy R
FPGA Implementation of a Novel Area Efficient FFT Scheme Using Mixed Radix FFT. 75-80
Analog/Mixed Signal
- G. Hanumanta Rao
Low Voltage, Low Power Transconductor for Low Frequency G_m -C Filters. 83-92 - Naresh Kumar, Raja Hari Gudlavalleti
An Improved Highly Efficient Low Input Voltage Charge Pump Circuit. 93-102 - Pallavi G. Darji
A Calibration Technique for Current Steering DACs - Self Calibration with Capacitor Storage. 103-114 - M. Santosh, Anjli Bansal, Jitendra Mishra, K. C. Behra, S. C. Bose:
Characterization and Compensation Circuitry for Piezo-Resistive Pressure Sensor to Accommodate Temperature Induced Variation. 115-126 - Ashok Ray, Gaurav Kumar, Sushanta Bordoloi
FEM Based Device Simulator for High Voltage Devices. 127-135 - Sushma Srivastava, Surendra S. Rathod
Synapse Circuits Implementation and Analysis in 180 nm MOSFET and CNFET Technology. 136-143 - Vivek Tyagi, Mohammad S. Hashmi
A 10 MHz, 73 ppm/°C, 84 µW PVT Compensated Ring Oscillator. 144-152
VLSI Testing
- Kanad Basu, Rishi Kumar, Santosh Kulkarni, Rohit Kapur:
Deterministic Shift Power Reduction in Test Compression. 155-167 - Yatharth Gupta, Sujay Deb
Pseudo-BIST: A Novel Technique for SAR-ADC Testing. 168-178 - Rahul Bhattacharya
SFG Based Fault Simulation of Linear Analog Circuits Using Fault Classification and Sensitivity Analysis. 179-190 - Satyadev Ahlawat
A Cost Effective Technique for Diagnosis of Scan Chain Faults. 191-204 - Anshu Goel, Rohini Gulve:
Multi-mode Toggle Random Access Scan to Minimize Test Application Time. 205-216 - Avishek Choudhury, Biplab K. Sikdar
Performance Analysis of Disability Based Fault Tolerance Techniques for Permanent Faults in Chip Multiprocessors. 217-224
Devices and Technology - I
- Ashish Soni, Abhijit Umap, Nihar R. Mohapatra:
Low-Power Sequential Circuit Design Using Work-Function Engineered FinFETs. 227-238 - Satish Maheshwaram
Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance. 239-248 - Ajay Singh, Rakhi Narang
Analysis of Electrolyte-Insulator-Semiconductor Tunnel Field-Effect Transistor as pH Sensor. 249-258 - Aditya Japa, Harshita Vallabhaneni, Ramesh Vaddi:
Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs. 259-269 - Jai Gopal Pandey, Tarun Goel, Abhijit Karmakar
An Efficient VLSI Architecture for PRESENT Block Cipher and Its FPGA Implementation. 270-278 - Jay Pathak
Investigation of TCADs Models for Characterization of Sub 16 nm In _0.53 Ga _0.47 As FinFET. 279-286 - Arindam Sinharay, Pranab Roy, Hafizur Rahaman
Hausdorff Distance Driven L-Shape Matching Based Layout Decomposition for E-Beam Lithography. 287-295
VLSI Architectures
- Sumanth Gudaparthi, Rahul Shrestha:
Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization. 299-312 - Anugrah Jain
Performance-Enhanced d^2 -LBDR for 2D Mesh Network-on-Chip. 313-323 - Sujit Kr Mahto, Newton
ACAM: Application Aware Adaptive Cache Management for Shared LLC. 324-336 - N. S. Aswathy, R. S. Reshma Raj, Abhijit Das
Adaptive Packet Throttling Technique for Congestion Management in Mesh NoCs. 337-344 - Anshu Bhardwaj, Subir Kumar Roy:
Defeating HaTCh: Building Malicious IP Cores. 345-353 - Shanthi Rekha Shanmugham, P. Saravanan
Low Cost Circuit Level Implementation of PRESENT-80 S-BOX. 354-362
Emerging Technologies and Memory
- Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri
Modeling and Analysis of Transient Heat for 3D IC. 365-375 - Mamata Panigrahy
Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder. 376-387 - Divya Singh:
Metal-Oxide Nanostructures Designed by Glancing Angle Deposition Technique and Its Applications on Sensors and Optoelectronic Devices: A Review. 388-397 - Y. Sudha Vani, N. Usha Rani, Ramesh Vaddi:
Low Write Energy STT-MRAM Cell Using 2T- Hybrid Tunnel FETs Exploiting the Steep Slope and Ambipolar Characteristics. 398-405 - Ankit Rehani, Sujay Deb
Enhancing Retention Voltage for SRAM. 406-413 - Anand Ilakal, Anuj Grover
Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies. 414-420 - Neha Chaudhuri, Chandan Bandyopadhyay, Hafizur Rahaman
Improving the Design of Nearest Neighbor Quantum Circuits in 2D Space. 421-426
Devices and Technology - II
- Manish Joshi, Koduri Teja, Ashish Singh, Rohit Dhiman:
Delay and Frequency Investigations in Coupled MLGNR Interconnects. 429-440 - Ambika Prasad Shah
LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits. 441-451 - Shubham Negi, Poornima Mittal, Brijesh Kumar:
Performance Analysis of OLED with Hole Block Layer and Impact of Multiple Hole Block Layer. 452-462 - Rakhi Narang
Improved Gate Modulation in Tunnel Field Effect Transistors with Non-rectangular Tapered Y-Gate Geometry. 463-473 - Purvi Patel, Biswajit Mishra, Dipankar Nagchoudhuri:
A 36 nW Power Management Unit for Solar Energy Harvesters Using 0.18 \upmu m CMOS. 474-486 - Swaati, Bishnu Prasad Das:
A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-Low Power Applications. 487-495 - Vandana Kumari, Manoj Saxena
Variability Investigation of Double Gate JunctionLess (DG-JL) Transistor for Circuit Design Perspective. 496-503
System Design
- Rourab Paul
A High Speed KECCAK Coprocessor for Partitioned NSP Architecture on FPGA Platform. 507-518 - Naushad Ali, Bharat Garg:
New Energy Efficient Reconfigurable FIR Filter Architecture and Its VLSI Implementation. 519-532 - Sanjay Singh, Sumeet Saurav, Ravi Saini, Atanendu S. Mandal, Santanu Chaudhury:
FPGA-Based Smart Camera System for Real-Time Automated Video Surveillance. 533-544 - B. Vandana
Effectiveness of High Permittivity Spacer for Underlap Regions of Wavy-Junctionless FinFET at 22 nm Node and Scaling Short Channel Effects. 545-556 - Puja Ghosh, P. Rangababu
Design and Implementation of Ternary Content Addressable Memory (TCAM) Based Hierarchical Motion Estimation for Video Processing. 557-569 - Kavya Sharat, Sumeet Bandishte, Kuruvilla Varghese, Bharadwaj S. Amrutur:
A Custom Designed RISC-V ISA Compatible Processor for SoC. 570-577
Low Power Design and Test
- Jasmine Kaur Gulati, Bhanu Prakash, Sumit Jagdish Darak
An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction. 581-593 - Ayan Palchaudhuri
Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs. 594-606 - Rohini Gulve, Nihar Hage:
On Generation of Delay Test with Capture Power Safety. 607-618 - Prokash Ghosh
A Configurable and Area Efficient Technique for Implementing Isolation Cells in Low Power SoC. 619-627
RF Circuits
- Vivek Tyagi, Mohammad S. Hashmi
A 10 MHz, 42 ppm/ °C, 69 μW PVT Compensated Latch Based Oscillator in BCD9S Technology for PCM. 631-645 - Antaryami Panigrahi
A 1.8 V Gain Enhanced Fully Differential Doubly-Recycled Cascode OTA with 100 dB Gain 200 MHz UGB in CMOS. 646-656 - Mudasir Bashir
A Low Power, Frequency-to-Digital Converter CMOS Based Temperature Sensor in 65 nm Process. 657-666 - Munish Malik, Ajay Kumar, H. S. Jatana:
Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL's 0.18 µm CMOS Process. 667-678
Architecture and CAD
- Sameer Pawanekar, Gaurav Trivedi:
Fast FPGA Placement Using Analytical Optimization. 681-693 - Arpan Chakraborty, Piyali Datta, Debasis Dhal, Rajat Kumar Pal:
A Dependability Preserving Fluid-Level Synthesis for Reconfigurable Droplet-Based Microfluidic Biochips. 694-706 - T. Pravinraj
Splitting and Transport of a Droplet with No External Actuation Force for Lab on Chip Devices. 707-717 - Sameer Pawanekar, Gaurav Trivedi:
Analytical Partitioning: Improvement over FM. 718-730 - Rajul Bansal, Mahendra Kumar Jatav, Abhijit Karmakar
A Lifting Instruction for Performing DWT in LEON3 Processor Based System-on-Chip. 731-736 - Vandana Jain, Vasavi Devarasetty, Rajendra M. Patrikar:
Droplet Position Estimator for Open EWOD System Using Open Source Computer Vision. 737-741 - Rituparna Choudhury
Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC Decoder. 742-750
Design Verification
- Binod Kumar, Kanad Basu, Ankit Jindal, Brajesh Pandey
A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection. 753-766 - Ramanuj Chouksey, Chandan Karfa
Translation Validation of Loop Invariant Code Optimizations Involving False Computations. 767-778 - Antara Ain, Sayandeep Sanyal, Pallab Dasgupta:
A Framework for Automated Feature Based Mixed-Signal Equivalence Checking. 779-791 - Surajit Das, Chandan Karfa
xMAS Based Accurate Modeling and Progress Verification of NoCs. 792-804 - Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
Faulty TSVs Identification in 3D IC Using Pre-bond Testing. 805-812
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