Abstract
At sub 16 nm In\(_{0.53}\)Ga\(_{0.47}\)As FinFET technology node the fabrication of device is quite complex in many sense. The study of such devices is only possible through TCAD simulations. To understand the behavior of such device the TCAD tool has to incorporate various simulation models related to physics of semiconductor and device geometry. In this paper, we have calibrated 50 nm In\(_{0.53}\)Ga\(_{0.47}\)As FinFET using various simulation models with experimental results and then same models are used to characterize \(I_{d}-V_g\) and \(I_{d}-V_{d}\) characteristics and along with the short channel parameters for the sub 16 nm In\(_{0.53}\)Ga\(_{0.47}\)As FinFET. The analysis is done on two types of devices i.e. Raised S/D with nitride spacers and without nitride spacers. Subthreshold slope SS (mV/dec) and DIBL (mV/V) for raised S/D In\(_{0.53}\)Ga\(_{0.47}\)As FinFET with spacers is measured as 65.48 and 38.4 respectively, while without spacers it is 84.45 and 44.
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References
Kalna, K., Seoane, N.: Benchmarking of scaled InGaAs implant-free nano MOSFETs. IEEE Trans. Electron Devices 55(9), 2297 (2008)
Djara, V., Deshpande, V., Sousa, M., Caimi, D., Czornomaz, L., Fompeyrine, J.: CMOS-compatible replacement metal gate InGaAs-OI FinFET with ION= 156 \(\upmu \)A/\(\upmu \)m at VDD=0.5 V and IOFF=100 nA/\(\upmu \)m. IEEE Electron Device Lett. 37(2), 169 (2016)
Sachid, A.B., Francis, R., Baghini, M.S., Sharma, D.K., Bach, K.H., Mahnkopf, R., Rao, V.R.: Sub-20 nm gate length FinFET design: can high-k spacers make a difference? In: Proceedings IEEE IEDM, pp. 1–4. IEEE (2008)
Tewari, S., Biswas, A., Mallik, A.: Impact of a spacer layer on the analog performance of asymmetric InP/InGaAs nMOSFETs. IEEE Trans. Electron Devices 63(6), 2313 (2016)
Koley, K., Dutta, A., Syamal, B., Saha, S.K., Sarkar, C.K.: Subthreshold analog/RF performance enhancement of underlap DG FETs with high-k spacer for low power applications. IEEE Trans. Electron Devices 60(1), 63 (2013)
ITRS. International Technology Roadmap for Semiconductors. http://www.itrs.net/Links/2009ITRS/Home2013.htm/ (2013)
Lombardi, C., Manzini, S., Saporito, A., Vanzi, M.: A physically based mobility model for numerical simulation of nonplanar devices. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 7(11), 1164 (1988)
Synopsys Inc, Mountain View, CA 2016 (2016)
Ortiz-Conde, A., García-Sánchez, F.J., Muci, J., Barrios, A.T., Liou, J.J., Ho, C.S.: Revisiting MOSFET threshold voltage extraction methods. Microelectron. Reliab. 53(1), 90 (2013)
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Pathak, J., Darji, A. (2017). Investigation of TCADs Models for Characterization of Sub 16 nm In\(_{0.53}\)Ga\(_{0.47}\)As FinFET. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_28
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DOI: https://doi.org/10.1007/978-981-10-7470-7_28
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