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Satyadev Ahlawat
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2020 – today
- 2024
- [j3]Aditi Gupta
, Sukanya Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh:
A-TSPD: autonomous-two stage algorithm for robust peak detection in online time series. Clust. Comput. 27(4): 4063-4076 (2024) - [j2]Aditi Gupta
DAT: A robust Discriminant Analysis-based Test of unimodality for unknown input distributions. Pattern Recognit. Lett. 182: 125-132 (2024) - [c27]Gaurav Kumar
On Evaluating Test Response Obfuscation and Encryption Countermeasures. IOLTS 2024: 1-3 - [i1]Mahendra Gurve, Sankar Behera, Satyadev Ahlawat, Yamuna Prasad:
MisGUIDE : Defense Against Data-Free Deep Learning Model Extraction. CoRR abs/2403.18580 (2024) - 2023
- [c26]Gaurav Kumar
On Enhancing the Security of Streaming Scan Network Architecture. ATS 2023: 1-6 - [c25]Gaurav Kumar
On Evaluating the Security of Dynamic Scan Obfuscation Scheme. IOLTS 2023: 1-7 - [c24]Aditi Gupta
TSPD: A Robust Online Time Series Two-Stage Peak Detection Algorithm. SOSE 2023: 91-97 - [c23]Anjum Riaz, Gaurav Kumar
On Protecting IJTAG using an Inherently Secure SIB. VLSI-SoC 2023: 1-6 - 2022
- [c22]Gaurav Kumar
A New Access Protocol for Elevating the Security of IJTAG Network. ATS 2022: 31-36 - [c21]Yogendra Sao, Anjum Riaz, Satyadev Ahlawat, Sk Subidh Ali:
Evaluating Security of New Locking SIB-based Architectures. ETS 2022: 1-6 - [c20]Gaurav Kumar
On Attacking Locking SIB based IJTAG Architecture. ACM Great Lakes Symposium on VLSI 2022: 105-109 - [c19]Gaurav Kumar
On Attacking IJTAG Architecture based on Locking SIB with Security LFSR. IOLTS 2022: 1-6 - [c18]Anjum Riaz, Gaurav Kumar
On Protecting IJTAG from Data Sniffing and Alteration Attacks. ISVLSI 2022: 146-151 - [c17]Gaurav Kumar
Low Cost Implementation of Deep Neural Network on Hardware. VDAT 2022: 584-594 - [c16]Gaurav Kumar
Power Analysis Attack on Locking SIB based IJTAG Achitecture. VLSI-SoC 2022: 1-6 - 2021
- [j1]Jaynarayan T. Tudu
A Framework for Configurable Joint-Scan Design-for-Test Architecture. J. Electron. Test. 37(5): 593-611 (2021)
2010 – 2019
- 2019
- [c15]Satyadev Ahlawat
Preventing Scan Attack through Test Response Encryption. DFT 2019: 1-6 - [c14]Satyadev Ahlawat
Securing Scan through Plain-text Restriction. IOLTS 2019: 251-252 - 2018
- [c13]Satyadev Ahlawat, Darshit Vaghani, Naveen Bazard, Virendra Singh:
Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks. EWDTS 2018: 1-6 - [c12]Nihar Hage, Satyadev Ahlawat
In-situ Monitoring for Slack Time Violation Without Performance Penalty. ISCAS 2018: 1-5 - [c11]Darshit Vaghani, Satyadev Ahlawat
On Securing Scan Design Through Test Vector Encryption. ISCAS 2018: 1-5 - 2017
- [c10]Satyadev Ahlawat
On Securing Scan Design from Scan-Based Side-Channel Attacks. ATS 2017: 58-63 - [c9]Satyadev Ahlawat
Preventing scan-based side-channel attacks through key masking. DFT 2017: 1-4 - [c8]Satyadev Ahlawat
An efficient test technique to prevent scan-based side-channel attacks. ETS 2017: 1-2 - [c7]Satyadev Ahlawat
A low cost technique for scan chain diagnosis. ISCAS 2017: 1-4 - [c6]Satyadev Ahlawat
A Cost Effective Technique for Diagnosis of Scan Chain Faults. VDAT 2017: 191-204 - 2016
- [c5]Satyadev Ahlawat
Enabling LOS delay test with slow scan enable. EWDTS 2016: 1-4 - [c4]Satyadev Ahlawat
A high performance scan flip-flop design for serial and mixed mode scan test. IOLTS 2016: 233-238 - [c3]Satyadev Ahlawat
On minimization of test power through modified scan flip-flop. VDAT 2016: 1-6 - [c2]Jaynarayan T. Tudu
Guided shifting of test pattern to minimize test time in serial scan. VDAT 2016: 1-6 - 2015
- [c1]Satyadev Ahlawat
A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. ATS 2015: 25-30
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last updated on 2024-10-07 22:13 CEST by the dblp team
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