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Kazutaka Kasuga
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2010 – 2019
- 2010
- [j2]Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu
, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. IEEE J. Solid State Circuits 45(4): 856-862 (2010) - [j1]Kiichi Niitsu
Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1238-1243 (2010) - [c3]Noriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda:
An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. ISSCC 2010: 436-437
2000 – 2009
- 2009
- [c2]Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu
MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. FPL 2009: 6-11 - [c1]Kiichi Niitsu
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. ISSCC 2009: 480-481
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