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Naohiko Irie
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2010 – 2019
- 2011
- [j7]Kiichi Niitsu
, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda:
Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1902-1907 (2011) - 2010
- [j6]Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. IEEE J. Solid State Circuits 45(4): 856-862 (2010) - [j5]Kiichi Niitsu
Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1238-1243 (2010)
2000 – 2009
- 2009
- [j4]Naohiko Irie, Toshihiro Hattori:
Multi-Core/Multi-IP Technology for Embedded Applications. IEICE Trans. Electron. 92-C(10): 1232-1239 (2009) - [j3]Tohru Nojiri, Yuki Kondo, Naohiko Irie, Masayuki Ito, Hajime Sasaki, Hideo Maejima:
Domain Partitioning Technology for Embedded Multicore Processors. IEEE Micro 29(6): 7-17 (2009) - [c7]Kiichi Niitsu
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. ISSCC 2009: 480-481 - 2007
- [j2]Tetsuya Yamada, Naohiko Irie, Takanobu Tsunoda, Takahiro Irita, Kenji Kitagawa, Ryohei Yoshida, Keisuke Toyama, Motoaki Satoyama:
A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core. IEICE Trans. Electron. 90-C(2): 523-530 (2007) - [j1]Yusuke Kanno, Hiroyuki Mizuno
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. IEEE J. Solid State Circuits 42(1): 74-83 (2007) - [c6]Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara
A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. ISSCC 2007: 100-590 - [c5]Makoto Saen, Kenichi Osada, Satoshi Misaka, Tetsuya Yamada, Yoshitaka Tsujimoto, Yuki Kondo, Tatsuya Kamei, Yutaka Yoshida, Ei Nagahama, Yusuke Nitta, Takayasu Ito, Tadashi Kameyama, Naohiko Irie:
Embedded SoC Resource Manager to Control Temperature and Data Bandwidth. ISSCC 2007: 296-604 - 2006
- [c4]Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno:
Hierarchical power distribution and power management scheme for a single chip mobile processor. DAC 2006: 292-295 - [c3]Yusuke Kanno, Hiroyuki Mizuno
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. ISSCC 2006: 2200-2209 - 2005
- [c2]Makoto Saen, Hiroshi Ueda, Masaru Hase, Eiji Yamamoto, Yoshihiro Mori, Hiroshi Hatae, Yuki Kondo, Seiji Miura, Itaru Nonomura, Naohiko Irie, Hiromi Watanabe:
Elastic shared resource scheduling SOC interconnect architecture for real-time system. CICC 2005: 787-790
1980 – 1989
- 1989
- [c1]Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita:
SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. ISCA 1989: 78-85
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