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José Luis Briz
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- affiliation: University of Zaragoza, Spain
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2020 – today
- 2024
- [j12]Alitzel Galilea Torres-Macías
, Juan Segarra Flor
Fast IEEE802.1Qbv Gate Scheduling Through Integer Linear Programming. IEEE Access 12: 111239-111250 (2024) - 2022
- [j11]Laura Elena Rubio Anguiano
Accounting for Preemption and Migration Costs in the Calculation of Hard Real-Time Cyclic Executives for MPSoCs. IEEE Robotics Autom. Lett. 7(3): 7990-7997 (2022) - 2021
- [j10]Laura Elena Rubio Anguiano
Maximizing Utilization and Minimizing Migration in Thermal-Aware Energy-Efficient Real-Time Multiprocessor Scheduling. IEEE Access 9: 83309-83328 (2021)
2010 – 2019
- 2019
- [j9]Gaddiel Desirena-Lopez, Laura Elena Rubio Anguiano, Antonio Ramírez-Treviño
A Flexible Framework for Real-Time Thermal-Aware Schedulers using Timed Continuous Petri Nets. Computación y Sistemas 23(2): 417-434 (2019) - [j8]Laura Elena Rubio Anguiano, Gaddiel Desirena-Lopez, Antonio Ramírez-Treviño
Energy-efficient thermal-aware multiprocessor scheduling for real-time tasks using TCPN. Discret. Event Dyn. Syst. 29(3): 237-264 (2019) - [j7]Gaddiel Desirena-Lopez, Antonio Ramírez-Treviño
Thermal-aware Real-time Scheduling Using Timed Continuous Petri Nets. ACM Trans. Embed. Comput. Syst. 18(4): 36:1-36:24 (2019) - [c8]Alejandro Valero
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. WCAE@ISCA 2019: 5:1-5:8 - 2018
- [j6]Rafael Trapani Possignolo
GPU NTC Process Variation Compensation With Voltage Stacking. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1713-1726 (2018) - 2017
- [j5]Javier Olivito
Accelerating Board Games Through Hardware/Software Codesign. IEEE Trans. Comput. Intell. AI Games 9(4): 393-401 (2017) - 2016
- [j4]Ehsan K. Ardestani, Rafael Trapani Possignolo, José Luis Briz
Managing Mismatches in Voltage Stacking with CoreUnfolding. ACM Trans. Archit. Code Optim. 12(4): 43:1-43:26 (2016) - [c7]Gaddiel Desirena-Lopez, Carlos Renato Vázquez
On-line scheduling in multiprocessor systems based on continuous control using Timed Continuous Petri Nets. WODES 2016: 278-283 - 2013
- [c6]Alamelu Sankaranarayanan, Ehsan K. Ardestani, José Luis Briz
An energy efficient GPGPU memory hierarchy with tiny incoherent caches. ISLPED 2013: 9-14 - 2011
- [j3]Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals:
Multi-level Adaptive Prefetching based on Performance Gradient Tracking. J. Instr. Level Parallelism 13 (2011)
2000 – 2009
- 2008
- [c5]Luis M. Ramos, José Luis Briz
Low-Cost Adaptive Data Prefetching. Euro-Par 2008: 327-336 - 2007
- [j2]Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez
Data prefetching in a cache hierarchy with high bandwidth and capacity. SIGARCH Comput. Archit. News 35(4): 37-44 (2007) - 2006
- [j1]Jesús Alastruey
Software Demand, Hardware Supply. IEEE Micro 26(4): 72-82 (2006) - [c4]Luis M. Ramos, José Luis Briz
Data prefetching in a cache hierarchy with high bandwidth and capacity. MEDEA@PACT 2006: 37-44 - 2001
- [c3]María Jesús Garzarán, José Luis Briz, Pablo E. Ibáñez
Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware. PDP 2001: 345-354
1990 – 1999
- 1998
- [c2]Pablo Ibáñez
Characterization and Improvement of Load/Store Cache-based Prefetching. International Conference on Supercomputing 1998: 369-376 - 1994
- [c1]José Luis Briz, José Manuel Colom:
Implementation of Weighted Place/Transition Nets Based on Linear Enabling Functions. Application and Theory of Petri Nets 1994: 99-118
Coauthor Index
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