research-article

Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs

Author:

Philippe FlatresseAuthors Info & Claims

ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design

Pages 127 - 130

https://doi.org/10.1145/2627369.2631640

Published: 11 August 2014 Publication History

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Abstract

Planar UTBB FD-SOI technology is an opportunity for energy efficient SOCs in deeply scaled technologies. Thanks to its excellent responsiveness to power management design techniques, this technology brings a significant improvement in terms of performance and power savings. The unique features offered by this technology at process and design levels enable a differentiation in terms of flexibility, cost and energy efficiency with respect to any process available on the market.

References

[1]

Y. Shin et al, "28nm high- metal-gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor", 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Page(s): 154--155

Google Scholar

[2]

Jakubczak, S. ; Katabi, D., "SoftCast: Clean-slate scalable wireless video", 2010 48th Annual Allerton Conference on Communication, Control, and Computing (Allerton), Page(s): 530--533

Google Scholar

[3]

B. Nikolić, M. Blagojević, O. Thomas, P. Flatresse, A. Vladimirescu, "Circuit Design in Nanoscale FDSOI Technologie", 2014 MIEL Conference

Google Scholar

[4]

Flatresse, P.; Giraud, B.; Noel, J.; Pelloux-Prayer, B.; Giner, F.; Arora, D.; Arnaud, F.; Planes, N.; Le Coz, J.; Thomas, O.; Engels, S.; Cesana, G.; Wilson, R.; Urard, P., "Ultra-wide body-bias range LDPC decoder in 28nm UTBB FD-SOI technology", 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Page(s): 424--425.

Google Scholar

[5]

Arnaud, F.; Planes, N.; Weber, O.; Barral, V.; Haendler, S.; Flatresse, P.; Nyer, F., "Switching energy efficiency optimization for advanced CPU thanks to UTBB technology", 2012 IEEE International Electron Devices Meeting (IEDM), Page(s): 3.2.1-- 3.2.4

Google Scholar

[6]

Pique, G.V.; Meijer, M., "A 350nA voltage regulator for 90nm CMOS digital circuits with Reverse-Body-Bias", 2011 Proceedings of the ESSCIRC (ESSCIRC), Page(s): 379-- 382

Google Scholar

[7]

Meijer, M.; de Gyvez, J.P.; Kup, B.; van Uden, B.; Bastiaansen, P.; Lammers, M.; Vertregt, M., "A forward body bias generator for digital CMOS circuits with supply voltage scaling", Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), Page(s): 2482--2485

Google Scholar

[8]

Jacquet, D.; Cesana, G.; Flatresse, P.; Arnaud, F.; Menut, P.; Hasbani, F.; Di Gilio, T.; Lecocq, C.; Roy, T.; Chhabra, A.; Grover, C.; Minez, O.; Uginet, J. ; Durieu, G; Nyer, F.; Adobati, C.; Wilson, R.; Casalotto, D., "2.6GHz ultra-wide voltage range energy efficient dual A9 in 28nm UTBB FD-SOI", 2013 Symposium on VLSI Technology (VLSIT), Page(s): C44-C45

Google Scholar

[9]

Philippe Magarshack, Philippe Flatresse, Giorgio Cesana: UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency. DATE 2013, Page(s): 952--957, 2013.

Digital Library

Google Scholar

[10]

Noel, J.-P.; Thomas, O.; Jaud, M.; Weber, O.; Poiroux, T.; Fenouillet-Beranger, C.; Rivallin, P. ; Scheiblin, P.; Andrieu, F.; Vinet, M.; Rozeau, O.; Boeuf, F.; Faynot, O.; Amara, A., "Multi- UTBB FD-SOI Device Architectures for Low-Power CMOS Circuit", IEEE Transactions on Electron Devices, Volume: 58, Issue: 8, 2011, Page(s): 2473--2482Tavel, P. 2007. Modeling and Simulation Design. AK Peters Ltd., Natick, MA.

Crossref

Google Scholar

[11]

Planes, N.et al, "28nm FD-SOI technology platform for high-speed low-voltage digital applications", 2012 Symposium on VLSI Technology (VLSIT), Page(s): 133--134.

Google Scholar

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Radu IDesbonnets ESellier MDidier C(2018)Enabling 5G — A substrate material perspective: AEM, ET/ID2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)10.1109/ASMC.2018.8373174(143-147)Online publication date: Apr-2018
https://doi.org/10.1109/ASMC.2018.8373174
Veirano FNaviner LSilveira F(2017)Optimum nMOS/pMOS Imbalance for Energy Efficient Digital CircuitsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2017.274748064:12(3081-3091)Online publication date: Dec-2017
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Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs
1. Hardware

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Information & Contributors

Information

Published In

ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design

August 2014

398 pages

ISBN:9781450329750

DOI:10.1145/2627369

General Chairs:
Yuan Xie
UCSB, USA
,
Tanay Karnik
Intel, USA
,
Program Chairs:
Muhammad M. Khellah
Intel, USA
,
Renu Mehra
Synopsys, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 August 2014

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ISLPED'14

Sponsor:

SIGDA

ISLPED'14: International Symposium on Low Power Electronics and Design

August 11 - 13, 2014

California, La Jolla, USA

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Cited By

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Radu IDesbonnets ESellier MDidier C(2018)Enabling 5G — A substrate material perspective: AEM, ET/ID2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)10.1109/ASMC.2018.8373174(143-147)Online publication date: Apr-2018
https://doi.org/10.1109/ASMC.2018.8373174
Veirano FNaviner LSilveira F(2017)Optimum nMOS/pMOS Imbalance for Energy Efficient Digital CircuitsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2017.274748064:12(3081-3091)Online publication date: Dec-2017
https://doi.org/10.1109/TCSI.2017.2747480
Veirano FSilveira FNaviner L(2017)Asymmetrical length biasing for energy efficient digital circuits2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS.2017.7948060(1-4)Online publication date: Feb-2017
https://doi.org/10.1109/LASCAS.2017.7948060
Rao SPrautsch BShrivastava AReich T(2017)Body biasing for analog design: Practical experiences in 22 nm FD-SOI2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)10.1109/DDECS.2017.7934580(73-78)Online publication date: Apr-2017
https://doi.org/10.1109/DDECS.2017.7934580
Doria RFlandre DTrevisoli Rde Souza MPavanello M(2017)Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structuresSemiconductor Science and Technology10.1088/1361-6641/aa765932:9(095005)Online publication date: 11-Aug-2017
https://doi.org/10.1088/1361-6641/aa7659
Veirano FNaviner LSilveira F(2017)Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOIIntegration, the VLSI Journal10.1016/j.vlsi.2017.08.008Online publication date: Aug-2017
https://doi.org/10.1016/j.vlsi.2017.08.008
Deval YRivet Fde Lima Monteiro DTorres FIndrusiak L(2016)A balanced logic routing block for factorial-DLL based frequency generationProceedings of the 29th Symposium on Integrated Circuits and Systems Design: Chip on the Mountains10.5555/3145862.3145887(1-4)Online publication date: 29-Aug-2016
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Teman ARossi DMeinerzhagen PBenini LBurg A(2016)Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled PlacementACM Transactions on Design Automation of Electronic Systems10.1145/289049821:4(1-25)Online publication date: 27-May-2016
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Deval YRivet F(2016)A balanced logic routing block for Factorial-DLL based Frequency Generation2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI.2016.7724061(1-4)Online publication date: Aug-2016
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Veirano FNaviner LSilveira F(2016)Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2016.7833694(243-249)Online publication date: Sep-2016
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