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Anuj Grover
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2020 – today
- 2024
- [j5]Rachit Sharma
, Anuj Grover
Up to 45% Faster Supply Boosted Voltage Sense Amplifier (SBVSA) for High-Speed SRAMs. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4683-4687 (2024) - [c36]Ajay Shroti, Anuj Grover:
Design Of High-Density Iso-Stable Asymmetric Memory Cell With Upto 10X Reduced Leakage. ISCAS 2024: 1-5 - 2023
- [c35]Debjit Batabyal, Sandeep Kumar Singh, Rajnish Kumar Mishra, Anuj Grover:
A Sense Amplifier Based Bulk Built-In Current Sensor for Detecting Laser-Induced Currents. VLSID 2023: 69-74 - [c34]Belal Iqbal, Anuj Grover, Harsh Rawat:
A Common Mode Insensitive Process Tolerant Sense Amplifier Design for In Memory Compute Applications in 65nm LSTP Technology. VLSID 2023: 121-126 - 2022
- [c33]Belal Iqbal, Anuj Grover, Harsh Rawat:
A Process and Data Variations Tolerant Capacitive Coupled 10T1C SRAM for In-Memory Compute (IMC) in Deep Neural Network Accelerators. AICAS 2022: 459-462 - [c32]Srikrishna Vasudev, Kartickraj K, Anuj Grover:
Up to 13.7% Increase in Throughput of RISC V SoC Using Timing Speculative Razor SRAM. APCCAS 2022: 222-225 - [c31]Anant Grover
Human Pose Estimation using Deep Learning Techniques. ICIMMI 2022: 72:1-72:6 - [c30]Anuj Grover
Keypoint Detection for Identifying Body Joints using TensorFlow. ICIMMI 2022: 111:1-111:6 - [c29]Mukesh Kumar Srivastav, Rimjhim, Roshan Mishra, Anuj Grover, Kedar Janardan Dhori, Harsh Rawat:
3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS. ISCAS 2022: 1546-1550 - [c28]Chandan Kumar, Rahul Kumar, Anuj Grover, Shouri Chatterjee, Kedar Janardan Dhori, Harsh Rawat:
Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI. VLSID 2022: 228-233 - 2021
- [j4]Mohammed Aamir
ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices. IEEE Open J. Circuits Syst. 2: 833-842 (2021) - [c27]Swapnil Bansal, Anuj Grover:
Process Compensated Diagnostic Circuit For Impending Fault Detection In SRAM Write Drivers. APCCAS 2021: 185-188 - [c26]Mukesh Kumar Srivastav, Rimjhim, Govind Soni, Umang Mittal, Rupali Tewari, Riya Yadav, Anuj Grover, Kedar Janardan Dhori, Harsh Rawat:
Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS. ICECS 2021: 1-6 - [c25]Feraj Husain, Belal Iqbal, Anuj Grover
A 0.4µA Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-Volatile Memories in 65nm LSTP Technology. VLSID 2021: 76-81 - [c24]Kumari Anjali, Shubham Saha, Anuj Grover
Reduced March iC- Test for Detecting Ageing Induced Faults in Memory Address Decoders. VLSID 2021: 193-198 - 2020
- [c23]Prakhar Shukla
A 800MHz, O.21pJ, 1.2V to 6V Level Shifter Using Thin Gate Oxide Devices in 65nm LSTP. ICECS 2020: 1-4 - [c22]Shivendra Singh, Varshita Gupta, Anuj Grover
Diagnostic Circuit for Latent Fault Detection in SRAM Row Decoder. ISQED 2020: 395-400 - [c21]Shashank Neeraj Dwivedi, Ashish Kumar Seth, Anuj Grover
Design & Benchmark of Single Bit & Multi Bit Sequential Elements in 65nm for Low Standby Power Consumption. VDAT 2020: 1-6 - [c20]Mishal Kumar, Anuj Grover
A 0.47V-1.17V 32KB Timing Speculative SRAM in 28nm HKMG CMOS. VDAT 2020: 1-5 - [c19]Aparna Mishra, Anuj Grover
A 0.9V 64Mb 6T SRAM cell with Read and Write assist schemes in 65nm LSTP technology. VDAT 2020: 1-4 - [c18]Vaibhav Verma
Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology. VDAT 2020: 1-6 - [c17]Vinay Patil, Anuj Grover
Design of Sense Amplifier for Wide Voltage Range Operation of Split Supply Memories in 22nm HKMG CMOS Technology. VLSID 2020: 37-42
2010 – 2019
- 2018
- [c16]Ankush Mamgain, Anuj Grover
A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP Technology. SoCC 2018: 203-208 - 2017
- [j3]Anuj Grover
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2438-2447 (2017) - [j2]Shalini Pathak
LoCCo-Based Scan Chain Stitching for Low-Power DFT. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3227-3236 (2017) - [c15]Anand Ilakal, Anuj Grover
Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies. VDAT 2017: 414-420 - 2016
- [c14]Jasvir Singh, Anuj Grover
Scan Chain Adaptation through ECO. ATS 2016: 107-112 - [c13]Nidhi Batra, Pawan Sehgal, Shashwat Kaushik, Mohammad S. Hashmi
Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques. ACM Great Lakes Symposium on VLSI 2016: 117-120 - [c12]Nidhi Batra, Shashwat Kaushik, Anil Kumar Gundu, Mohammad S. Hashmi
A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementation. SoCC 2016: 47-51 - [c11]Prakhar Raj Gupta, G. S. Visweswaran, Gaurav Narang, Anuj Grover
Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework. SoCC 2016: 290-295 - [c10]Nidhi Batra, Anil Kumar Gundu, Mohammad S. Hashmi
An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI. VDAT 2016: 1-6 - [c9]Antara Ganguly, Sangeeta Goyal, Sneha Bhatia, Anuj Grover
New stable loadless 6T dual-port SRAM cell design. VDAT 2016: 1-6 - [c8]Anil Kumar Gundu, Mohammad S. Hashmi
A New Sense Amplifier Topology with Improved Performance for High Speed SRAM Applications. VLSID 2016: 185-190 - 2015
- [j1]Edith Beigné
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits 50(1): 125-136 (2015) - [c7]Anuj Grover
Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs. ICICDT 2015: 1-4 - [c6]Gaurav Narang, Alexander Fell
Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems. SoCC 2015: 105-110 - [c5]Jitendra Yadav, Pallavi Das, Abhinav Jain, Anuj Grover
Area compact 5T portless SRAM cell for high density cache in 65nm CMOS. VDAT 2015: 1-4 - [c4]Gaurav Narang, Pragya Sharma, Mansi Jain, Anuj Grover
Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance. VLSID 2015: 411-416 - 2014
- [c3]Robin Wilson, Edith Beigné
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC 2014: 452-453 - 2013
- [c2]Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE 2013: 613-618 - [c1]Guillaume Moritz, Bastien Giraud, Jean-Philippe Noel, David Turgis, Anuj Grover
Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology. ICICDT 2013: 53-56
Coauthor Index
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