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ACM Transactions on Reconfigurable Technology and Systems, Volume 4
Volume 4, Number 1, December 2010
- Roger F. Woods, Jürgen Becker, Peter Athanas, Fearghal Morgan:
Guest Editorial ARC 2009. 1:1-1:2 - Chalermpol Saiprasert, Christos-Savvas Bouganis
, George A. Constantinides:
An Optimized Hardware Architecture of a Multivariate Gaussian Random Number Generator. 2:1-2:21 - Asma Kahoul, Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods. 3:1-3:23 - Krzysztof Kepa
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems. 4:1-4:26 - Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. 5:1-5:24 - Xu Guo, Patrick Schaumont
Optimized System-on-Chip Integration of a Programmable ECC Coprocessor. 6:1-6:21 - Luca Sterpone
A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs. 7:1-7:21 - Marco Lanuzza
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. 8:1-8:22 - Pao-Ann Hsiung, Chun-Hsian Huang, Jih-Sheng Shen, Cheng-Chi Chiang:
Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems. 9:1-9:32 - Kenji Kanazawa, Tsutomu Maruyama:
An Approach for Solving Large SAT Problems on FPGA. 10:1-10:21 - Yingxi Lu, Máire O'Neill, John V. McCanny:
Evaluation of Random Delay Insertion against DPA on FPGAs. 11:1-11:20
Volume 4, Number 2, May 2011
- Etienne Bergeron, Louis-David Perron, Marc Feeley, Jean-Pierre David:
Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation. 12:1-12:27 - Pranav Vaidya, Jaehwan John Lee
A Novel Multicontext Coarse-Grained Reconfigurable Architecture (CGRA) For Accelerating Column-Oriented Databases. 13:1-13:30 - Shane O'Neill, Roger F. Woods
A Scalable and Programmable Modular Traffic Manager Architecture. 14:1-14:19 - Mao Nakajima, Minoru Watanabe:
Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control. 15:1-15:21 - Tzu-Chiang Tai, Yen-Tai Lai:
A Performance-Oriented Algorithm with Consideration on Communication Cost for Dynamically Reconfigurable FPGA Partitioning. 16:1-16:18 - Melina Demertzi, Pedro C. Diniz
Domain-Specific Optimization of Signal Recognition Targeting FPGAs. 17:1-17:26 - Carlo Galuzzi, Koen Bertels:
The Instruction-Set Extension Problem: A Survey. 18:1-18:28 - Kyle Rupnow
Scientific Application Demands on a Reconfigurable Functional Unit Interface. 19:1-19:30 - Alexander Kaganov, Asif Lakhany, Paul Chow:
FPGA Acceleration of MultiFactor CDO Pricing. 20:1-20:17
Volume 4, Number 3, August 2011
- Martin Labrecque, Mark C. Jeffrey
Application-specific signatures for transactional memory in soft processors. 21:1-21:14 - David Boland
Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods. 22:1-22:14 - Johann Glaser, Markus Damm, Jan Haase
TR-FSM: Transition-Based reconfigurable finite state machine. 23:1-23:14 - Husain Parvez, Zied Marrakchi, Alp Kiliç, Habib Mehrez:
Application-Specific FPGA using heterogeneous logic blocks. 24:1-24:14 - Jing Yan, Ning-Yi Xu, Xiongfei Cai, Rui Gao, Yu Wang
An FPGA-based accelerator for LambdaRank in Web search engines. 25:1-25:19 - Vikas Aggarwal, Alan D. George
SHMEM+: A multilevel-PGAS programming model for reconfigurable supercomputing. 26:1-26:24 - Brian Holland, Alan D. George
An analytical model for multilevel performance prediction of Multi-FPGA systems. 27:1-27:28 - Lesley Shannon, Paul Chow:
Leveraging reconfigurability in the hardware/software codesign process. 28:1-28:27 - Federico Nava, Donatella Sciuto
Applying dynamic reconfiguration in the mobile robotics domain: A case study on computer vision algorithms. 29:1-29:22 - Seth Koehler, Greg Stitt, Alan D. George
Platform-aware bottleneck detection for reconfigurable computing applications. 30:1-30:28
Volume 4, Number 4, December 2011
- Peter Y. K. Cheung:
Introduction to special section FPGA 2009. 31:1 - Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Kenneth B. Kent
VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. 32:1-32:23 - Raphael Rubin, André DeHon:
Choose-your-own-adventure routing: Lightweight load-time defect avoidance. 33:1-33:24 - Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Stephen Jang:
Scalable don't-care-based logic optimization and resynthesis. 34:1-34:23 - Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox:
FPGA technology mapping with encoded libraries and staged priority cuts. 35:1-35:17 - Kyprianos Papadimitriou
Performance of partial reconfiguration in FPGA systems: A survey and a cost model. 36:1-36:24 - Xiaoheng Chen, Venkatesh Akella:
Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA. 37:1-37:17 - Lakshmi Easwaran, Ali Akoglu
Net-length-based routability-driven power-aware clustering. 38:1-38:16 - Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk
Compressor tree synthesis on commercial high-performance FPGAs. 39:1-39:19 - Hiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, Masato Motomura
Test compression for dynamically reconfigurable processors. 40:1-40:15
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