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Jih-Sheng Shen
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2010 – 2019
- 2014
- [j7]Hung-Lin Chao, Cheng-Chien Wu, Chun-Yang Peng, Chun-Hsien Lu, Jih-Sheng Shen, Pao-Ann Hsiung:
Dynamic partially reconfigurable architecture for fast Fourier transform computation. Int. J. Embed. Syst. 6(2/3): 207-215 (2014) - [j6]Jih-Sheng Shen, Pao-Ann Hsiung:
Reasoning and Learning-Based Dynamic Codec Reconfiguration for Varying Processing Requirements in Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 22(8): 1777-1790 (2014) - [c11]Jih-Sheng Shen, Pao-Ann Hsiung, Juin-Ming Lu:
Reconfigurable Network-on-chip design for heterogeneous multi-core system architecture. HPCS 2014: 523-526 - 2013
- [j5]Jih-Sheng Shen, Pao-Ann Hsiung, Chun-Hsian Huang:
Learning-based adaptation to applications and environments in a reconfigurable network-on-chip for reducing crosstalk and dynamic power consumption. Comput. Electr. Eng. 39(2): 453-464 (2013) - [c10]Hung-Lin Chao, Chun-Yang Peng, Cheng-Chien Wu, Ken-Shin Huang, Chun-Hsien Lu, Jih-Sheng Shen, Pao-Ann Hsiung:
Spatio-Temporally-Shared Reconfigurable Fast Fourier Transform architecture design. FPT 2013: 426-429 - 2011
- [c9]Wan-Ting Su, Jih-Sheng Shen, Pao-Ann Hsiung:
Network-on-Chip router design with Buffer-Stealing. ASP-DAC 2011: 160-164 - 2010
- [b1]Jih-Sheng Shen, Pao-Ann Hsiung:
Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication. IGI Global 2010, ISBN 978-1-61520-807-4, pp. I-XVII, 1-366 - [j4]Chun-Hsian Huang, Pao-Ann Hsiung, Jih-Sheng Shen:
UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems. J. Syst. Archit. 56(2-3): 88-102 (2010) - [j3]Chun-Hsian Huang, Pao-Ann Hsiung, Jih-Sheng Shen:
Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption. J. Syst. Archit. 56(11): 545-560 (2010) - [j2]Pao-Ann Hsiung, Chun-Hsian Huang, Jih-Sheng Shen, Cheng-Chi Chiang:
Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. 4(1): 9:1-9:32 (2010) - [c8]Jih-Sheng Shen, Chun-Hsian Huang, Pao-Ann Hsiung:
Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip. DATE 2010: 381-386 - [c7]Chun-Hsian Huang, Jih-Sheng Shen, Pao-Ann Hsiung:
A Self-Adaptive Hardware/Software System Architecture for Ubiquitous Computing Applications. UIC 2010: 382-396
2000 – 2009
- 2008
- [j1]Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen:
Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes. ACM Trans. Design Autom. Electr. Syst. 13(1): 12:1-12:31 (2008) - [c6]Jih-Sheng Shen, Pao-Ann Hsiung, Kuei-Chung Chang:
A novel spatio-temporal adaptive bus encoding for reducing crosstalk interferences with trade-offs between performance and reliability. ACSAC 2008: 1-8 - 2006
- [c5]Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen:
Fast Run-Time Power Monitoring Methodology for Embedded Systems. ESA 2006: 129-133 - [c4]Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen:
Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. DAC 2006: 143-148 - [c3]Jih-Sheng Shen, Kuei-Chung Chang, Tien-Fu Chen:
On a design of crossroad switches for low-power on-chip communication architectures. ISCAS 2006 - 2005
- [c2]Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen:
Crossroad System-on-Chip Communication Architecture for Low Power Embedded Systems. ESA 2005: 151-157 - [c1]Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen:
A low-power crossroad switch architecture and its core placement for network-on-chip. ISLPED 2005: 375-380
Coauthor Index
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