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Masato Motomura
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2020 – today
- 2024
- [j43]Junnosuke Suzuki
, Jaehoon Yu
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. IEEE Access 12: 2057-2073 (2024) - [j42]Shungo Kumazawa
Toward Improving Ensemble-Based Collaborative Inference at the Edge. IEEE Access 12: 6926-6940 (2024) - [j41]Satoru Jimbo
A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization. IEEE Access 12: 43660-43673 (2024) - [j40]Yuki Ichikawa
Efficient Stereo Visual Odometry on FPGA Featuring On-Chip Map Management and Pipelined Descriptor-Based Block Matching. IEEE Access 12: 171458-171471 (2024) - [j39]Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura:
Restricted Random Pruning at Initialization for High Compression Range. Trans. Mach. Learn. Res. 2024 (2024) - [c78]Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Progressive Variable Precision DNN With Bitwise Ternary Accumulation. AICAS 2024: 377-381 - [c77]Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu:
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow. ASPDAC 2024: 785-791 - [c76]Kyo Kuroki
Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization. GECCO 2024 - [c75]Yuki Ichikawa, Akihiro Shioda, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection. ICCE 2024: 1-2 - [c74]Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu:
Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA. ICCE 2024: 1-2 - [c73]Masato Watanabe, Shungo Kumazawa, Thiem Van Chu, Kazushi Kawamura, Jaehoon Yu, Masato Motomura:
Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA. ICCE 2024: 1-2 - [c72]Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
High Throughput Datapath Design for Vision Permutator FPGA Accelerator. ICCE 2024: 1-2 - [c71]Tsukasa Yamakura, Kazushi Kawamura, Masato Motomura, Thiem Van Chu:
ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data. IJCNN 2024: 1-8 - [c70]Masato Motomura:
RAW 2024 Invited Talk-5. IPDPS (Workshops) 2024: 87 - [i3]Hikari Otsuka
Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket. CoRR abs/2402.14029 (2024) - 2023
- [j38]Jiale Yan
TT-MLP: Tensor Train Decomposition on Deep MLPs. IEEE Access 11: 10398-10411 (2023) - [j37]Ángel López García-Arias
Recurrent Residual Networks Contain Stronger Lottery Tickets. IEEE Access 11: 16588-16604 (2023) - [j36]Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems. IEICE Trans. Inf. Syst. 106(12): 1969-1978 (2023) - [c69]Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance. COOL CHIPS 2023: 1-3 - [c68]Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura:
Decision Forest Training Accelerator Based on Binary Feature Decomposition. FCCM 2023: 215 - [c67]Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension. ISSCC 2023: 42-43 - [c66]Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Multicoated and Folded Graph Neural Networks With Strong Lottery Tickets. LoG 2023: 11 - [c65]Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura:
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations. MCSoC 2023: 478-485 - [c64]Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. VLSI Technology and Circuits 2023: 1-2 - [i2]Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka
Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets. CoRR abs/2312.03236 (2023) - 2022
- [j35]Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers. IEICE Trans. Inf. Syst. 105-D(12): 2019-2031 (2022) - [j34]Yafei Ou
Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark. IEEE Trans. Circuits Syst. Video Technol. 32(5): 2666-2686 (2022) - [c63]Pitchayapatchaya Srikram, Prasoon Ambalathankandy, Yuri Kanazawa, Masato Motomura, Masayuki Ikebe:
Ring-VCO-based ReLU activation function with linearity improvement for pulsed neuron circuits. ICECS 2022 2022: 1-4 - [c62]Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu:
Multicoated Supermasks Enhance Hidden Networks. ICML 2022: 17045-17055 - [c61]Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control. IPDPS Workshops 2022: 414-420 - [c60]Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. ISSCC 2022: 1-3 - 2021
- [j33]Kazutoshi Hirose
Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture. IEEE Access 9: 6179-6187 (2021) - [j32]Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu:
ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training. Int. J. Netw. Comput. 11(2): 215-230 (2021) - [j31]Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu:
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation. Int. J. Netw. Comput. 11(2): 338-353 (2021) - [j30]Kasho Yamamoto
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. IEEE J. Solid State Circuits 56(1): 165-178 (2021) - [j29]Kota Shiba
A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 692-703 (2021) - [c59]Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu:
Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. BMVC 2021: 205 - [c58]Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura:
A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning. FPT 2021: 1-10 - [c57]Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. HCS 2021: 1-21 - [i1]Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu:
Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. CoRR abs/2111.12330 (2021) - 2020
- [j28]Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda:
A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks. Int. J. Netw. Comput. 10(2): 84-93 (2020) - [j27]Prasoon Ambalathankandy
An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA. IEEE Trans. Circuits Syst. Video Technol. 30(9): 3015-3028 (2020) - [c56]Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura
Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs. ARC 2020: 345-357 - [c55]Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training. CANDAR 2020: 146-152 - [c54]Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation. CANDAR 2020: 215-220 - [c53]Kota Shiba
A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. ISCAS 2020: 1-5 - [c52]Kasho Yamamoto, Kota Ando, Normann Mertig
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. ISSCC 2020: 138-140
2010 – 2019
- 2019
- [j26]Masato Motomura
Foreword. IEICE Trans. Inf. Syst. 102-D(5): 1002 (2019) - [j25]Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai
FPGA-Based Annealing Processor with Time-Division Multiplexing. IEICE Trans. Inf. Syst. 102-D(12): 2295-2305 (2019) - [j24]Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. IEICE Trans. Inf. Syst. 102-D(12): 2341-2353 (2019) - [j23]Yohan Frans
Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 54(1): 3-5 (2019) - [j22]Kodai Ueyoshi
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. IEEE J. Solid State Circuits 54(1): 186-196 (2019) - [c51]Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura
DeltaNet: Differential Binary Neural Network. ASAP 2019: 39 - [c50]Prasoon Ambalathankandy
Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band. DICTA 2019: 1-8 - [c49]Yuki Hirayama, Tetsuya Asai, Masato Motomura
A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators. CANDAR 2019: 137-142 - 2018
- [j21]Aoi Tanibata
Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing. Complex. 2018: 3618621:1-3618621:11 (2018) - [j20]Kota Ando
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53(4): 983-994 (2018) - [j19]Prasoon Ambalathankandy
Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA. Microprocess. Microsystems 61: 21-31 (2018) - [c48]Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. FPT 2018: 6-13 - [c47]Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy
Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. ICASSP 2018: 1842-1846 - [c46]Dejan Markovic, Masato Motomura, Byeong-Gyu Nam:
Session 13 overview: Machine learning and signal processing: Digital architectures and systems subcommittee. ISSCC 2018: 214-215 - [c45]Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. ISSCC 2018: 216-218 - [c44]Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. MCSoC 2018: 237-243 - [c43]Prasoon Ambalathankandy
Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions. VCIP 2018: 1-4 - [c42]Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications. VLSI Circuits 2018: 41-42 - [p1]Masato Motomura, Masanori Hariyama, Minoru Watanabe:
Advanced Devices and Architectures. Principles and Structures of FPGAs 2018: 207-231 - 2017
- [j18]Takao Marukame, Kodai Ueyoshi, Tetsuya Asai
Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation. IEEE Trans. Circuits Syst. II Express Briefs 64-II(4): 462-466 (2017) - [c41]Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
Accelerating deep learning by binarized hardware. APSIPA 2017: 1045-1051 - [c40]Tomoya Fujii, Simpei Sato, Hiroki Nakahara
An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning. ARC 2017: 268-280 - [c39]Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura
An image sensor/processor 3D stacked module featuring ThruChip interfaces. ASP-DAC 2017: 7-8 - [c38]Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura:
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). FPGA 2017: 290 - [c37]Aoi Tanibata, Alexandre Schmid
FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. FPL 2017: 1 - [c36]Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
A Time-Division Multiplexing Ising Machine on FPGAs. HEART 2017: 3:1-3:6 - [c35]Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. CANDAR 2017: 291-297 - [c34]Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
Exploring optimized accelerator design for binarized convolutional neural networks. IJCNN 2017: 2510-2516 - [c33]Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura
Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA. ISCAS 2017: 1 - [c32]Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Tetsuya Asai, Masato Motomura
Low latency divider using ensemble of moving average curves. ISQED 2017: 397-402 - [c31]Meng-Fan Chang, Jun Deguchi, Vivek De, Masato Motomura, Shinichiro Shiratake, Marian Verhelst:
F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems. ISSCC 2017: 506-508 - [c30]Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara
In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS 2017: 116-119 - [c29]Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
Quantization Error-Based Regularization in Neural Networks. SGAI Conf. 2017: 137-142 - 2016
- [j17]Miho Ushida, Alexandre Schmid, Tetsuya Asai, Kazuyoshi Ishimura, Masato Motomura:
Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata. Int. J. Unconv. Comput. 12(2-3): 169-187 (2016) - [j16]Masato Motomura
Introduction to the Special Issue on the 2015 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 51(4): 787-788 (2016) - [c28]Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors. APCCAS 2016: 297-300 - [c27]Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura
Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces. ESSCIRC 2016: 105-108 - [c26]Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura
A memory-based realization of a binarized deep convolutional neural network. FPT 2016: 277-280 - [c25]Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura
Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network. ISCAS 2016: 357-360 - [c24]Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions. ReConFig 2016: 1-6 - [c23]Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting. ReConFig 2016: 1-6 - [c22]Jeffrey C. Gealow, Masato Motomura
Foreword. VLSI Circuits 2016: 1-2 - 2015
- [j15]Li-Chung Hsu, Masato Motomura
Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration. IEICE Trans. Electron. 98-C(4): 288-297 (2015) - [j14]Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai
Enhancing Memcached by Caching Its Data and Functionalities at Network Interface. J. Inf. Process. 23(2): 143-152 (2015) - [j13]Jeffrey C. Gealow
Introduction to the Special Issue on the 2014 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 50(4): 812-813 (2015) - [j12]Kamal El-Sankary, Tetsuya Asai
Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 726-730 (2015) - [c21]Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer. VLSIC 2015: 82- - 2014
- [j11]Lizeth Gonzalez-Carabarin, Tetsuya Asai
Low-power asynchronous digital pipeline based on mismatch-tolerant logic gates. IEICE Electron. Express 11(15): 20140632 (2014) - [c20]Itaru Hida, Dahoo Kim, Tetsuya Asai, Masato Motomura
A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator. A-SSCC 2014: 37-40 - [c19]Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
Caching memcached at reconfigurable network interface. FPL 2014: 1-6 - [c18]Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
Achieving higher performance of memcached by caching at network interface. FPT 2014: 288-289 - 2013
- [j10]Hiroaki Inoue, Takashi Takenaka, Masato Motomura
C-Based Complex Event Processing on Reconfigurable Hardware. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 971-974 (2013) - [c17]Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Taro Fujii, Koichiro Furuta, Tetsuya Asai, Masato Motomura
C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join. ARC 2013: 220 - [c16]Katsuki Ohata, Yukitoshi Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. ICECS 2013: 169-172 - [c15]Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Tetsuya Asai, Masato Motomura
Exploiting hardware reconfigurability on window join. HPCS 2013: 690-691 - [c14]Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura
A restricted dynamically reconfigurable architecture for low power processors. ReConFig 2013: 1-7 - 2011
- [j9]Hiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, Masato Motomura
Test compression for dynamically reconfigurable processors. ACM Trans. Reconfigurable Technol. Syst. 4(4): 40:1-40:15 (2011) - [c13]Masato Motomura, Takafumi Aoki, Toru Awashima, Toru Baji, Masaaki Ishikawa:
Panel discussions: Impact on society by fusion and harmony of mobile devices, servers, and networks - Their direction of evolutions and optimal roles. COOL Chips 2011: 1-2 - [c12]Hiroaki Inoue, Takashi Takenaka, Masato Motomura
20Gbps C-Based Complex Event Processing. FPL 2011: 97-102 - [c11]Makoto Miyamura, Shogo Nakaya, Munehiro Tada
Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS. ISSCC 2011: 228-229
2000 – 2009
- 2004
- [j8]Kenichiro Anjo, Atsushi Okamura, Masato Motomura
Wrapper-based bus implementation techniques for performance improvement and cost reduction. IEEE J. Solid State Circuits 39(5): 804-817 (2004) - [j7]Mahmoud Méribout
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems. IEEE Trans. Computers 53(12): 1508-1522 (2004) - [j6]Mahmoud Méribout
Efficient metrics and high-level synthesis for dynamically reconfigurable logic. IEEE Trans. Very Large Scale Integr. Syst. 12(6): 603-621 (2004) - [c10]Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. FCCM 2004: 328-329 - [c9]Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima:
Stream applications on the dynamically reconfigurable processor. FPT 2004: 137-144 - 2003
- [j5]Mahmoud Méribout, Masato Motomura:
A Hierarchical Cost Estimation Technique for High Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(2): 444-461 (2003) - [j4]Mahmoud Méribout, Masato Motomura
New design methodology with efficient prediction of quality metrics for logic level design towards dynamic reconfigurable logic. J. Syst. Archit. 48(8-10): 285-310 (2003) - [c8]Mahmoud Méribout, Masato Motomura:
A New Hardware Algorithm for Fast IP Routing Targeting Programmable Routers. Net-Con 2003: 164-179 - [c7]Mahmoud Méribout
A New Reconfigurable Hardware Architecture for High Throughput Networking Applications and its Design Methodology. IPDPS 2003: 182 - 2000
- [c6]Masakazu Yamashina, Masato Motomura
Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk. ASP-DAC 2000: 329-332 - [c5]Koichiro Furuta, Taro Fujii, Masato Motomura, Kazutoshi Wakabayashi, Masakazu Yamashina:
Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI. CICC 2000: 151-154 - [c4]Yuichiro Shibata, Masaki Uno, Hideharu Amano, Koichiro Furuta, Taro Fujii, Masato Motomura
A Virtual Hardware System on a Dynamically Reconfigurable Logic Device. FCCM 2000: 295-296 - [c3]Lars Friebe, Yoshikazu Yabe, Masato Motomura:
A Study of Channeled DRAM Memory Architectures. ICCD 2000: 261-266
1990 – 1999
- 1998
- [j3]Hiroyuki Igura, Yukihiro Naito, Kenya Kazama, Ichiro Kuroda, Masato Motomura
An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing. IEEE J. Solid State Circuits 33(11): 1820-1828 (1998) - [c2]Masato Motomura
An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration. FCCM 1998: 264-266 - 1995
- [j2]Masato Motomura
Cache-processor coupling: a fast and wide on-chip data cache design. IEEE J. Solid State Circuits 30(4): 375-382 (1995) - [c1]Masato Motomura, Toshiaki Inoue, Sunao Torii, Akihiko Konagaya:
Ordered multithreading: a novel technique for exploiting thread-level parallelism. PACT 1995: 37-48 - 1994
- [j1]Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura
A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI. IEEE J. Solid State Circuits 29(3): 290-297 (1994)
Coauthor Index
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