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EURO-DAC 1996: Geneva, Switzerland
- Graham Symonds, Wolfgang Nebel:
Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996. IEEE Computer Society Press 1996, ISBN 0-8186-7573-X
Analog and Mixed Mode Simulation
- Mona M. Ahmed, Hani F. Ragaie, Hisham Haddara:
A hierarchical approach to analog behavioral modeling of neural networks using HDL-A. 2-9 - Ulrich Bretthauer, Ernst-Helmut Horneber:
BRASIL: the Braunschweig mixed-mode-simulator for integrated circuits. 10-14 - Vladimir B. Dmitriev-Zdorov:
Generalized coupling as a way to improve the convergence in relaxation-based solvers. 15-20
Low Power Synthesis
- Matthias A. Senn, Peter H. Schneider, Bernd Wurth:
Power analysis for sequential circuits at logic level. 22-27 - Manfred Koegst, Klaus Feske, Günter Franke:
State assignment for FSM low power design. 28-33
Design Experience
- Jürgen Bortolazzi, Thomas Hirth, Thomas Raith:
Specification and design of electronic control units. 36-41 - Mohamed Abid, Adel Changuel, Ahmed Amine Jerraya:
Exploration of hardware/software design space through a codesign of robot arm controller. 42-47 - Adel Changuel, Ahmed Amine Jerraya, Robin Rolland:
Design of an adaptive motors controller based on fuzzy logic using behavioral synthesis. 48-52 - Valentina Salapura, Volker Hamann:
Implementing fuzzy control systems using VHDL and statecharts. 53-58 - T. Murayama, Yuji Gendai
:
A top down mixed-signal design methodology using a mixed-signal simulator and analog HDL. 59-64
Timing Modeling
- Dirk Rabe, Wolfgang Nebel:
New approach in gate-level glitch modelling. 66-71 - Bernhard Wunder, Gunther Lehmann, Klaus D. Müller-Glaser:
A new concept for accurate modeling of VLSI interconnections and its application for timing simulation. 72-77 - Rhodri M. Davies, John V. Woods:
Timing verification for asynchronous design. 78-83
Design Flow and Design Management
- Andrew Seawright, Joseph Buck, Ulrich Holtmann, Wolfgang Meyer, Barry M. Pangrle, Rob Verbrugghe:
A system for compiling and debugging structured data processing controllers. 86-91 - Claus Mayer, Jörg Pleickhardt, Hans Sahm:
A graphical data management system for HDL-based ASIC design projects. 92-97 - Michael Ryba, Utz G. Baitinger:
An integrated concept for design project planning and design flow control. 98-103 - Vladimir A. Shepelev, Stephen W. Director:
Automatic workflow generation. 104-109
Partitioning
- Giovanni De Micheli, Vincent John Mooney III, Claudionor Nunes Coelho, Toshiyuki Sakamoto:
Synthesis from mixed specifications. 114-119 - Markus Schwiegershausen, Holger Kropp, Peter Pirsch:
A system level HW/SW partitioning and optimization tool. 120-125 - Masaharu Imai, Nguyen-Ngoc Bình, Akichika Shiomi:
A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs. 126-131
Logic & FSM Synthesis
- Heinz-Josef Eikerling, Wolfgang Rosenstiel:
Automatic structuring and optimization of hierarchical designs. 134-139 - Andrew Crews, Forrest Brewer
Controller optimization for protocol intensive applications. 140-145 - J. Bullmann, Wolfgang Rosenstiel, Endric Schubert, Udo Kebschull:
Library based technology mapping using multiple domain representations. 146-150
BDD Optimization Techniques
- Stefan Höreth:
Compilation of optimized OBDD-algorithms. 152-157 - Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer, Robert K. Brayton, Ellen Sentovich:
Incremental re-encoding for symbolic traversal of product machines. 158-163 - Andreas Hett, Bernd Becker, Rolf Drechsler:
MORE: an alternative implementation of BDD packages by multi-operand synthesis. 164-169 - Stefano Quer, Gianpiero Cabodi, Paolo Camurati:
Decomposed symbolic forward traversals of large finite state machines. 170-175
Codesign Methodology and Cospecification
- Michael J. Knieser, Christos A. Papachristou:
COMET: a hardware-software codesign methodology. 178-183 - Christian Veith, Klaus Buchenrieder
Mapping statechart models onto an FPGA-based ASIP architecture. 184-189 - Armin Bender:
MILP based task mapping for heterogeneous multiprocessor systems. 190-197
System Level Design & Synthesis
- Rainer Leupers, Peter Marwedel:
Instruction selection for embedded DSPs with complex instructions. 200-205 - Sanjiv Narayan, Daniel D. Gajski:
Rapid performance estimation for system design. 206-211 - Vinoo Srinivasan, Nand Kumar, Ranga Vemuri:
Hierarchical behavioral partitioning for multicomponent synthesis. 212-217
New Aspects on Testing
- Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar:
Testable path delay fault cover for sequential circuits. 220-226 - Arno Kunzmann:
Efficient random testing with global weights. 227-232 - Paolo Prinetto, Fulvio Corno, Matteo Sonza Reorda
Fault tolerant and BIST design of a FIFO cell. 233-238 - M. Robson, G. Russell:
A digital method for testing embedded switched capacitor filters. 239-244
Codesign Methodology & Cosimulation
- Georg Pelz, Jürgen Bielefeld, Günther Hess, Günter Zimmer:
Hardware/software-cosimulation for mechatronic system design. 246-251 - Karl van Rompaey, Ivo Bolsens, Hugo De Man, Diederik Verkest:
CoWare - a design environment for heterogenous hardware/software systems. 252-257 - Yankin Tanurhan, H. Gölz, Stefan Schmerler, Klaus D. Müller-Glaser:
An approach for integrated specification and design of real-time systems. 258-263 - D. Gareth Evans, Peter N. Green, Derrick Morris:
An integrated approach to engineering computer systems. 264-269
Key Technologies and CAD of Microsystems
- Stephanus Büttgenbach:
Spotlights on recent developments in microsystem technology. 274-279 - Klaus D. Müller-Glaser:
CAD of microsystems - a challenge for system engineering. 280-281
Asynchronous Synthesis and Storage Optimization
- Peter A. Beerel, Wei-Chun Chou, Kenneth Y. Yun:
A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits. 284-289 - Kenneth Y. Yun:
Automatic synthesis of extended burst-mode circuits using generalized C-elements. 290-295 - Youn-Long Lin, Tsung-Yi Wu:
Storage optimization by replacing some flip-flops with latches. 296-301 - Sabih H. Gerez
Assignment of storage values to sequential read-write memories. 302-307
Modelling, Simulation of Microsystems and Multi Layer Routing in PCBs
- Ivan Hom, John J. Granacki:
Estimation of the number of routing layers and total wirelength in a PCB through wiring distribution analysis. 310-315 - Zeljko Mrcarica, Helmut Detter, Dejan Glozic, Vanco B. Litovski:
Describing space-continuous models of microelectromechanical devices for behavioral simulation. 316-321 - Wolfgang Süß, Horst Eggert, Martina Gorges-Schleuter, Wilfried Jakob, S. Meinzer, Alexander Quinte:
Simulation and design optimization of microsystems based on standard simulators and adaptive search techniques. 322-327
Timing Issues in Synthesis
- Hsiao-Ping Juan, Smita Bakshi, Daniel D. Gajski:
Clock optimization for high-performance pipelined design. 330-335 - Christos A. Papachristou, Mehrdad Nourani:
False path exclusion in delay analysis of RTL-based datapath-controller designs. 336-341 - Luis Entrena, Emilio Olías, Javier Uceda, José Alberto Espejo:
Timing optimization by an improved redundancy addition and removal technique. 342-347
Physical Design for Deep Submicron
- Takashi Mitsuhashi, Masami Murakata, Kenji Yoshida, Takahiro Aoki:
Physical design CAD in deep sub-micron era. 350-355 - Henrik Esbensen, Ernest S. Kuh:
EXPLORER: an interactive floorplanner for design space exploration. 356-361 - Mitsuho Seki, Kazuo Kato, S. Kobayashi, Kouki Tsurusaki:
A practical clock router that accounts for the capacitance derived from parallel and cross segments. 362-367
Architectural Synthesis Techniques
- Smita Bakshi, Daniel D. Gajski, Hsiao-Ping Juan:
Component selection in resource shared and pipelined DSP applications. 370-375 - Massoud Pedram, Jui-Ming Chang:
Module assignment for low power. 376-381 - Mariagiovanna Sami, Anna Antola, Vincenzo Piuri:
A high-level synthesis approach to optimum design of self-checking circuits. 382-387
CAD for Analog Circuit
- Bogdan G. Arsintescu, Sorin A. Spânoche:
Global stacking for analog circuits. 392-397 - Tobias H. Abthoff, Frank M. Johannes:
TINA: analog placement using enumerative techniques capable of optimizing both area and net length. 398-403
Analysis Tools
- Donatella Sciuto, Luciano Baresi
Software methodologies for VHDL code static analysis based on flow graphs. 406-411 - Gunther Lehmann, Klaus D. Müller-Glaser, Bernhard Wunder:
A VHDL reuse workbench. 412-417 - Franz J. Rammig:
Beyond VHDL: textual formalisms, visual techniques, or both? 420-427
Beyond VHDL
- Guido Schumacher, Wolfgang Nebel:
Object-oriented hardware modelling - where to apply and what are the objects? 428-433 - Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli:
Hardware/software partitioning of VHDL system specifications. 434-439
Fault Modeling and Design for Testability
- Enrico Macii, Massimo Poncino, Fabrizio Ferrandi
BDD-based testability estimation of VHDL designs. 444-449 - João Paulo Teixeira, F. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos:
VHDL fault simulation for defect-oriented test and diagnosis of digital ICs. 450-455 - Eduardo de la Torre, J. Calvo, Javier Uceda:
Model generation of test logic for macrocell based designs. 456-461 - Teresa Riesgo, Javier Uceda:
A fault model for VHDL descriptions at the register transfer level. 462-467 - Wendell C. Baker, A. Richard Newton:
The maximal VHDL subset with a cycle-level abstraction. 470-475 - Ayman M. Wahba, Dominique Borrione:
Automatic diagnosis may replace simulation for correcting simple design errors. 476-481 - Peter T. Breuer
A refinement calculus for VHDL. 482-487
Modeling Methodologies
- Maher Rahmouni, Ahmed Amine Jerraya, Polen Kission, Antonio Carneiro de Mesquita Filho, Aloysio Pedroza, Luci Pirmez:
Analysis of different protocol description styles in VHDL for high-level synthesis. 490-495 - Konrad Feyerabend, Rainer Schlör:
Hardware synthesis from requirement specifications. 496-501 - Ekambaram Balaji, Prabhu Krishnamurthy:
Modeling ASIC memories in VHDL. 502-508 - Claus Schneider, Wolfgang Ecker:
Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionality. 509-514
Synthesis
- Krzysztof Bilinski, Erik L. Dagless, Jaroslaw Mirkowski:
Synchronous parallel controller synthesis from behavioural multiple-process VHDL description. 516-521 - Francesco Curatelli, Marco Chirico, Leonardo Mangeruca:
Specification and management of timing constraints in behavioral VHDL. 522-527 - Kevin O'Brien, Serge Maginot, Anne Robert:
Towards maximising the use of structural VHDL for synthesis. 528-533
System Level Design
- Paolo Prinetto, Alfredo Benso, Fulvio Corno
Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment. 536-541 - Ambar Sarkar:
System design using an integrated specification and performance modeling methodology. 542-547 - Michael Gschwind, Dietmar Maurer:
An extendable MIPS-I processor kernel in VHDL for hardware/software co-design. 548-553
VHDL & Mixed Signal Design
- Ernst Christen, Kenneth Bakalar:
VHDL 1076.1 - analog and mixed signal extensions to VHDL. 556-561 - C.-J. Richard Shi:
Entity overloading for mixed-signal abstraction in VHDL. 562-567 - Christoph Grimm, Klaus Waldschmidt:
KIR - a graph-based model for description of mixed analog/digital systems. 568-573
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