Article

Free access

Assignment of storage values to sequential read-write memories

Authors:

S. Gerez,

E. WoutersenAuthors Info & Claims

EURO-DAC '96/EURO-VHDL '96: Proceedings of the conference on European design automation

Pages 302 - 307

Published: 20 September 1996 Publication History

PDF eReader

References

[1]

M. Aloqeely and C.Y.R. Chen. A new technique for exploiting regularity in data path synthesis. In European Design Automation Conference, EURO-DAC, pages 394-399, 1994.

Digital Library

Google Scholar

[2]

I.E. Bennour and E.M. Aboulhamid. Register allocation using circular FIFOs. In International Symposium on Circuits and Systems, pages 560-563, 1996.

Crossref

Google Scholar

[3]

G. De Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York, 1994.

Digital Library

Google Scholar

[4]

D.D. Gajski, N.D. Dutt, A.C.H. Wu, and S.Y.L. Lin. High- Level Synthesis, Introduction to Chip and System Design. Kluwer Academic Publishers, Boston, 1992.

Digital Library

Google Scholar

[5]

S.H. Gerez and E.G. Woutersen. A high-level synthesis tool for the assignment of storage values to sequential read-write memories. In IFIP TC 10 WG 10.5 International Workshop on Logic and Architecture Synthesis, pages 220-230, Grenoble, December 1995.

Google Scholar

[6]

B.S. Haroun and M.I. Elmasry. Architechtural synthesis for DSP silicon compilers. IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, 8(4):431- 447, April 1989.

Digital Library

Google Scholar

[7]

S.M. Heemstra de Groot, S.H. Gerez, and O.E. Herrmann. Range-chart-guided iterative data-flow-graph scheduling. IEEE Transactions on Circuits and Systems I: Fundamental Theo17 and Applications, 39:351-364, May 1992.

Crossref

Google Scholar

[8]

A. Heubi, M. Ansorge, and F. Pellandini. Architecture VLSI faible consommation pour le traitement numdrique du signal. In Proceedings GRETSI '93, pages 1083-1086, Juanles-Pins, France, September 1993.

Google Scholar

[9]

A. Heubi, S. Grassi, M. Ansorge, and F. Pellandini. A low power VLSI architecture with an application to adaptive algorithms for digital hearing aids. In M.J.J. Holt, C.EN. Cowan, RM. Grant, and W.A. Sandham, editors, Signal Processing VII: Theories and Applications (Proceedings of the EUSIPCO-94 Seventh Eulvpean Signal Processing Conference), pages 1875-1878, 1994.

Google Scholar

[10]

H.A. Hilderink and J.A.G. Jess. Rom-based multi thread controller. In IFIP Workshop on Logic and Architecture Synthesis, pages 231-241, Grenoble, December 1993.

Google Scholar

[11]

E. Horowitz and S. Sahni. Fundamentals of Computer Algorithms. Computer Science Press, Rockville, Maryland, 1978.

Digital Library

Google Scholar

[12]

S. Kirkpatrick, C.D. Gelatt, and M.P. Vecchi. Optimization by simulated annealing. Science, 220(4598):671-690, May 1983.

Crossref

Google Scholar

[13]

J.L. van Meerbergen, RE.R. Lippens, W.F.J. Verhaegh, and A. van der Werf. Relative location assignment for repetitive schedules. In Ewvpean Conference on Design Automation with the Eulvpean Event on ASIC Design, EDAC/EUROASIC, pages 403-407, 1993.

Google Scholar

[14]

K.K. Parhi. Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation. IEEE Transactions on Circuit and Systems - II: Analog and Digital Signal Processing, 39(7):423-440, July 1992.

Crossref

Google Scholar

[15]

K.K. Parhi and D.G. Messerschmitt. Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding. IEEE Transactions on Computers, 40(2):178-195, February 1991.

Digital Library

Google Scholar

[16]

L. Stok and J.A.G. Jess. Foreground memory management in data path synthesis. International Journal of Circuit Theo17 and Applications, 20:235-255, 1992.

Google Scholar

[17]

E.G. Woutersen. The application of sequential read-write memories in high-level synthesis. Master's thesis, University of Twente, Department of Electrical Engineering, Laboratory of Network Theory, December 1995. EL-BSC- 097N95.

Google Scholar

[18]

E.G. Woutersen and S.H. Gerez. Some complexity results in memory mapping. In Third HCM BELSIGN Workshop, Corsica, April 1996.

Google Scholar

[19]

E.G. Woutersen and S.H. Gerez. The application of sequential read-write memories in high-level synthesis. In GRONICS ' 96: Groningen Information Technology Conference for Students, pages 93-100, Groningen, The Netherlands, February 1996.

Google Scholar

Cited By

View all

Mamidipaka MDutt N(2003)On-chip Stack Based Memory Organization for Low Power Embedded ArchitecturesProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022866Online publication date: 3-Mar-2003
https://dl.acm.org/doi/10.5555/789083.1022866
Hettiaratchi SCheung PClarke T(2002)Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled MemoryProceedings of the conference on Design, automation and test in Europe10.5555/882452.874333Online publication date: 4-Mar-2002
https://dl.acm.org/doi/10.5555/882452.874333

Index Terms

Assignment of storage values to sequential read-write memories
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Integrated circuits
    1. Logic circuits
      1. Sequential circuits
    2. Semiconductor memory

Recommendations

Transactional Read-Modify-Write Without Aborts

Language-level transactions are said to provide “atomicity,” implying that the order of operations within a transaction should be invisible to concurrent transactions and thus that independent operations within a transaction should be safe to execute in ...
Write-rationing garbage collection for hybrid memories
PLDI 2018: Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation

Emerging Non-Volatile Memory (NVM) technologies offer high capacity and energy efficiency compared to DRAM, but suffer from limited write endurance and longer latencies. Prior work seeks the best of both technologies by combining DRAM and NVM in hybrid ...
DedupHR: Exploiting Content Locality to Alleviate Read/Write Interference in Deduplication-Based Flash Storage
Data deduplication has been widely employed in flash-based storage as an effective technique for enhancing reliability and cost efficiency. However, the read/write interference problem of flash storage, where on-going write requests prevent read requests ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

EURO-DAC '96/EURO-VHDL '96: Proceedings of the conference on European design automation

September 1996

604 pages

ISBN:081867573X

Chairmen:
Graham Symonds
Viewlogic Systems Ltd., Bracknell, Berkshire, UK
,
Wolfgang Nebel
Carl-von-Ossietzky Univ., Oldenburg, Germany

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 20 September 1996

Check for updates

Qualifiers

Article

Conference

EuroDAC95

Sponsor:

SI-G
EDAC
SIGDA
IEEE-CS
IFIP

EuroDAC95: European Design Automation Conference

Geneva, Switzerland

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
136
Total Downloads

Downloads (Last 12 months)32
Downloads (Last 6 weeks)12

Reflects downloads up to 08 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Mamidipaka MDutt N(2003)On-chip Stack Based Memory Organization for Low Power Embedded ArchitecturesProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022866Online publication date: 3-Mar-2003
https://dl.acm.org/doi/10.5555/789083.1022866
Hettiaratchi SCheung PClarke T(2002)Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled MemoryProceedings of the conference on Design, automation and test in Europe10.5555/882452.874333Online publication date: 4-Mar-2002
https://dl.acm.org/doi/10.5555/882452.874333

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Transactional Read-Modify-Write Without Aborts

Write-rationing garbage collection for hybrid memories

DedupHR: Exploiting Content Locality to Alleviate Read/Write Interference in Deduplication-Based Flash Storage