A practical clock router that accounts for the capacitance derived from parallel and cross segments

In deep sub-micron fabrication technology, clock skew is one of the dominant factors which determine system performance. Previous works in zero skew clock tree routing assume that the wires have uniform size, and previous wire-sizing algorithms for ...

With the continuous increase of circuit density, interconnect length, and aspect ratio, the influence of capacitive and inductive coupling on timing characteristics of integrated circuits has become very critical. In this paper, the effects of ...

Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approach to overcome the variation problem. Existing non-tree clock routing ...