default search action
44th ESSCIRC 2018: Dresden, Germany
- 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, Dresden, Germany, September 3-6, 2018. IEEE 2018, ISBN 978-1-5386-5404-0
- Udo Gomez:
Smart Connected Sensors - Enablers for the IoT. 1 - Gary L. Patton:
Unleashing Technology Solutions for a New Era of Connected Intelligence. 2 - Baher Haroun:
Autonomous Vehicles Sensor Needs. 3 - Evangelos Eleftheriou:
"In-memory Computing": Accelerating AI Applications. 4-5 - Borivoje Nikolic
, Elad Alon, Krste Asanovic:
Generating the Next Wave of Custom Silicon. 6-11 - Georg Sigl, Mathieu Gross, Michael Pehl:
Where Technology Meets Security: Key Storage and Data Separation for System-on-Chips. 12-17 - Haoming Xin, Martin Andraud
A 0.1nW -1µW All-Dynamic Capacitance-to-Digital Converter with Power/Speed/Capacitance Scalability. 18-21 - Shaolong Liu, Jeyanandh Paramesh, Larry T. Pileggi, Taimur Gibran Rabuske
A 125 MS/s 10.4 ENOB 10.1 fJ/Conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS. 22-25 - Marcel Runge, Dario Schmock, Philipp Scholz, Georg Böck, Friedel Gerfers:
A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS. 26-29 - Elbert Bechthum, Mohieddine El Soussi, Johan Dijkhuis, Paul Mateman, Gert-Jan van Schaik, Arjan Breeschoten, Yao-Hong Liu
A CMOS Polar Single-Supply Class-G SCPA for LTE NB-IoT and Cat-M1. 30-33 - See Taur Lee, Abdellatif Bellaouar, Sherif H. K. Embabi:
A Low-Power, Compact 76-81GHz FMCW Transmitter for Automotive Radar in 22nm FDSOI. 34-37 - Chongyu Yu, Jun Feng, Dixian Zhao:
A 28-GHz CMOS Broadband Single-Path Power Amplifier with 17.4-dBm P1dB for 5G Phased-Array. 38-41 - Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, Shanthi Pavan:
Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting. 42-45 - Elly De Pelecijn
A Fully Integrated Switched-Capacitor Based AC-DC Converter for a 120VRMS Mains Interface. 46-49 - Hyeonji Lee, Eunsang Jang, Hassan Saif, Yongmin Lee
A Sub-nW Fully Integrated Switched-Capacitor Energy Harvester for Implantable Applications. 50-53 - Robert K. Henderson, Nick Johnston, Haochang Chen, David Day-Uei Li, Graham Hungerford, Richard Hirsch, David McLoskey, Philip Yip, David J. S. Birch:
A 192×128 Time Correlated Single Photon Counting Imager in 40nm CMOS Technology. 54-57 - Masato Osawa, S. Hiraide, S. Suzuki, H. Kato, Kosei Tamiya, Yasunari Harada, Kuba Raczkowski, J. L. Bacq, Peter Van Wesemael, M. Liu, Annachiara Spagnolo, K. De Munck, S. Guerrieri, Jonathan Borremans:
An Adaptive Frame Image Sensor with Fine-Grained Power Management for Ultra-Low Power Internet of Things Application. 58-61 - Laurent Millet, Margaux Vigier, Gilles Sicard, Wilfried Uhring
A 5 Million Frames Per Second 3D Stacked Image Sensor With In-Pixel Digital Storage. 62-65 - Naser Mousavi, Zhiheng Wang, Ramesh Harjani:
A 0.4-1.0GHz, 47MHop/S Frequency Hopped TXR Front-End with 20dB in-Band Blocker Rejection. 66-69 - Ashwin Raghunathan, Thomas H. Lee:
A 125 pJ/hit 5 mW 28 GHz Superregenerative Receiver with Automatic Gain Control and Energy Efficient Startup for Burst Mode IoE Applications. 70-73 - Kuangyuan Ying, Carlos A. M. Costa Júnior, Bindi Wang, Dusan M. Milosevic, Hao Gao, Peter G. M. Baltus:
A Reconfigurable Receiver with 38 dB Frequency-Independent Blocker Suppression and Enhanced in-B and Linearity and Power Efficiency. 74-77 - Umanath Kamath, Edward Cullen, John Jennings, Ionut Cical, Darragh Walsh, Peng Lim, Brendan Farley, Robert Bogdan Staszewski
A 1 V Bandgap Reference in 7-nm FinFET with a Programmable Temperature Coefficient and an Inaccuracy of ±0.2% from -45°C to 125°C. 78-81 - Yuwei Wang, Ruizhi Zhang, Quan Sun, Hong Zhang:
A 0.5 V, 650 pW, 0.031%/V Line Regulation Subthreshold Voltage Reference. 82-85 - Teerasak Lee
An MF Energy Harvesting Receiver with Slow QPSK Control Data Demodulator for Wide Area Low Duty Cycle Applications. 86-89 - Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Kam Krisnnamurthy:
34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms. 90-93 - Tianyu Jia, Russ Joseph, Jie Gu:
An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. 94-97 - Vikram B. Suresh, Sudhir Satpathy, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS. 98-101 - Kevin Cushon, Per Larsson-Edefors, Peter A. Andrekson:
A High-Throughput Low-Power Soft Bit-Flipping LDPC Decoder in 28 nm FD-SOI. 102-105 - Sashank Krishnamurthy, Filip Maksimovic, Ali M. Niknejad:
580µW 2.2-2.4GHz Receiver with +3.3dBm Out-of-Band IIP3 for IoT Applications. 106-109 - Qingrui Meng, Ramesh Harjani:
A 4GHz Instantaneous Bandwidth Low Squint Phased Array Using Sub-Harmonic ILO Based Channelization. 110-113 - Bart Philippe
A Quadrature Phase Detector in 28nm CMOS for Differential mm-Wave Sensing Applications Using Dielectric Waveguides. 114-117 - Michael Hanhart, Soheil Aghaie, Stefan Dietrich, Tobias Zekorn, Ralf Wunderlich, Stefan Heinen:
A 16.5 W Single-Inductor 4-Channel Multi-Color Output DC-DC Buck LED Driver with Digital Control and 96 % Efficiency. 118-121 - Li-Cheng Chu, Shao-Qi Chen, Ke-Horng Chen
A Pseudo-Ramp Controlled Three Level Buck Converter with an Auto-Ripple Cancellation Technique for Low Output Voltage Ripple in Sub-Threshold Applications. 122-125 - Daniel Lutz, Achim Seidel, Bernhard Wicht:
A 50V, 1.45ns, 4.1pJ High-Speed Low-Power Level Shifter for High-Voltage DCDC Converters. 126-129 - Samuel Quenzer-Hohmuth, Steffen Ritzmann, Thoralf Rosahl, Bernhard Wicht:
A Boost Converter with 3-6V Input and Fast Transient Digital Control Comprising a 90 ns-Latency Live-Tracking Window ADC. 130-133 - Zexi Ji, Saba Zargham, Antonio Liscidini
Low-Power QPSK Transmitter Based on an Injection-Locked Power Amplifier. 134-137 - J. Rimmelspacher, Robert Weigel, Amelie Hagelauer
A Quad-Core 60 GHz Push-Push 45 nm SOI CMOS VCO with -101.7 dBc/Hz Phase Noise at 1 MHz offset, 19 % Continuous FTR and -187 dBc/Hz FoMT. 138-141 - Yuan Liang, Hao Yu, Chirn Chye Boon, Chenyang Li, Dietmar Kissinger, Yong Wang:
D-Band Surface-Wave Modulator and Signal Source with 40 dB Extinction Ratio and 3.7mW Output Power in 65 nm CMOS. 142-145 - Jahoon Jin
A 4.0-10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-Tolerant, and Harmonic-Lock-Free Frequency Acquisition Technique. 146-149 - Ningxi Liu, Rishika Agarwala, Anjana Dissanayake
A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-up Time. 150-153 - Jiangyi Li, Pavan Kumar Chundi, Sung Kim, Zhewei Jiang, Minhao Yang, Joonseong Kang, Seungchul Jung, Sang Joon Kim, Mingoo Seok:
A 0.78-µW 96-Ch. Deep Sub-Vt Neural Spike Processor Integrated with a Nanowatt Power Management Unit. 154-157 - Sae Kyu Lee, Paul N. Whatmough, Niamh Mulholland
A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET. 158-161 - Hsi-Shou Wu, Zhengya Zhang
A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks. 162-165 - Juan Sebastian Piedrahita Giraldo, Marian Verhelst
Laika: A 5uW Programmable LSTM Accelerator for Always-on Keyword Spotting in 65nm CMOS. 166-169 - Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, Chuanjin Richard Shi:
iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS. 170-173 - Pen-Jui Peng
A 50-Gb/s Quarter-Rate Voltage-Mode Transmitter with Three-Tap FFE in 40-nm CMOS. 174-177 - Abishek Manian, Amit Rane, Yongseon Koh:
A Simultaneous Bidirectional Single-Ended Coaxial Link with 24-Gb/s Forward and 312.5-Mb/s Back Channels. 178-181 - Gautam R. Gangasani, Peter R. Kinget:
A 19Gb/s RX for VSR-C2C Links with Clock-Less DFE and High-BW CDR Based on Master-Slave ILOs in 14nm CMOS. 182-185 - Bob Schell, Robert Bishop, Jack Kenney:
A 3-12.5 Gb/s Reference-Less CDR for an Eye-Opening Monitor. 186-189 - Said Hussaini, Hui Jiang
A 15nW Per Button Noise-Immune Readout IC for Capacitive Touch Sensor. 190-193 - Nikolaos Papadopoulos, Soeren Steudel, Florian De Roose, Doaa M. Eigabry, Auke Jisk Kronemeijer, Jan Genoe
In-Panel 31.17dB 140kHz 87µW Unipolar Dual-Gate In-Ga-Zn-O Charge-Sense Amplifier for 500dpi Sensor Array on Flexible Displays. 194-197 - Christopher Rogi, Enrique Prefasi
A Low-Power Auto-Zero Switched-Capacitor Dual-Slope Noise-Shaping Direct CDC. 198-201 - Anthony Quelen, Guilherme Migliato Marega
LDO-Assisted Voltage Selector Over 0.5-to-1V VDD Range for Fine Grained DVS in FDSOI 28nm with 200ns/V Controlled Transition. 202-205 - Junyao Tang, Chenchang Zhan, Guanhua Wang, Yang Liu
A 0.7V Fully-on-Chip Pseudo-Digital LDO Regulator with 6.3μA Quiescent Current and 100mV Dropout Voltage in 0.18-μm CMOS. 206-209 - Younghyun Lim
A 320µV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector. 210-213 - David L. Harame:
RF FDSOI Technology and Modelling. 214 - Andreia Cathelin:
FD-SOI Integration Solutions for Analog, RF and Millimeter-Wave Applications. 215 - Edith Beigné:
FDSOI Circuit Design for High Energy Efficiency: Wide Operating Range and ULP Applications - a 7-Year Experience. 216 - Marian Verhelst:
Exploiting FDSOI Towards Minimum Energy Point Operation in Processors and Machine Learning Accelerators. 217 - Lei Zeng, Chun-Huat Heng:
A Dual Loop 8-Channel ECG Recording System with Fast Settling Mode. 218-221 - Mohammad Zulqarnain
A 52 µW Heart-Rate Measurement Interface Fabricated on a Flexible Foil with A-IGZO TFTs. 222-225 - Reza Ranjandish
All Wireless, 16-Channel Epilepsy Control System with Sub-µW/Channel and Closed-Loop Stimulation Using a Switched-Capacitor-Based Active Charge Balancing Method. 226-229 - Vincent W. Leung
A CMOS Distributed Sensor System for High-Density Wireless Neural Implants for Brain-Machine Interfaces. 230-233 - Yang Zhang, Maxime De Wit, Patrick Reynaert:
A D-band Foam-Cladded Dielectric Waveguide Communication Link with Automatic Tuning. 234-237 - Roel Uytterhoeven, Wim Dehaene:
A sub 10 pJ/Cycle Over a 2 to 200 MHz Performance Range RISC- V Microprocessor in 28 nm FDSOI. 236-239 - Hao Li, Ganesh Balamurugan, James E. Jaussi, Bryan Casper:
A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS. 238-241 - Wouter Diels, Michiel Steyaert
A 1310/1550 nm Fully-Integrated Optical Receiver with Schottky Photodiode and Low-Noise Transimpedance Amplifier in 40 nm Bulk CMOS. 242-245 - Jens Sauerbrey, Jacinto San Pablo Garcia, Udo Schutz, Hasham Khushk, John G. Kauffman:
A Multi-mode GSM to LTE100 ADC. 246-249 - Shankarram Athreya, Hiva Hedayati, Shayan Kazemkhani, Yanfei Chen, Saurabh Vats, Michael D. Scott, Bart Zeydel, Peter Keller, Jian Wang, Bhaskarareddy Avula, Boris Murmann, Echere Iroaga:
Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver. 250-253 - Chi-Hang Chan, Yan Zhu, Zi-Hao Zheng, Rui Paulo Martins:
A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end. 254-257 - Borivoje Nikolic:
Energy-Efficient Design in FDSOI. 258 - Sarin Voinigescu:
mm W and High Speed Solutions Enabled by FD-SOI. 259 - Vadim Issakov:
Circuit Design Challenges of Highly-Integrated mm-Wave Radar-Based Sensors in SOI Based Technologies. 260 - Anirban Bandyopadhyay:
FD-SOI Enabled mmWave Telecommunication Applications and System Architectures. 261 - Reinhard Herzer:
Gate Driver Solutions for Modern Power Devices and Topologies. 262-270 - Giulio Ricotti, Valeria Bottarel:
HV Floating Switch Matrix with Parachute Safety Driving for 3D Echography Systems. 271-273 - Antonio Pullini, Davide Rossi, Igor Loi, Alfio Di Mauro, Luca Benini
Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing. 274-277 - Rubén Salvador, Alberto Sanchez, Xin Fan, Tobias Gemmeke
A Cortex-M3 Based MCV Featuring AVS with 34nW Static Power, 15.3pJ/inst. Active Energy, and 16% Power Variation Across Process and Temperature. 278-281 - Jaro De Roose, Haoming Xin, Martin Andraud
Flexible and Self-Adaptive Sense-and-Compress for Sub-MicroWatt Always-on Sensory Recording. 282-285 - Matthias Korb, Samuel Willi, Benjamin Weber
A Dual-Mode NB-IoT and EC-GSM RF-SoC Achieving -128-dBm Extended-Coverage and Supporting OTDOA and A-GPS Positioning. 286-289 - Martijn F. Snoeij:
A 36V 48MHz JFET-Input Bipolar Operational Amplifier with 150µV Maximum Offset and Overload Supply Current Control. 290-293 - Matthias Häberle, Denis Djekic, Georg E. Fantner
An Integrator-Differentiator TIA Using a Multi-Element Pseudo-Resistor in its DC Servo Loop for Enhanced Noise Performance. 294-297 - Federico Fary, Marcello De Matteis, Tommaso Vergine, Andrea Baschirotto:
A 28nm-CMOS 100MHz 1mW 12dBm-IIP3 4th-Order Flipped-Source-Follower Analog Filter. 298-301 - Jaeho Im, Hun-Seok Kim, David D. Wentzloff:
A 470µW -92.5dBm OOK/FSK Receiver for IEEE 802.11 WiFi LP-WUR. 302-305 - Javid Musayev, Antonio Liscidini
Quantized Analog RX Front-End for SAW-Less Applications. 306-309 - Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang
A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver. 310-313 - Tuan Thanh Ta, Yosuke Ogasawara, Tong Wang, Masayoshi Oshiro, Naotaka Koide, Akihide Sai, Takashi Tokairin:
A 15mW -105dBm Image-Sparse-Sliding-IF Receiver with Transformer-Based on-Chip Q-Enhanced RF Matching Network for a 113dB-Link-Budget BLE 5.0 TRX. 314-317 - Eric Guthmuller
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. 318-321 - Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic
A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. 322-325 - Jorge Marin
A Single-Temperature-Calibration 0.18-µm CMOS Time-Based Resistive Sensor Interface with Low Drift over a -40°C to 175°C Temperature Range. 330-333 - Ori Bass, Joseph Shor:
Ultra-Miniature 0.003 mm2 PNP-Based Thermal Sensor for CPU Thermal Monitoring. 334-337 - Yongjia Li, Mario Motz, Leneesh Raghavan:
A Signal and Offset T&H Frontend for Spinning Hall Sensors with Ping-Pong and Chopping Techniques. 338-341 - Matan Gal-Katziri, Ali Hajimiri:
A Coupled Inductive Bridge for Magnetic Sensing Applications. 342-345
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-19 22:02 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: