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2020 – today
- 2024
- [j59]ZiXuan Xu
, Kai Xing
An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R. IEEE J. Solid State Circuits 59(3): 753-764 (2024) - [j58]Yuzhao Fu
FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm2 Analog Compute-in-Memory Macro. IEEE J. Solid State Circuits 59(9): 3021-3031 (2024) - [j57]Chaorui Zou
A 256 × 192 -Pixel Direct Time-of-Flight LiDAR Receiver With a Current-Integrating-Based AFE Supporting 240-m-Range Imaging. IEEE J. Solid State Circuits 59(11): 3525-3537 (2024) - [j56]Yuefeng Cao, Minglei Zhang, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan:
A 12-GS/s 12-b 4× Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer. IEEE J. Solid State Circuits 59(12): 4211-4224 (2024) - [j55]Yuzhao Fu
CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 4996-5004 (2024) - [j54]Yaozhong Ou
A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2554-2558 (2024) - [c56]Chi-Hang Chan, Minglei Zhang, Yuefena Cao
The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs. CICC 2024: 1-8 - [c55]Pengyu He, Yuanzhe Zhao, Heng Xie, Yang Wang, Shouyi Yin, Li Li, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan, Minglei Zhang:
A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC. CICC 2024: 1-2 - [c54]Wei Zhang
A PVT-Robust 8b 20GS/s Time-Interleaved SAR ADC with Quantization-Embedded Current-Mode Buffer and Differ-Based Dither Timing Skew Calibration. CICC 2024: 1-2 - [c53]Chaorui Zou
6.8 A 256×192-Pixel 30fps Automotive Direct Time-of-Flight LiDAR Using 8× Current-Integrating-Based TIA, Hybrid Pulse Position/Width Converter, and Intensity/CNN-Guided 3D Inpainting. ISSCC 2024: 114-116 - [c52]Yuefeng Cao
22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer. ISSCC 2024: 388-390 - 2023
- [j53]Wenning Jiang, Yan Zhu
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier. IEEE J. Solid State Circuits 58(10): 2709-2721 (2023) - [j52]Hongshuai Zhang
A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator. IEEE J. Solid State Circuits 58(12): 3565-3575 (2023) - [j51]Hongzhi Zhao
A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC. IEEE J. Solid State Circuits 58(12): 3586-3597 (2023) - [j50]Lai Wei
A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4679-4691 (2023) - [j49]Junlin Zhong
A 0.016mm2 Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3792-3796 (2023) - [c51]Xiang-Hui Pan, Buhui Rui, Yuefeng Cao
A 12b 1GS/s ADC with Lightweight Input Buffer Distortion Background Calibration Achieving >75dB SFDR over PVT. CICC 2023: 1-2 - [c50]ZiXuan Xu
An ELDC-Free 2.78mW 20MHz-BW 75.5dB-SNDR 4th- Order CTSDM Facilitated by 2nd-Order CT NS-SAR and AC-Coupled Negative-R. CICC 2023: 1-2 - [c49]Yuanzhe Zhao, Minglei Zhang, Pengyu He, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A Double-Mode Sparse Compute-In-Memory Macro with Reconfigurable Single and Dual Layer Computation. CICC 2023: 1-2 - [c48]Junyan Hao, Minglei Zhang, Yanbo Zhang, Shubin Liu, Zhangming Zhu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness. ISSCC 2023: 168-169 - [c47]Yuefeng Cao
A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer. ISSCC 2023: 170-171 - [c46]Hongshuai Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A 25MHz-BW 77.2dB-SNDR 2nd-Order Gain-Error-Shaping and NS Pipelined SAR ADC Based on a Quantization-Prediction-Unrolled Scheme. ISSCC 2023: 174-175 - [c45]Yanbo Zhang, Junyan Hao, Shubin Liu, Zhangming Zhu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A Single-Channel 70dB-SNDR 100MHz-BW 4th-Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping. ISSCC 2023: 178-179 - [c44]Hongzhi Zhao
A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input. ISSCC 2023: 264-265 - [c43]Minglei Zhang, Yuefeng Cao
A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j48]Yanbo Zhang, Jin Zhang, Shubin Liu
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations. IEEE J. Solid State Circuits 57(3): 745-756 (2022) - [j47]Hongshuai Zhang
An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration. IEEE J. Solid State Circuits 57(5): 1480-1491 (2022) - [j46]Zihao Zheng, Lai Wei, Jorge Lagos
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier. IEEE J. Solid State Circuits 57(6): 1673-1683 (2022) - [j45]Kai Xing
A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 64-74 (2022) - [j44]Yu Duan, Chi-Hang Chan
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4799-4809 (2022) - [j43]Jiahao Liu
A Weak PUF-Assisted Strong PUF With Inherent Immunity to Modeling Attacks and Ultra-Low BER. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4898-4907 (2022) - [j42]Jiahao Liu
An Entropy-Source-Preselection-Based Strong PUF With Strong Resilience to Machine Learning Attacks and High Energy Efficiency. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 5108-5120 (2022) - [c42]Lele Fang, Jiahao Liu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
LSB-Reused Protection Technique in Secure SAR ADC against Power Side-Channel Attack. AsianHOST 2022: 1-6 - [c41]Yi Zeng, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins:
An Auxiliary-Loop-Enhanced Fast-Transient FVF LDO as Reference Buffer of a SAR ADC. ISCAS 2022: 2660-2664 - [c40]Yi Zeng, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins:
A low dropout regulator with PSR under -48dB up to 20GHz for a SARADC reference buffer. MWSCAS 2022: 1-4 - 2021
- [j41]Rui Paulo Martins
Bird's-eye view of analog and mixed-signal chips for the 21st century. Int. J. Circuit Theory Appl. 49(3): 746-761 (2021) - [j40]Yan Song
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC. IEEE J. Solid State Circuits 56(6): 1772-1783 (2021) - [j39]Wenning Jiang
A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 557-568 (2021) - [c39]Jiahao Liu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A 0.46pJ/bit Ultralow-Power Entropy-Preselection-Based Strong PUF with Worst-Case BER-6. A-SSCC 2021: 1-3 - [c38]Yanbo Zhang, Jin Zhang, Shubin Liu, Zhangming Zhu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture. CICC 2021: 1-2 - [c37]Hongshuai Zhang
27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration. ISSCC 2021: 380-382 - [c36]Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC. VLSI Circuits 2021: 1-2 - [c35]Minglei Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration. VLSI Circuits 2021: 1-2 - 2020
- [j38]Yan Song
A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC. IEEE J. Solid State Circuits 55(2): 312-321 (2020) - [j37]Wenning Jiang
A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier. IEEE J. Solid State Circuits 55(2): 322-332 (2020) - [j36]Wei Wang
A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization. IEEE J. Solid State Circuits 55(6): 1588-1598 (2020) - [j35]Minglei Zhang
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC With <1.5-ps Uncalibrated Quantization Steps. IEEE J. Solid State Circuits 55(12): 3225-3235 (2020) - [j34]Jin Zhang
An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 67-II(7): 1174-1178 (2020) - [j33]Yanbo Zhang, Shubin Liu, Binbin Tian, Yan Zhu
A 2nd-Order Noise-Shaping SAR ADC With Lossless Dynamic Amplifier Assisted Integrator. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1819-1823 (2020) - [j32]Xiaofeng Yang, Chi-Hang Chan
A Calibration-Free Ring-Oscillator PLL With Gain Tracking Achieving 9% Jitter Variation Over PVT. IEEE Trans. Circuits Syst. 67-I(11): 3753-3763 (2020) - [j31]Jiahao Liu
A 0.04% BER Strong PUF With Cell-Bias-Based CRPs Filtering and Background Offset Calibration. IEEE Trans. Circuits Syst. 67-I(11): 3853-3865 (2020) - [c34]Yan Song, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
9.6 A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration. ISSCC 2020: 164-166 - [c33]Minglei Zhang
16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input. ISSCC 2020: 252-254 - [c32]Zihao Zheng, Lai Wei, Jorge Lagos
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. ISSCC 2020: 254-256 - [c31]Kai Xing
A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j30]Minglei Zhang
A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-Enhanced Techniques. IEEE J. Solid State Circuits 54(12): 3396-3409 (2019) - [j29]Cheng Li
Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 82-93 (2019) - [j28]Dezhi Xing
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 489-501 (2019) - [j27]Xuewei Lei
A 4-b 7-µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3365-3372 (2019) - [j26]Xiaochao Li
Background Offset Calibration for Comparator Based on Temperature Drift Profile. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1648-1652 (2019) - [j25]Jianwei Liu
Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 481-485 (2019) - [c30]Lai Wei, Xiang-Hui Pan, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins:
Input Correlated Swap-Sampling Technique for Input Driver Power Reduction in a 12b 25MS/s SAR ADC. ISCAS 2019: 1-5 - [c29]Wenning Jiang
A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier. ISSCC 2019: 60-62 - [c28]Minglei Zhang
A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques. ISSCC 2019: 66-68 - [c27]Xiaofeng Yang, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins:
A -246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT. ISSCC 2019: 260-262 - [c26]Wei Wang, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins:
A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ. ISSCC 2019: 340-342 - 2018
- [j24]Chi-Hang Chan
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration. IEEE J. Solid State Circuits 53(3): 850-860 (2018) - [j23]Wei Wang
A 5.35-mW 10-MHz Single-Opamp Third-Order CT ΔΣ Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS. IEEE J. Solid State Circuits 53(10): 2783-2794 (2018) - [j22]Xiaofeng Yang
Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1819-1829 (2018) - [j21]X. Shawn Wang
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1534-1538 (2018) - [j20]Yan Zhu
A 0.19 mm2 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3606-3616 (2018) - [j19]Guan-Cheng Wang
Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3707-3719 (2018) - [j18]Yan Song
Passive Noise Shaping in SAR ADC With Improved Efficiency. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 416-420 (2018) - [j17]Guan-Cheng Wang
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2279-2289 (2018) - [c25]Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H. A-SSCC 2018: 1-2 - [c24]Wenning Jiang
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler. A-SSCC 2018: 235-238 - [c23]Chi-Hang Chan, Yan Zhu, Zi-Hao Zheng, Rui Paulo Martins:
A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end. ESSCIRC 2018: 254-257 - [c22]Yan Song, Yan Zhu, Chi-Hang Chan, Li Geng, Rui Paulo Martins:
A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ∑Δ ADC Based on the Pipelined-SAR Structure. VLSI Circuits 2018: 203-204 - 2017
- [j16]Chi-Hang Chan
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration. IEEE J. Solid State Circuits 52(10): 2576-2588 (2017) - [j15]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin
Metastablility in SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 111-115 (2017) - [j14]Jianyu Zhong
A 12b 180MS/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7): 1684-1695 (2017) - [j13]Chi-Hang Chan
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(8): 1966-1976 (2017) - [j12]Yan Zhu
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 354-363 (2017) - [j11]Arshad Hussain
Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 364-374 (2017) - [j10]Dezhi Xing
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1168-1172 (2017) - [c21]Wei Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS. A-SSCC 2017: 285-288 - [c20]Guan-Cheng Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC. ESSCIRC 2017: 239-242 - [c19]Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins
16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration. ISSCC 2017: 282-283 - 2016
- [j9]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC. IEEE J. Solid State Circuits 51(2): 365-377 (2016) - [j8]Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS. IEEE J. Solid State Circuits 51(5): 1223-1234 (2016) - [j7]Yan Zhu, Chi-Hang Chan, Si-Seng Wong, Seng-Pan U, Rui Paulo Martins:
Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1203-1207 (2016) - [j6]Jianwei Liu, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2603-2607 (2016) - [c18]Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Chon-Lam Lio, Seng-Pan U, Rui Paulo Martins
A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages. A-SSCC 2016: 145-148 - [c17]Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction. ESSCIRC 2016: 169-172 - 2015
- [c16]Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin
A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation. A-SSCC 2015: 1-4 - [c15]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin
26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS. ISSCC 2015: 1-3 - 2014
- [j5]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 372-383 (2014) - [c14]Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC. ESSCIRC 2014: 211-214 - 2013
- [j4]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin
A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS. IEEE J. Solid State Circuits 48(9): 2154-2169 (2013) - [c13]Wen-Lan Wu, Yan Zhu, Li Ding, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. ISCAS 2013: 2239-2242 - 2012
- [j3]Yan Zhu, Chi-Hang Chan, Sai-Weng Sin
A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation. IEEE J. Solid State Circuits 47(11): 2614-2626 (2012) - [j2]He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. IEEE J. Solid State Circuits 47(11): 2763-2772 (2012) - [c12]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. VLSIC 2012: 86-87 - [c11]Yan Zhu, Chi-Hang Chan, Sai-Weng Sin
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC. VLSIC 2012: 90-91 - 2011
- [c10]Yan Zhu, Chi-Hang Chan, Sai-Weng Sin
A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation. A-SSCC 2011: 61-64 - [c9]Si-Seng Wong, U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin
A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators. A-SSCC 2011: 73-76 - [c8]Chi-Hang Chan, Yan Zhu, U. Fat Chio, Sai-Weng Sin
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS. A-SSCC 2011: 233-236 - [c7]U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin
A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. ESSCIRC 2011: 363-366 - [c6]He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin
A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. ISSCC 2011: 188-190 - 2010
- [j1]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. IEEE J. Solid State Circuits 45(6): 1111-1121 (2010) - [c5]Sai-Weng Sin
An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. ESSCIRC 2010: 218-221 - [c4]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin
A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. ISCAS 2010: 4061-4064
2000 – 2009
- 2004
- [c3]Chi-Hang Chan, Irwin King
Using Biased Support Vector Machine to Improve Retrieval Result in Image Retrieval with Self-organizing Map. ICONIP 2004: 714-719 - 2003
- [c2]Cheuk Hang Ng, Ka Cheung Sia, Chi-Hang Chan:
Advanced Peer Clustering and Firework Query Model in the Peer-to-Peer Network. WWW (Posters) 2003 - [c1]Ka Cheung Sia, Cheuk Hang Ng, Chi-Hang Chan:
Bridging the P2P and WWW Divide with DISCOVIR - DIStributed COntent-based Visual Information Retrieval. WWW (Posters) 2003
Coauthor Index
Rui Paulo Martins
aka: Rui Paulo da Silva Martins
aka: Rui Paulo da Silva Martins
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