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Filip Tavernier
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2020 – today
- 2024
- [j14]Tuur Van Daele
, Filip Tavernier
Monolithic 230-VRMS-to-12-VDC AC-DC Converter at 9 mW/mm2 Enabled by a 31-325-VDC Input Range Capacitive Multi-Ratio DC-DC Converter. IEEE J. Solid State Circuits 59(4): 1067-1077 (2024) - [j13]Filip Tavernier
Guest Editorial IEEE 2023 European Solid-State Circuits Conference. IEEE J. Solid State Circuits 59(7): 1979-1980 (2024) - 2023
- [b1]Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert
Multi-Gigahertz Nyquist Analog-to-Digital Converters - Architecture and Circuit Innovations in Deep-Scaled CMOS and FinFET Technologies, 3. Springer 2023, ISBN 978-3-031-22708-0, pp. 1-256 - [j12]Tuur Van Daele
Fully Integrating a 400 V-to-12 V DC-DC Converter in High-Voltage CMOS. IEEE J. Solid State Circuits 58(3): 732-741 (2023) - [c27]Zongyuan Li, Filip Tavernier:
A 10 GHz Quadruple-Tail Comparator with Double Feedforward Paths and Minimal Delay Slope in 28 nm CMOS. ESSCIRC 2023: 205-208 - [c26]Tuur Van Daele, Filip Tavernier:
A Fully Integrated 230 VRMS-to-12 VDC AC-DC Converter Achieving 9 mW/mm2. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j11]Athanasios T. Ramkaj
A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4404-4414 (2022) - [c25]Tuur Van Daele, Filip Tavernier:
A 400-to-12 V Fully Integrated Switched-Capacitor DC-DC Converter Achieving 119 mW/mm2 at 63.6 % Efficiency. CICC 2022: 1-2 - [c24]Qiuyang Lin, Christina Avidikou, Filip Tavernier, Nick Van Helleputte:
Photoplethysmography (PPG) Sensor Circuit Design Techniques. CICC 2022: 1-8 - [c23]Bram Veraverbeke, Tim Thielemans
A 240V to 47.5 V Fully Integrated Switched-Capacitor Converter in GaN Achieving 62.6% Efficiency at 220 mW/mm2. PRIME 2022: 249-252 - [c22]Athanasios Ramkaj, Adalberto Cantoni, Gabriele Manganaro, Siddharth Devarajan, Michiel Steyaert, Filip Tavernier:
A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET. VLSI Technology and Circuits 2022: 100-101 - 2021
- [j10]Qiuyang Lin
A 134 DB Dynamic Range Noise Shaping Slope Light-to-Digital Converter for Wearable Chest PPG Applications. IEEE Trans. Biomed. Circuits Syst. 15(6): 1224-1235 (2021) - [c21]Qiuyang Lin, Shuang Song
A 28μW 134dB DR 2nd-Order Noise-Shaping Slope Light-to-Digital Converter for Chest PPG Monitoring. ISSCC 2021: 390-392 - 2020
- [j9]Athanasios T. Ramkaj
A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS. IEEE J. Solid State Circuits 55(6): 1553-1564 (2020) - [j8]Wouter Diels
1310/1550 nm Optical Receivers With Schottky Photodiode in Bulk CMOS. IEEE J. Solid State Circuits 55(7): 1776-1784 (2020) - [j7]Yifan Lyu
A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs. IEEE J. Solid State Circuits 55(7): 1807-1818 (2020) - [j6]Qiuyang Lin
A 119dB Dynamic Range Charge Counting Light-to-Digital Converter For Wearable PPG/NIRS Monitoring Applications. IEEE Trans. Biomed. Circuits Syst. 14(4): 800-810 (2020) - [c20]Yifan Lyu
A 1 GS/s Reconfigurable BW 2nd-Order Noise-Shaping Hybrid Voltage-Time Two-Step ADC Achieving 170.9 dB FoMS. VLSI Circuits 2020: 1-2 - [c19]Tim Thielemans
A 4V-0.55V Input Fully Integrated Switched-Capacitor Converter Enabling Dynamic Voltage Domain Stacking and Achieving 80.1% Average Efficiency. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j5]Filipe D. Baumgratz
A Wideband Low-Noise Variable-Gain Amplifier With a 3.4 dB NF and up to 45 dB Gain Tuning Range in 130-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 66-II(7): 1104-1108 (2019) - [c18]Wouter Diels, Michiel Steyaert
Optical Receiver with Schottky Photodiode and TIA with High Gain Amplifier in 28nm Bulk CMOS. ESSCIRC 2019: 149-152 - [c17]Yifan Lyu
A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feed-Forward Ring Oscillator-Based TDCs. ESSCIRC 2019: 163-166 - [c16]Athanasios T. Ramkaj, Michiel S. J. Steyaert
A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS. ESSCIRC 2019: 167-170 - [c15]Athanasios Ramkaj
A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS. ISSCC 2019: 62-64 - [c14]Tuur Van Daele, Elly De Pelecijn, Tim Thielemans
A Fully-Integrated 6: 1 Cascaded Switched-Capacitor DC-DC Converter Achieving 74% Efficiency at 0.1W/mm2. PRIME 2019: 49-52 - [c13]Qiuyang Lin, Jiawei Xu, Shuang Song
A 196μW, Reconfigurable Light-to-Digital Converter with 119dB Dynamic Range, for Wearable PPG/NIRS Sensors. VLSI Circuits 2019: 58- - 2018
- [j4]Athanasios Ramkaj
A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS. IEEE J. Solid State Circuits 53(7): 1889-1901 (2018) - [j3]Filipe D. Baumgratz
40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(8): 2581-2591 (2018) - [c12]Tim Thielemans
A capacitive DC-DC converter for stacked loads with wide range DVS achieving 98.2% peak efficiency in 40nm CMOS. CICC 2018: 1-4 - [c11]Wouter Diels, Michiel Steyaert
A 1310/1550 nm Fully-Integrated Optical Receiver with Schottky Photodiode and Low-Noise Transimpedance Amplifier in 40 nm Bulk CMOS. ESSCIRC 2018: 242-245 - [c10]Filipe D. Baumgratz, Sandro B. Ferreira
A Charge-Sharing Bandpass Filter Topology with Boosted Q-Factor in 40-NM CMOS. SBCCI 2018: 1-6 - [c9]Mingyi Chen, Ivan Dario Castro, Qiuyang Lin, Tom Torfs, Filip Tavernier, Chris Van Hoof
A 400GΩ Input-Impedance, 220MVpp Linear-Input-Range, 2.8Vpp CM-Interference-Tolerant Active Electrode for Non-Contact Capacitively Coupled ECG Acquisition. VLSI Circuits 2018: 129-130 - 2017
- [c8]Athanasios Ramkaj
A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS. ESSCIRC 2017: 167-170 - [c7]Wouter Diels, Michiel Steyaert
Modelling, design and characterization of Schottky diodes in 28nm bulk CMOS for 850/1310/1550nm fully integrated optical receivers. ESSDERC 2017: 224-227 - [c6]Wouter Diels, Michiel Steyaert, Filip Tavernier:
Schottky diodes in 40nm bulk CMOS for 1310nm high-speed optical receivers. OFC 2017: 1-3 - 2016
- [j2]Tao Zhang, Ping Gui, Sudipto Chakraborty, Tianwei Liu, Guoying Wu
10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2502-2510 (2016) - 2015
- [c5]Michiel Steyaert
When hardware is free, power is expensive! Is integrated power management the solution? ESSCIRC 2015: 26-34 - 2010
- [c4]Filip Tavernier, Michiel Steyaert
A 5.5 Gbit/s optical receiver in 130 nm CMOS with speed-enhanced integrated photodiode. ESSCIRC 2010: 542-545
2000 – 2009
- 2009
- [j1]Filip Tavernier, Michel S. J. Steyaert
High-Speed Optical Receivers With Integrated Photodiode in 130 nm CMOS. IEEE J. Solid State Circuits 44(10): 2856-2867 (2009) - [c3]Filip Tavernier, Michiel Steyaert
A low power, area efficient limiting amplifier in 90nm CMOS. ESSCIRC 2009: 128-131 - 2008
- [c2]Filip Tavernier, Michiel Steyaert
Power efficient 4.5Gbit/s optical receiver in 130nm CMOS with integrated photodiode. ESSCIRC 2008: 162-165 - [c1]Filip Tavernier, Michiel Steyaert
A high-speed fully integrated optical receiver in standard 130nm CMOS. ICECS 2008: 806-809
Coauthor Index
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last updated on 2024-09-28 01:25 CEST by the dblp team
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