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CICC 2021: Austin, TX, USA
- IEEE Custom Integrated Circuits Conference, CICC 2021, Austin, TX, USA, April 25-30, 2021. IEEE 2021, ISBN 978-1-7281-7581-2
- Mohamed A. Mokhtar, Ahmed Abdelaal
, Markus Sporer, Joachim Becker, John G. Kauffman, Maurits Ortmanns:
A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s Continuous Time Incremental Delta-Sigma ADC Utilizing Variable Bit Width Quantizer in 28nm CMOS. 1-2 - Mohsen Mortazavi, Yiyu Shen, Dieuwert P. N. Mul, Leo C. N. de Vreede, Marco Spirito
A 30GHz 4-way Series Doherty Digital Polar Transmitter Achieving 18% Drain Efficiency and -27.6dB EVM while Transmitting 300MHz 64-QAM OFDM Signal. 1-2 - Xiangxing Yang, Keren Zhu
An In-Memory-Computing Charge-Domain Ternary CNN Classifier. 1-2 - Abdullah Abdulslam, Patrick P. Mercier
A Battery-Connected Inductor-First Flying Capacitor Multilevel Converter Achieving 0.77W/mm2 and 97.1% Peak Efficiency. 1-2 - Yuqi Su, Junjie Mu, Hyunjoon Kim
A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems. 1-2 - Hai Au Huynh, Milad Zamani
A 53GΩ@DC Input Impedance Multi-Channel Neural Recording Amplifier with 0.77 μVrms Input-Referred Noise for Deep Brain Implants. 1-2 - Marcel Runge, Julius Edler, Tobias Kaiser, Friedel Gerfers:
A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS. 1-2 - Wei Zhu, Jiawen Wang, Ruitao Wang
An Ultra-Compact 84.9-107GHz LNA with 4.9dB NF by Utilizing Coupled-line-based Gm-Boosting and Noise-Canceling Techniques in 65-nm CMOS Technology. 1-2 - Qijun Liu
Zero-Crossing-Based Bio-Engineered Sensor. 1-2 - Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation. 1-2 - Yibo Zhao, Huajun Zhang
A 94.1 dB DR 4.1 nW/Hz Bandwidth/Power Scalable DTDSM for IoT Sensing Applications Based on Swing-Enhanced Floating Inverter Amplifiers. 1-2 - Pingda Guan
An Ultra-Compact 16-to-45 GHz Power Amplifier within A Single Inductor Footprint Using Folded Transformer Technique. 1-2 - Fatemeh Eshaghi, Esmaeil Najafi Aghdam
A 24-Channel Neurostimulator IC with One-Shot Impedance-Adaptive Channel-Specific Charge Balancing. 1-2 - Kyu-Sang Park
A second-order temperature compensated 1μW/MHz 100MHz RC oscillator with ±140ppm inaccuracy from -40°C to 95°C. 1-2 - Wei Zhu, Jiawen Wang, Ruitao Wang
A Dual-Mode 24-32 GHz 4-Element Phased-Array Transceiver Front-End with SSA Beamformer for Autonomous Agile Unknown Signal Tracking and Blocker Rejection within <0.1 us and 21.3%/15% Transmitter Peak/OP1dB PAE. 1-2 - Haoran Pu, Ahmad Reza Danesh
A 40V Voltage-Compliance 12.75mA Maximum-Current Multipolar Neural Stimulator Using Time-Based Charge Balancing Technique Achieving 2mV Precision. 1-2 - Tamer A. Ali, Mohammed Abdullatif, Henry Park, Ehung Chen, Ramy Awad, Miguel Gandara:
56/112Gbps Wireline Transceivers for Next Generation Data Centers on 7nm FINFET CMOS Technology. 1-6 - Li-Yang Chen, Abhinav Kumar Vinod, James F. McMillan, Chee Wei Wong, Chih-Kong Ken Yang:
A 6μm-Precision Pulsed-Coherent Lidar with a 40-dB Tuning Range Inverter-Based Phase-Invariant PGA. 1-2 - Bahareh Hadidian, Farzad Khoeini, S. M. Hossein Naghavi
An Energy Efficient Fully Integrated 20Gbps OOK Wireless Transmitter at 220GHz. 1-2 - Charles R. Sullivan
Coupled Inductors for Fast-Response High-Density Power Delivery: Discrete and Integrated. 1-8 - Meizhi Wang
Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks. 1-2 - Ahmed Elmallah, Junheng Zhu, Amr Khashaba, Karim M. Megawer, Ahmed Elkholy, Pavan Kumar Hanumolu:
A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction. 1-2 - Yanbo Zhang, Jin Zhang, Shubin Liu, Zhangming Zhu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture. 1-2 - Rajkumar Kubendran
A 256x256 6.3pJ/pixel-event Query-driven Dynamic Vision Sensor with Energy-conserving Row-parallel Event Scanning. 1-2 - Wei Deng, Haikun Jia, Rui Wu, Shiyan Sun, Chenggang Li, Zhihua Wang, Baoyong Chi:
An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator. 1-2 - Chengshuo Yu, Yuqi Su, Jaeho Lee, Kevin T. C. Chai, Bongjin Kim:
A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations. 1-2 - Payam Heydari:
Transceivers for 6G Wireless Communications: Challenges and Design Solutions. 1-8 - Minjae Kim, Hyun-Su Lee, Hyung-Min Lee:
An Efficient Wireless Power and Data Transfer System with Current-Modulated Energy-Reuse Back Telemetry and Energy-Adaptive Dual-Input Voltage Regulation. 1-2 - Nirmoy Modak, Debayan Das, Mayukh Nath
A 65nm Resonant Electro-Quasistatic 5-240uW Human Whole-Body Powering and 2.19uW Communication SoC with Automatic Maximum Resonant Power Tracking. 1-2 - Zhanghao Yu, Joshua C. Chen
Multisite bio-stimulating implants magnetoelectrically powered and individually programmed by a single transmitter. 1-2 - Arda Uran, Kerim Türe
A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOS. 1-2 - Christos G. Adamopoulos, Sidney Buchbinder, Panagiotis G. Zarkos, Pavan Bhargava, Asmaysinh Gharia, Ali M. Niknejad, Mekhail Anwar, Vladimir Stojanovic:
Fully Integrated Electronic-Photonic Sensor for Label-Free Refractive Index Sensing in Advanced Zero-Change CMOS-SOI Process. 1-2 - Yaolong Hu, Xiaohan Zhang, Taiyun Chi:
A 28GHz Hybrid-Beamforming Transmitter Array Supporting Concurrent Dual Data Steams and Spatial Notch Steering for 5G MIMO. 1-2 - Seneke Chamith Chandrarathna, Jong-Wook Lee:
A Self-Resonant Boost Converter for Solar Energy Harvesting with 97% Tracking Efficiency, 80 mV Self-Startup and Ultra-Wide Range Source Tracking. 1-2 - Hao Wang
Dividerless Frequency Acquisition & Charge Pump Mismatch Compensation for Low-Power Millimeter-Wave Sub-Sampling PLL. 1-8 - Yuting Shen, Hanyue Li, Haoming Xin, Eugenio Cantatore, Pieter Harpe:
A low-cost 0.98μW0.8V oversampled SAR ADC with pre-comparison and mismatch error shaping achieving 84.5dB SNDR and 103dB SFDR. 1-2 - Weiyu Leng, Asad A. Abidi, Sraavan R. Mundlapudi, Hooman Darabi, Debopriyo Chowdhury, Ali Afsahi, Sida Li:
Envelope-Tracking Supply Modulator with Trellis Search-Based Switching and 160MHz Capability. 1-2 - Yongki Lee, Bohdan Karpinskyy, Yunhyeok Choi, Kyoung-Moon Ahn, Yongsoo Kim, Jieun Park, Sumin Noh, Jisu Kang, Jonghoon Shin, Jaechul Park, Youngjin Chung, Jongshin Shin:
Samsung Physically Unclonable Function (SAMPUF™) and its integration with Samsung Security System. 1-7 - Rezwan A. Rasul, Mike Shuo-Wei Chen:
A 128x128 SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain via MOS Capacitor for Machine Learning Application. 1-2 - Qiuzhen Xu, Kun Liao, Junzhong Yang, Pengda Qu, Feng Luo
An Inverter-Based Amplifier Structure for Neural Signal Recording with an NEF of 1.28 and Area-per-Channel of 0.06mm2. 1-2 - Boyu Shen
A Digitally-Reconfigurable RC Frequency Generator using Impedance IQ-Balanced Frequency-Locked-Loop with Selectable Phase Mixing. 1-2 - Arindam Mandal, Diego Peña, Rajesh Pamula, Karam Khateeb, Logan Murphy, Azadeh Yazdan-Shahmorad, Steve I. Perlmutter, Forrest Pape, Jacques Christophe Rudell, Visvesh S. Sathe:
A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation. 1-2 - Yi Zhong
An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer. 1-2 - Hao Luo, Somnath Kundu, Chun C. Lee, Rinkle Jain, Sarah Shahraini, Eduardo Alban, Timo Huusari, Jason Mix, Nasser A. Kurd, Mohamed Abdel-moneum, Brent R. Carlton:
A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOS. 1-2 - Sumanth Kamineni, Shourya Gupta, Benton H. Calhoun:
MemGen: An Open-Source Framework for Autonomous Generation of Memory Macros. 1-2 - Huanbo Li, Jixin Chen, Debin Hou, Zekun Li, Rui Zhou, Wei Hong:
A 94GHz Scalable 2 × 2 Phased-Array Receiver in SiGe BiCMOS for High Data-Rate Communication. 1-2 - Geng Mu, Dawei Ye
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording. 1-2 - Li Xu
Design Techniques of Integrated Power Management Circuits for Low Power Edge Devices. 1-4 - Xiangyu Mao, Yan Lu, Rui Paulo Martins:
A Dual-Loop 4-Phase Switching LDO with Scalable Load Capability and Tunable Active Voltage Positioning for Microprocessors. 1-2 - Fabio Toso, Francesco Zanetto
Electronics-photonics co-design for robust control of optical devices in dense integrated photonic circuits. 1-8 - Victoria Kolesov, Vivek Rajan, Ramune Nagisetty:
3DIC Design Challenges, Early Solutions and Future Recommendations. 1-4 - Michiel Verplaetse, Hannes Ramon, Nishant Singh
A 4-to-1 240 Gb/s PAM-4 MUX with a 7-tap Mixed-Signal FFE in 55nm BiCMOS. 1-2 - Zhanhong Tan, Sia Huat Tan, Jan-Henrik Lambrechts, Yannian Zhang, Yifu Wu, Kaisheng Ma
A 400MHz NPU with 7.8TOPS2/W High-PerformanceGuaranteed Efficiency in 55nm for Multi-Mode Pruning and Diverse Quantization Using Pattern-Kernel Encoding and Reconfigurable MAC Units. 1-2 - Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu
MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC. 1-2 - Meizhi Wang
Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management. 1-2 - Yong Qu
A 12-W 96.1%-Efficiency eFuse-Based Ultrafast Battery Charger Supporting Wireless and USB Power Inputs. 1-2 - Sajjad Moazeni, Kevin Renehan, Eric H. Pollmann, Kenneth L. Shepard:
Integrated-Circuit Node for Time-Domain Near-infrared Diffuse Optical Tomography Imaging Arrays with On-chip Histogramming and Integrated VCSELs. 1-2 - Rakshith Saligram, Suman Datta, Arijit Raychowdhury:
CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications. 1-2 - Rahul Mathur, Mudit Bhargava, Heath Perry, Alberto Cestero, Frank Frederick, Shawn Hung, Chien-Ju Chao, Daniel Smith, Daniel Fisher, Norman Robson, Xiaoqing Xu, Pranavi Chandupatla, Raguram Balachandran, Saurabh Sinha, Brian Cline, Jaydeep P. Kulkarni:
3D-Split SRAM: Enabling Generational Gains in Advanced CMOS. 1-2 - Alyosha Christopher Molnar, Sunwoo Lee, Alejandro J. Cortese, Paul L. McEuen, Sanaz Sadeghi
Nanoliter-Scale Autonomous Electronics: Advances, Challenges, and Opportunities. 1-6 - Jinyong Kim, Callen Votzke
A 20 μ W, 0.05mm2 Duty-Cycled Resistor and Frequency-Locked-Loop-based Wheatstone Bridge Interface for Low Resistance Sensing Systems. 1-2 - Amr Ahmed
A 26-32 GHz Dual-Polarization Receiver with Autonomous Polarization Alignment for Fast-Response Mm-Wave MIMO Links in Highly Dynamic Mobile Environments. 1-2 - Liang Fang, Tao Fu, Xianshan Wen, Ping Gui:
A 1GS/s 82dB Peak-SFDR 12b Single-Channel Pipe-SAR ADC with Harmonic-Injecting Cross-Coupled-Pair and Fast N-replica Bootstrap Switch Achieving 7.5fj/conv-step. 1-2 - James F. Buckwalter, Mark J. W. Rodwell, Kang Ning, Ahmed S. H. Ahmed, Andrea Arias-Purdue, Jeff Chien, Everett O'Malley, Eythan Lam:
Prospects for High-Efficiency Silicon and lll-V Power Amplifiers and Transmitters in 100-300 GHz Bands. 1-7 - Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie:
A 2.7mW 45fsrms-Jitter Cryogenic Dynamic-Amplifier-Based PLL for Quantum Computing Applications. 1-2 - Mansour Taghadosi
An Analog Low-Power Highly-Accurate Link-Adaptive Energy Storage Efficiency Maximizer for Resonant CM Wireless Power Receivers. 1-2 - Zhixian Deng
A 3.6dB NF, 23-39GHz Reflectionless RX with Absorptive Amplifier and Dual-Path Noise Cancelling LNA Supporting 64-QAM/256-QAM/1024-QAM for 5G NR. 1-2 - Qiwen Liao, Miaofeng Li, Zhao Zhang, Jian Liu, Nanjian Wu, Xi Xiao
A 50Gb/s High-Efficiency Si-Photonic Transmitter With Lump-Segmented MZM and Integrated PAM4 CDR. 1-2 - Aoyang Zhang, Mostafa M. Ayesh
A 24-28 GHz Concurrent Harmonic and Subharmonic Tuning Class E/F2, 2/3 Subharmonic Switching Power Amplifier Achieving Peak/PBO Efficiency Enhancement. 1-2 - Rajesh Inti, Mozhgan Mansuri, Joe Kennedy, Junyi Qiu, Chun-Ming Hsu, Jahnavi Sharma, Hao Li, Bryan Casper, James E. Jaussi:
A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOS. 1-2 - Ashutosh Chitnis, Rajat Chauhan, Divya Kaur, Qadeer Khan:
A 0.75-5V, 15.8 nA with 1.8 μs Delay Supply Voltage Supervisor using Adaptively Biased Comparator and Sample & Hold Technique for IoT. 1-2 - Utsav Banerjee
A Low-Power Elliptic Curve Pairing Crypto-Processor for Secure Embedded Blockchain and Functional Encryption. 1-2 - Qihui Zhang, Jing Li, Zhong Zhang, Kejun Wu, Ning Ning, Qi Yu:
A13b-ENOB Third-Order Noise-Shaping SAR ADC using a Hybrid Error-Control Structure. 1-2 - Chester Liu, Jacob Botimer, Zhengya Zhang
A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer. 1-2 - Wantong Li
Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security. 1-2 - Rakshith Saligram, Divya Prasad, David Pietromonaco, Arijit Raychowdhury, Brian Cline:
A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance. 1-2 - Qi Cheng
A 5-100V Input Low-Profile Adaptive Delay Compensated Hysteretic LED Driver with Enhanced Current Accuracy. 1-2 - Han Hao, Hangxing Liu, Jan Van der Spiegel, Firooz Aflatouni:
A Somatosensory Feedback System in 180nm CMOS. 1-2 - Zhong Tang, Yun Fang, Xiao-Peng Yu, Nianxiong Nick Tan, Zheng Shi, Pieter Harpe:
A 1-V Diode-Based Temperature Sensor with a Resolution FoM of 3.1pJ•K2 in 55nm CMOS. 1-2 - Alessandro Garghetti, Andrea Leonardo Lacaita
A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS. 1-2 - Chang Yang, Weizhong Chen, Yanli Fan, Ping Gui:
A General-Regression-Neural-Network Based 5V-to-48V Three-Level Buck/Boost Power Converter with 40dB PSRR 90%-Efficiency for SSD Power Loss Protection. 1-2 - Youngcheol Chae, Moon Hyung Jang
A Negative R-Assisted Amplifier on the Virtual Ground and Its Applications. 1-6 - K. Gaurav Kumar, Baibhab Chatterjee
A 16 pJ/bit 0.1-15Mbps Compressive Sensing IC with on-chip DWT Sparsifier for Audio Signals. 1-2 - Pourya Assem, Robert C. N. Pilawa-Podgurski:
Quad Gate-Driver Controller with Start-Up and Shutdown for Cascaded Resonant Switched-Capacitor Converter. 1-2 - Ioannis A. Papistas, Stefan Cosemans, Bram Rooseleer, Jonas Doevenspeck, Myung Hee Na, Arindam Mallik, Peter Debacker
A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration. 1-2 - Marcel Runge, Dario Schmock, Tobias Kaiser, Friedel Gerfers:
A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS. 1-2 - Yuyang Li, Inhee Lee:
An 111pW Voltage Reference with a Diode-Leakage-Decoupling Replica for High-Temperature Miniature IoT Systems. 1-2 - Taewook Kang, Seungjong Lee, Mohammad Haghigat, Darren Abramson, Michael P. Flynn:
A 50μW 4-channel 83dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature Extraction. 1-2 - Ki Yong Kim, Ranjit Gharpurey:
A 1.6 GS/s Spectrum Channelizer with PWM-LO Based Sub-band Equalization. 1-2
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last updated on 2024-12-16 22:14 CET by the dblp team
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