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"Energy-efficient High-level Synthesis for HDR Architectures with Clock ..."

Hiroyuki Akasaka et al. (2013)

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DOI: 10.2197/IPSJTSLDM.6.101

access: closed

type: Journal Article

metadata version: 2020-09-29

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Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. IPSJ Trans. Syst. LSI Des. Methodol. 6: 101-111 (2013)

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