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Shin-ya Abe
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2010 – 2019
- 2015
- [j10]Shin-ya Abe, Youhua Shi
, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1376-1391 (2015) - [j9]Koichi Fujiwara, Kazushi Kawamura, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1392-1405 (2015) - [j8]Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. Inf. Media Technol. 10(1): 1-7 (2015) - 2014
- [j7]Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. IPSJ Trans. Syst. LSI Des. Methodol. 7: 74-80 (2014) - [c3]Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs. APCCAS 2014: 244-247 - 2013
- [j6]Shin-ya Abe, Youhua Shi
Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2597-2611 (2013) - [j5]Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. Inf. Media Technol. 8(4): 913-923 (2013) - [j4]Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. IPSJ Trans. Syst. LSI Des. Methodol. 6: 101-111 (2013) - [c2]Shin-ya Abe, Youhua Shi
An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. VLSI-DAT 2013: 1-4 - 2012
- [j3]Shin-ya Abe, Youhua Shi
MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures. IEICE Electron. Express 9(17): 1414-1422 (2012) - [j2]Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures. Inf. Media Technol. 7(4): 1319-1330 (2012) - [j1]Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
Energy-efficient High-level Synthesis for HDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 5: 106-117 (2012) - [c1]Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures. ISCAS 2012: 576-579
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