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"SEDAAF: FPGA Based Single Exact Dual Approximate Adders for Approximate ..."

Chandan Kumar Jha et al. (2020)

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DOI: 10.1109/ISCAS45731.2020.9181185

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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  dblp key:
  - conf/iscas/0001PTM20
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Chandan Kumar Jha, Kailash Prasad, Arun Singh Tomar, Joycee Mekie:
SEDAAF: FPGA Based Single Exact Dual Approximate Adders for Approximate Processors. ISCAS 2020: 1-5

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