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Rainer Kress 0002
Person information
- affiliation: Infineon
- affiliation: Universität Kaiserslautern
Other persons with the same name
- Rainer Kress 0001
(aka: Rainer Kreß) — Universität Göttingen, Germany
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2010 – 2019
- 2014
- [c24]Marco Casale-Rossi, Pietro Palella, Mario Anton, Ori Galzur, Robert Hum, Rainer Kress, Paul Lo:
Panel: The world is going... analog & mixed-signal! What about EDA? DATE 2014: 1-5 - 2012
- [c23]Marco Casale-Rossi, Pierluigi Rolandi, Andreas Bruening, Antun Domic, Rainer Kress, Joseph Sawicki, Christian Sebeke:
Panel: What is EDA doing for trailing edge technologies? DATE 2012: 874
2000 – 2009
- 2000
- [c22]Rainer Kress, Andreas Pyttel, Alexander Sedlmeier:
FPGA-Based Prototyping for Product Definition. FPL 2000: 78-86 - [c21]Michael Mrva, Rainer Kress:
Role-Centered Conceptual Modeling in System Design. MBMV 2000: 121-128
1990 – 1999
- 1999
- [c20]Josef Fleischmann, Klaus Buchenrieder
Java Driven Codesign and Prototyping of Networked Embedded Systems. DAC 1999: 794-797 - [c19]Josef Fleischmann, Klaus Buchenrieder
Codesign of Embedded Systems Based on Java and Reconfigurable Hardware Components. DATE 1999: 768-769 - [c18]Rainer Kress, Andreas Pyttel:
Debugging Application-Specific Programmable Products. FPL 1999: 481-486 - 1998
- [c17]Josef Fleischmann, Klaus Buchenrieder
A hardware/software prototyping environment for dynamically reconfigurable embedded systems. CODES 1998: 105-109 - [c16]Michael Mrva, Klaus Buchenrieder
A Scalable Architecture for Multi-threaded JAVA Applications. DATE 1998: 868-874 - [c15]Rainer Kress, Andreas Pyttel:
High-Level Synthesis for Dynamically Reconfigurable Hardware/Software Systems. FPL 1998: 288-297 - 1997
- [c14]Rainer Kress, Reiner W. Hartenstein, Ulrich Nageldinger:
An operating system for custom computing machines based on the Xputer paradigm. FPL 1997: 304-313 - 1996
- [b1]Rainer Kress:
A fast reconfigurable ALU for Xputers. Kaiserslautern University of Technology, Germany, 1996, pp. I-XIV, 1-241 - [j2]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig:
High-performance computing using a reconfigurable accelerator. Concurr. Pract. Exp. 8(6): 429-443 (1996) - [c13]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger:
A Synthesis System For Bus-Based Wavefront Array Architectures. ASAP 1996: 274-283 - [c12]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. CODES 1996: 77-84 - [c11]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
Two-Level Hardware/Software Partitioning Using CoDe-X. ECBS 1996: 395- - [c10]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
An Embedded Accelerator for Real-Time Image Processing. RTS 1996: 83-88 - [c9]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. FPL 1996: 65-76 - [c8]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger:
A Partitioning Programming Environment for a Novel Parallel Architecture. IPPS 1996: 544-548 - [c7]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig:
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. VLSI Design 1996: 81-84 - 1995
- [c6]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt:
A Parallelizing Compilation Method for the Map-oriented Machine. ASAP 1995: 129-132 - [c5]Reiner W. Hartenstein, Rainer Kress:
A datapath synthesis system for the reconfigurable datapath architecture. ASP-DAC 1995 - 1994
- [c4]Reiner W. Hartenstein, Rainer Kress, Helmut Reinig:
A dynamically reconfigurable wavefront array architecture for evaluation of expressions. ASAP 1994: 404-414 - [c3]Reiner W. Hartenstein, Rainer Kress, Helmut Reinig:
A New FPGA Architecture for Word-Oriented Datapaths. FPL 1994: 144-155 - [c2]Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt:
Data-Procedural Languages for FPL-based Machines. FPL 1994: 183-195 - 1993
- [j1]Rainer Kress, Elmar U. K. Melcher, Reiner W. Hartenstein, Michel Dana:
CMOS interconnect modelling for timing analysis. Microprocess. Microprogramming 37(1-5): 7-10 (1993) - 1992
- [c1]Andreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt:
Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods. FPL 1992: 211-217
Coauthor Index
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