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DESB, a functional abstractor for CMOS VLSI circuits

Authors:

M. Laurentin,

A. Greiner,

R. MarbotAuthors Info & Claims

EURO-DAC '92: Proceedings of the conference on European design automation

Pages 22 - 27

Published: 01 November 1992 Publication History

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References

[1]

W. Nebel "REX, Automatic Extraction of RT Level Description from Integrated layout Data" Doctoral thesis of Kaiserslautern Univ. 1986.

Google Scholar

[2]

J.B. Guignet "DESA desassembleur de circuit CMOS VLSI" Bull internal report 1989.

Google Scholar

[3]

T. Kostelijk, B. De Loore "Automatic verification of libraxy-based IC design" IEEE J. Solid-State Circuits vo126, no 3, pp 394-403, March 1991.

Crossref

Google Scholar

[4]

D.T. Blaauw, D.G. Saab, P. Barnerjee, J.A.Abraham "Functional Abstraction of Logic Gates for Switch-Level Simulation" Proc IEEE EDAC 1991 pp 329-333 February 1991.

Digital Library

Google Scholar

[5]

A.Hajjar, A.Greiner, R.Maxbot, P.Kiani "TAS An accurate timing analyser for CMOS VLSI" Proc IEEE EDAC 1991 February 1991.

Digital Library

Google Scholar

[6]

N.P. Jouppi "Derivation of Signal Flow Direction in MOS VLSI" IEEE Trans. Computer-Aided- Design vol cad-6, no3, pp 480-490, May 1987.

Digital Library

Google Scholar

[7]

"LOGEX An Automatic Logic Extractor from Transistor to Gate Lavel for Cmos Technology" proc IEEE Design Automation Conference pp 517-522, 1988.

Digital Library

Google Scholar

[8]

R.E. Bryant "Graph-Based Algorithms for Boolean Function Manipulation" IEEE Transaction on Computers vol c-35, no 8, pp 677-685, August 1986.

Digital Library

Google Scholar

Cited By

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Dupenloup GLemeunier TMayr RSentovich E(2006)Transistor abstraction for the functional verification of FPGAsProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147179(1069-1072)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1147179
Jolly SParashkevov AMcDougall TAckland B(2002)Automated equivalence checking of switch level circuitsProceedings of the 39th annual Design Automation Conference10.1145/513918.513996(299-304)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.513996

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DESB, a functional abstractor for CMOS VLSI circuits
1. Hardware

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Published In

EURO-DAC '92: Proceedings of the conference on European design automation

November 1992

765 pages

ISBN:0818627808

Chairman:
G. Musgrave

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 November 1992

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Dupenloup GLemeunier TMayr RSentovich E(2006)Transistor abstraction for the functional verification of FPGAsProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147179(1069-1072)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1147179
Jolly SParashkevov AMcDougall TAckland B(2002)Automated equivalence checking of switch level circuitsProceedings of the 39th annual Design Automation Conference10.1145/513918.513996(299-304)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.513996

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From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators