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An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles

Authors:

Emmanuel Viaud,

François Pêcheux,

Alain GreinerAuthors Info & Claims

DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings

Pages 94 - 99

Published: 06 March 2006 Publication History

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Abstract

The paper presents an innovative simulation scheme to speed-up simulations of multi-clusters multi-processors SoCs at the TLM/T (Transaction Level Model with Time) abstraction level. The hardware components of the SoC architecture are written in standard SystemC. The goal is to describe the dynamic behavior of a given software application running on a given hardware architecture (including the dynamic contention in the interconnect and the cache effects), in order to provide the system designer with the same reliable timing information as a cycle accurate simulation, with a simulation speed similar to a TLM simulation. The key idea is to apply Parallel Discrete Event Simulation (PDES) techniques to a collection of communicating SystemC SC_THREAD. Experimental results show a simulation speedup of a factor up to 50 versus a BCA simulation (Bus Cycle Accurate), for a timing error lower than 10⁻³.

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Cited By

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Indrusiak LHarbin JDos Santos O(2015)Fast Simulation of Networks-on-Chip with Priority-Preemptive ArbitrationACM Transactions on Design Automation of Electronic Systems10.1145/275555920:4(1-22)Online publication date: 28-Sep-2015
https://dl.acm.org/doi/10.1145/2755559
Horsinka SMeyer RWagner JBuchty RBerekovic MMehdipour FDimitrakopoulos G(2014)On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design ExplorationProceedings of the 2014 International Workshop on Network on Chip Architectures10.1145/2685342.2685349(39-44)Online publication date: 13-Dec-2014
https://dl.acm.org/doi/10.1145/2685342.2685349
Harbin JIndrusiak LSilvano CCardoso JHuebner M(2014)Fine-Grained Link Locking Within Power and Latency Transaction Level Modelling in Wormhole Switching Non-Preemptive Networks On ChipProceedings of Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms10.1145/2556863.2556865(33-38)Online publication date: 20-Jan-2014
https://dl.acm.org/doi/10.1145/2556863.2556865
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Information & Contributors

Information

Published In

DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings

March 2006

1390 pages

ISBN:3981080106

General Chair:
Georges Gielen
KU Leuven, BE

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 06 March 2006

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DATE '06 Paper Acceptance Rate 267 of 834 submissions, 32%;

Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

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Indrusiak LHarbin JDos Santos O(2015)Fast Simulation of Networks-on-Chip with Priority-Preemptive ArbitrationACM Transactions on Design Automation of Electronic Systems10.1145/275555920:4(1-22)Online publication date: 28-Sep-2015
https://dl.acm.org/doi/10.1145/2755559
Horsinka SMeyer RWagner JBuchty RBerekovic MMehdipour FDimitrakopoulos G(2014)On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design ExplorationProceedings of the 2014 International Workshop on Network on Chip Architectures10.1145/2685342.2685349(39-44)Online publication date: 13-Dec-2014
https://dl.acm.org/doi/10.1145/2685342.2685349
Harbin JIndrusiak LSilvano CCardoso JHuebner M(2014)Fine-Grained Link Locking Within Power and Latency Transaction Level Modelling in Wormhole Switching Non-Preemptive Networks On ChipProceedings of Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms10.1145/2556863.2556865(33-38)Online publication date: 20-Jan-2014
https://dl.acm.org/doi/10.1145/2556863.2556865
Helmstetter CCornet JGalilée BMoy MVivet PMacii E(2013)Fast and accurate TLM simulations using temporal decoupling for FIFO-based communicationsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485573(1185-1188)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485573
Ventroux NSassolas TGuerre ACreusillet BKeryell RPérez DNiar SSilvano CAbhari M(2012)SESAM/Par4AllProceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2162131.2162133(9-16)Online publication date: 23-Jan-2012
https://dl.acm.org/doi/10.1145/2162131.2162133
Lin KCai SHuang CLin Y(2010)Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and schedulingProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899752(143-148)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899752
Mello AMaia IGreiner APecheux FDe Micheli GAl-Hashimi BMueller WMacii E(2010)Parallel simulation of SystemC TLM 2.0 compliant MPSoC on SMP workstationsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871069(606-609)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871069
Cheung EHsieh HBalarin FWakabayashi K(2009)Memory subsystem simulation in software TLM/T modelsProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509814(811-816)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509814

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