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T. N. Vijaykumar
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- affiliation: Purdue University, West Lafayette, USA
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2020 – today
- 2024
- [i10]Gokulan Ravi, Xiaokang Qiu, Mithuna Thottethodi, T. N. Vijaykumar:
QED: Scalable Verification of Hardware Memory Consistency. CoRR abs/2404.03113 (2024) - [i9]Mingxuan He, Mithuna Thottethodi, T. N. Vijaykumar:
Efficient Sparse Processing-in-Memory Architecture (ESPIM) for Machine Learning Inference. CoRR abs/2404.04708 (2024) - 2023
- [j18]Ashish Gondimalla
, Jianqiao Liu
Occam: Optimal Data Reuse for Convolutional Neural Networks. ACM Trans. Archit. Code Optim. 20(1): 12:1-12:25 (2023) - [c74]Ashish Gondimalla
Eureka: Efficient Tensor Cores for One-sided Unstructured Sparsity in DNN Inference. MICRO 2023: 324-337 - [i8]Conor Green, Cole Nelson, Mithuna Thottethodi, T. N. Vijaykumar:
SafeBet: Secure, Simple, and Fast Speculative Execution. CoRR abs/2306.07785 (2023) - 2022
- [c73]Mingxuan He, Mithuna Thottethodi, T. N. Vijaykumar:
Booster: An Accelerator for Gradient Boosting Decision Trees Training and Inference. IPDPS 2022: 1051-1062 - 2021
- [j17]Tariq Mahmood
Karma: Cost-Effective Geo-Replicated Cloud Storage with Dynamic Enforcement of Causal Consistency. IEEE Trans. Cloud Comput. 9(1): 197-211 (2021) - [c72]Sree Charan Gundabolu, T. N. Vijaykumar, Mithuna Thottethodi:
FastZ: accelerating gapped whole genome alignment on GPUs. SC 2021: 8 - [i7]Ashish Gondimalla, Sree Charan Gundabolu, T. N. Vijaykumar, Mithuna Thottethodi:
Barrier-Free Large-Scale Sparse Tensor Accelerator (BARISTA) For Convolutional Neural Networks. CoRR abs/2104.08734 (2021) - [i6]Ashish Gondimalla, Jianqiao Liu, T. N. Vijaykumar, Mithuna Thottethodi:
OCCAM: Optimal Data Reuse for Convolutional Neural Networks. CoRR abs/2106.14138 (2021) - 2020
- [j16]Jiachen Xue, T. N. Vijaykumar, Mithuna Thottethodi
Network Interface Architecture for Remote Indirect Memory Access (RIMA) in Datacenters. ACM Trans. Archit. Code Optim. 17(2): 13:1-13:22 (2020) - [j15]Jiachen Xue, Muhammad Usama Chaudhry, Balajee Vamanan
Dart: Divide and Specialize for Fast Response to Congestion in RDMA-Based Datacenter Networks. IEEE/ACM Trans. Netw. 28(1): 322-335 (2020) - [c71]Ejebagom John Ojogbo, Mithuna Thottethodi
Secure automatic bounds checking: prevention is simpler than cure. CGO 2020: 43-55 - [c70]Mingxuan He, Choungki Song, Ilkon Kim, Chunseok Jeong, Seho Kim, Il Park, Mithuna Thottethodi
Newton: A DRAM-maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning. MICRO 2020: 372-385 - [i5]Mingxuan He, T. N. Vijaykumar, Mithuna Thottethodi:
Booster: An Accelerator for Gradient Boosting Decision Trees. CoRR abs/2011.02022 (2020)
2010 – 2019
- 2019
- [c69]Ashish Gondimalla
SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks. MICRO 2019: 151-165 - 2018
- [c68]Nitin, Mithuna Thottethodi
Millipede: Die-Stacked Memory Optimizations for Big Data Machine Learning Analytics. IPDPS 2018: 160-171 - [c67]Jaichen Xue, Muhammad Usama Chaudhry, Balajee Vamanan, T. N. Vijaykumar, Mithuna Thottethodi
Fast Congestion Control in RDMA-based Datacenter Networks. SIGCOMM Posters and Demos 2018: 24-26 - [i4]Jaichen Xue, Muhammad Usama Chaudhry, Balajee Vamanan, T. N. Vijaykumar, Mithuna Thottethodi:
Dart: Divide and Specialize for Fast Response to Congestion in RDMA-based Datacenter Networks. CoRR abs/1805.11158 (2018) - 2017
- [c66]Yiyang Chang, Ashkan Rezaei, Balajee Vamanan, Jahangir Hasan, Sanjay G. Rao, T. N. Vijaykumar:
Exploring Functional Slicing in the Design of Distributed SDN Controllers. COMSNETS (Revised Selected Papers and Invited Papers) 2017: 177-199 - [c65]Yiyang Chang, Ashkan Rezaei, Balajee Vamanan
Hydra: Leveraging functional slicing for efficient distributed SDN controllers. COMSNETS 2017: 251-258 - [c64]Nitin, Mithuna Thottethodi
Efficient Collaborative Approximation in MapReduce without Missing Rare Keys. ICCAC 2017: 80-91 - [c63]Ashiwan Sivakumar, Chuan Jiang, Yun Seong Nam, Shankaranarayanan Puzhavakath Narayanan, Vijay Gopalakrishnan, Sanjay G. Rao, Subhabrata Sen, Mithuna Thottethodi
NutShell: Scalable Whittled Proxy Execution for Low-Latency Web over Cellular Networks. MobiCom 2017: 448-461 - 2016
- [i3]Yiyang Chang, Ashkan Rezaei, Balajee Vamanan, Jahangir Hasan, Sanjay G. Rao, T. N. Vijaykumar:
Hydra: Leveraging Functional Slicing for Efficient Distributed SDN Controllers. CoRR abs/1609.07192 (2016) - 2015
- [c62]Nitin, Irith Pomeranz, T. N. Vijaykumar:
FaultHound: value-locality-based soft-fault tolerance. ISCA 2015: 668-681 - [c61]Balajee Vamanan
TimeTrader: exploiting latency tail to save datacenter energy for online search. MICRO 2015: 585-597 - [i2]Balajee Vamanan, Hamza Bin Sohail, Jahangir Hasan, T. N. Vijaykumar:
TimeTrader: Exploiting Latency Tail to Save Datacenter Energy for On-line Data-Intensive Applications. CoRR abs/1503.05338 (2015) - [i1]Hamza Bin Sohail, Balajee Vamanan, T. N. Vijaykumar:
MigrantStore: Leveraging Virtual Memory in DRAM-PCM Memory Architecture. CoRR abs/1504.04297 (2015) - 2014
- [c60]Gwendolyn Voskuilen, T. N. Vijaykumar:
High-performance fractal coherence. ASPLOS 2014: 701-714 - [c59]Gwendolyn Voskuilen, T. N. Vijaykumar:
Fractal++: Closing the performance gap between fractal and conventional coherence. ISCA 2014: 409-420 - [c58]Faraz Ahmad, Srimat T. Chakradhar, Anand Raghunathan, T. N. Vijaykumar:
ShuffleWatcher: Shuffle-aware Scheduling in Multi-tenant MapReduce Clusters. USENIX ATC 2014: 1-12 - 2013
- [j14]Faraz Ahmad, Seyong Lee
MapReduce with communication overlap (MaRCO). J. Parallel Distributed Comput. 73(5): 608-620 (2013) - [c57]Syed Ali Raza Jafri, Gwendolyn Voskuilen, T. N. Vijaykumar:
Wait-n-GoTM: improving HTM performance by serializing cyclic dependencies. ASPLOS 2013: 521-534 - 2012
- [j13]Paolo Faraboschi
Top Picks from the 2011 Computer Architecture Conferences. IEEE Micro 32(3): 3-6 (2012) - [c56]Faraz Ahmad, Srimat T. Chakradhar, Anand Raghunathan
Tarazu: optimizing MapReduce on heterogeneous clusters. ASPLOS 2012: 61-74 - [c55]Balajee Vamanan
Deadline-aware datacenter tcp (D2TCP). SIGCOMM 2012: 115-126 - 2011
- [c54]Balajee Vamanan
TreeCAM: decoupling updates and lookups in packet classification. CoNEXT 2011: 27 - 2010
- [c53]Faraz Ahmad, T. N. Vijaykumar:
Joint optimization of idle and cooling power in data centers while maintaining response time. ASPLOS 2010: 243-256 - [c52]Syed Ali Raza Jafri, Mithuna Thottethodi
LiteTM: Reducing transactional state overhead. HPCA 2010: 1-12 - [c51]Gwendolyn Voskuilen, Faraz Ahmad, T. N. Vijaykumar:
Timetraveler: exploiting acyclic races for optimizing memory race recording. ISCA 2010: 198-209 - [c50]Syed Ali Raza Jafri, Yu-Ju Hong, Mithuna Thottethodi
Adaptive Flow Control for Robust Performance and Energy. MICRO 2010: 433-444 - [c49]Balajee Vamanan
EffiCuts: optimizing packet classification for memory and throughput. SIGCOMM 2010: 207-218
2000 – 2009
- 2009
- [p2]Gurindar S. Sohi, T. N. Vijaykumar:
Speculatively Multithreaded Architectures. Multicore Processors and Systems 2009: 111-143 - 2008
- [j12]Zeshan Chishti, T. N. Vijaykumar:
Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies. IEEE Trans. Computers 57(1): 69-81 (2008) - [c48]Eric Chun, Zeshan Chishti, T. N. Vijaykumar:
Shapeshifter: Dynamically changing pipeline width and speed to address process variations. MICRO 2008: 411-422 - [c47]Ahmed M. Amin, Mithuna Thottethodi
Automatic volume management for programmable microfluidics. PLDI 2008: 56-67 - 2007
- [c46]Ethan Schuchman, T. N. Vijaykumar:
BlackJack: Hard Error Detection with Redundant Threads on SMT. DSN 2007: 327-337 - [c45]Ahmed M. Amin, Mithuna Thottethodi
Aquacore: a programmable architecture for microfluidics. ISCA 2007: 254-265 - [c44]Michael D. Powell, T. N. Vijaykumar:
Resource area dilation to reduce power density in throughput servers. ISLPED 2007: 268-273 - [c43]Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykumar:
Speculative thread decomposition through empirical optimization. PPoPP 2007: 205-214 - 2006
- [j11]Alan Fern, Robert Givan, Babak Falsafi, T. N. Vijaykumar:
Dynamic feature selection for hardware prediction. J. Syst. Archit. 52(4): 213-234 (2006) - [j10]Mohamed A. Gomaa, T. N. Vijaykumar:
Opportunistic Transient-Fault Detection. IEEE Micro 26(1): 92-99 (2006) - [j9]Hilmi Ozdoganoglu, T. N. Vijaykumar, Carla E. Brodley, Benjamin A. Kuperman, Ankit Jalote:
SmashGuard: A Hardware Solution to Prevent Security Attacks on the Function Return Address. IEEE Trans. Computers 55(10): 1271-1285 (2006) - [j8]Seon Wook Kim, Chong-liang Ooi, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar:
Exploiting reference idempotency to reduce speculative storage overflow. ACM Trans. Program. Lang. Syst. 28(5): 942-965 (2006) - [c42]Chen-Yong Cher, Il Park, T. N. Vijaykumar:
Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?. ARCS 2006: 232-251 - [c41]Ethan Schuchman, T. N. Vijaykumar:
A program transformation and architecture support for quantum uncomputation. ASPLOS 2006: 252-263 - [c40]Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Saurabh Bagchi:
Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection. ICCD 2006: 514-521 - 2005
- [j7]Benjamin A. Kuperman, Carla E. Brodley, Hilmi Ozdoganoglu, T. N. Vijaykumar, Ankit Jalote:
Detection and prevention of stack buffer overflow attacks. Commun. ACM 48(11): 50-56 (2005) - [j6]Hai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar:
Combined circuit and architectural level variable supply-voltage scaling for low power. IEEE Trans. Very Large Scale Integr. Syst. 13(5): 564-576 (2005) - [c39]Jahangir Hasan, Ankit Jalote, T. N. Vijaykumar, Carla E. Brodley:
Heat Stroke: Power-Density-Based Denial of Service in SMT. HPCA 2005: 166-177 - [c38]Ethan Schuchman, T. N. Vijaykumar:
Rescue: A Microarchitecture for Testability and Defect Tolerance. ISCA 2005: 160-171 - [c37]Mohamed A. Gomaa, T. N. Vijaykumar:
Opportunistic Transient-Fault Detection. ISCA 2005: 172-183 - [c36]Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar:
Optimizing Replication, Communication, and Capacity Allocation in CMPs. ISCA 2005: 357-368 - [c35]Michael D. Powell, Ethan Schuchman, T. N. Vijaykumar:
Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines. MICRO 2005: 294-304 - [c34]Jahangir Hasan, T. N. Vijaykumar:
Dynamic pipelining: making IP-lookup truly scalable. SIGCOMM 2005: 205-216 - [e4]Babak Falsafi, T. N. Vijaykumar:
Power-Aware Computer Systems, 4th International Workshop, PACS 2004, Portland, OR, USA, December 5, 2004, Revised Selected Papers. Lecture Notes in Computer Science 3471, Springer 2005, ISBN 3-540-29790-1 [contents] - 2004
- [j5]Hai Li, Swarup Bhunia
DCG: deterministic clock-gating for low-power microprocessor design. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 245-254 (2004) - [c33]Chen-Yong Cher, Antony L. Hosking
Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign. ASPLOS 2004: 199-210 - [c32]Mohamed A. Gomaa, Michael D. Powell, T. N. Vijaykumar:
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system. ASPLOS 2004: 260-270 - [c31]T. N. Vijaykumar, Zeshan Chishti:
Wire Delay is Not a Problem for SMT (In the Near Future). ISCA 2004: 40-51 - [c30]Michael D. Powell, T. N. Vijaykumar:
Exploiting Resonant Behavior to Reduce Inductive Noise. ISCA 2004: 288-301 - [c29]Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykumar:
Min-cut program decomposition for thread-level speculation. PLDI 2004: 59-70 - [e3]Babak Falsafi, T. N. Vijaykumar:
Power-Aware Computer Systems, Third International Workshop, PACS 2003, SanDiego, CA, USA, December 1, 2003, Revised Papers. Lecture Notes in Computer Science 3164, Springer 2004, ISBN 3-540-24031-4 [contents] - 2003
- [j4]Mohamed A. Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz:
Transient-Fault Recovery for Chip Multiprocessors. IEEE Micro 23(6): 76-83 (2003) - [c28]Amit Agarwal, Kaushik Roy, T. N. Vijaykumar:
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. DATE 2003: 10778-10783 - [c27]Hai Li, Swarup Bhunia
Deterministic Clock Gating for Microprocessor Power Reduction. HPCA 2003: 113-122 - [c26]Il Park, Babak Falsafi, T. N. Vijaykumar:
Iimplicitly-Multithreaded Processors. ISCA 2003: 39-50 - [c25]Michael D. Powell, T. N. Vijaykumar:
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage. ISCA 2003: 72-83 - [c24]Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar:
Transient-Fault Recovery for Chip Multiprocessors. ISCA 2003: 98-109 - [c23]Jahangir Hasan, Satish Chandra, T. N. Vijaykumar:
Efficient Use of Memory Bandwidth to Improve Network Processor Throughput. ISCA 2003: 300-311 - [c22]Michael D. Powell, T. N. Vijaykumar:
Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise. ISLPED 2003: 223-228 - [c21]Praveen Dongara, T. N. Vijaykumar:
Accelerating private-key cryptography via multithreading on symmetric multiprocessors. ISPASS 2003: 58-69 - [c20]Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy:
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. MICRO 2003: 19-28 - [c19]Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar:
Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. MICRO 2003: 55-66 - [c18]Il Park, Chong-liang Ooi, T. N. Vijaykumar:
Reducing Design Complexity of the Load/Store Queue. MICRO 2003: 411-422 - [p1]Amit Agarwal, Kaushik Roy, T. N. Vijaykumar:
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. Embedded Software for SoC 2003: 345-358 - [e2]Babak Falsafi, T. N. Vijaykumar:
Power-Aware Computer Systems, Second International Workshop, PACS 2002 Cambridge, MA, USA, February 2, 2002, Revised Papers. Lecture Notes in Computer Science 2325, Springer 2003, ISBN 3-540-01028-9 [contents] - 2002
- [c17]Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T. N. Vijaykumar:
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay. HPCA 2002: 151-161 - [c16]T. N. Vijaykumar, Irith Pomeranz, Karl Cheng:
Transient-Fault Recovery Using Simultaneous Multithreading. ISCA 2002: 87-98 - [c15]Il Park, Michael D. Powell, T. N. Vijaykumar:
Reducing register ports for higher speed and lower energy. MICRO 2002: 171-182 - 2001
- [j3]T. N. Vijaykumar, Sridhar Gopal, James E. Smith, Gurindar S. Sohi:
Speculative Versioning Cache. IEEE Trans. Parallel Distributed Syst. 12(12): 1305-1317 (2001) - [j2]Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar:
Reducing leakage in a high-performance deep-submicron instruction cache. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 77-89 (2001) - [c14]Brannon Batson, T. N. Vijaykumar:
Reactive-Associative Caches. IEEE PACT 2001: 49-60 - [c13]Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar:
An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. HPCA 2001: 147-157 - [c12]Chong-liang Ooi, Seon Wook Kim, Il Park, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar:
Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor. ICS 2001: 368-380 - [c11]Chen-Yong Cher, T. N. Vijaykumar:
Skipper: a microarchitecture for exploiting control-flow independence. MICRO 2001: 4-15 - [c10]Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy:
Reducing set-associative cache energy via way-prediction and selective direct-mapping. MICRO 2001: 54-65 - [c9]Seon Wook Kim, Chong-liang Ooi, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar:
Reference idempotency analysis: a framework for optimizing speculative execution. PPoPP 2001: 2-11 - [e1]Babak Falsafi, T. N. Vijaykumar:
Power-Aware Computer Systems, First International Workshop, PACS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers. Lecture Notes in Computer Science 2008, Springer 2001, ISBN 3-540-42329-X [contents] - 2000
- [c8]Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar:
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories. ISLPED 2000: 90-95
1990 – 1999
- 1999
- [j1]T. N. Vijaykumar, Gurindar S. Sohi:
Task Selection for the Multiscalar Architecture. J. Parallel Distributed Comput. 58(2): 132-158 (1999) - [c7]Chris Gniady, Babak Falsafi, T. N. Vijaykumar:
Is SC + ILP=RC? ISCA 1999: 162-171 - 1998
- [c6]Sridhar Gopal, T. N. Vijaykumar, James E. Smith, Gurindar S. Sohi:
Speculative Versioning Cache. HPCA 1998: 195-205 - [c5]Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar:
Multiscalar Processors. 25 Years ISCA: Retrospectives and Reprints 1998: 521-532 - [c4]T. N. Vijaykumar, Gurindar S. Sohi:
Task Selection for a Multiscalar Processor. MICRO 1998: 81-92 - 1997
- [c3]Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi:
Dynamic Speculation and Synchronization of Data Dependences. ISCA 1997: 181-193 - 1995
- [c2]Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar:
Multiscalar Processors. ISCA 1995: 414-425 - 1994
- [c1]Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi:
The anatomy of the register file in a multiscalar processor. MICRO 1994: 181-190
Coauthor Index
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