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3DIC 2016: San Francisco, CA, USA
- 2016 IEEE International 3D Systems Integration Conference, 3DIC 2016, San Francisco, CA, USA, November 8-11, 2016. IEEE 2016, ISBN 978-1-5090-1399-9
- Jaber Derakhshandeh, Lin Hou, Inge De Preter, Carine Gerets, Samuel Suhard, Vikas Dubey
, Geraldine Jamieson, Fumihiro Inoue
Die to wafer 3D stacking for below 10um pitch microbumps. 1-4 - Ephraim Suhir, Sung Yi:
Predicted thermal stresses in a TSV design. 1-4 - Makoto Suwada, Kazuhiro Kanai:
Considerations of TSV effects on next-generation super-high-speed transmission and power integrity design for 300A-class 2.5D and 3D package integration. 1-4 - Michael Scheuermann, Shurong Tian, Raphael Robertazzi, Matthew R. Wordeman, C. Bergeron, H. Jacobson, Phillip J. Restle, Joel Silberman, Christy Tyberg:
Thermal analysis of multi-layer functional 3D logic stacks. 1-4 - Hideki Kitada, Hiroko Tashiro, Shoichi Miyahara, Takeshi Ishitsuka, Aki Dote
Study of MOSFET thermal stability with TSV in operation temperature using novel 3D-LSI stress analysis. 1-4 - Gerald Cibrario, Nour Ben Salem, Joris Lacord, Karim Azizi-Mourier, Olivier Rozeau, Etienne Maurin, Olivier Billoint, Sébastien Thuries, Alexandre Valentian:
From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purpose. 1-5 - C. Hemanth Kumar, Asisa Kumar Panigrahi
Noise performance improvement through optimized stacked layer of liner structure around the TSV in 3D IC. 1-4 - Suraj Singh, Asisa Kumar Panigrahi
Analysis of graphene and CNT based finned TTSV and spreaders for thermal management in 3D IC. 1-4 - Stefaan Van Huylenbroeck, Yunlong Li, Michele Stucchi, Lieve Bogaerts, Joeri De Vos, Gerald Beyer, Eric Beyne
Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module. 1-4 - Joeri De Vos, Lan Peng, Alain Phommahaxay, Joost Van Ongeval, Andy Miller, Eric Beyne
Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects. 1-5 - Ye Lin, Chuan Seng Tan
Through-substrate via (TSV) with embedded capacitor as an on-chip energy storage element. 1-4 - Luke England, Sukeshwar Kannan, Rahul Agarwal, Daniel Smith:
Impact of TSV integration on 14nm FinFET device performance. 1-5 - Kumail Khurram, Asisa Kumar Panigrahi
Novel inter layer dielectric and thermal TSV material for enhanced heat mitigation in 3-D IC. 1-4 - Subin Kim, Youngwoo Kim, Kyungjun Cho, Jinwook Song, Joungho Kim:
Design and analysis of on-interposer active power distribution network for an efficient simultaneous switching noise suppression in 2.5D IC. 1-5 - Cristiano Santos, Pascal Vivet
Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes. 1-5 - Brian Mattis, Lovelace Soirez, Catherine Bullock, Dave Martini, Sara Jensen, James Levy, Adam Jones:
Front-side mid-level Tungsten TSV integration for high-density 3D applications. 1-4 - Hao-Wen Liang, Hsiu-Chi Chen, Chien-Hung Lin, Chia-Lin Lee, Shan-Chun Yang, Kuan-Neng Chen:
The influence of device morphology on wafer-level bonding with polymer-coated layer. 1-4 - Yu-Tao Yang, Yu-Chen Hu, Kuan-Neng Chen:
Reliability investigation and mechanism analysis for a novel bonding method of flexible substrate in 3D integration. 1-4 - Gilad Yahalom, Stacy Ho, Alice Wang, Uming Ko, Anantha P. Chandrakasan:
Analog-digital partitioning and coupling in 3D-IC for RF applications. 1-4 - Didier Lattard, Lucile Arnaud, Arnaud Garnier, Nicolas Bresson, Franck Bana, R. Segaud, Amadine Jouve, H. Jacquinot, Stéphane Moreau
ITAC: A complete 3D integration test platform. 1-4 - Guillaume Berhault, Melanie Brocard, Sébastien Thuries, François Galea, Lilia Zaourar:
3DIP: An iterative partitioning tool for monolithic 3D IC. 1-5 - Hantao Huang, Leibin Ni, Yuhao Wang, Hao Yu, Zongwei Wang
A 3D multi-layer CMOS-RRAM accelerator for neural network. 1-5 - Muhammad Waqas Chaudhary
Interposer based integration to achieve high speed interfaces for ADC application. 1-4 - S. E. Kucuk Eroglu, W. Y. Choo, Yusuf Leblebici:
Copper TSV-based die-level via-last 3D integration process with parylene-C adhesive bonding technique. 1-5 - Mariappan Murugesan, Jichel Bea, Takafumi Fukushima
Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology. 1-4 - William Wahby, Thomas E. Sarvey, Hardik Sharma, Hadi Esmaeilzadeh, Muhannad S. Bakir:
The impact of 3D stacking on GPU-accelerated deep neural networks: An experimental study. 1-4 - Asisa Kumar Panigrahi
Low temperature CMOS compatible Cu-Cu thermo-compression bonding with constantan alloy passivation for 3D IC integration. 1-4 - Reynard Blasa, Brian Mattis, Dave Martini, Sidi Lanee, Carl Petteway, Sangki Hong, Kangsoo Yi:
High density backside tungsten TSV for 3D stacked ICs. 1-4 - Suraj Patil, Asisa Kumar Panigrahi
Improved noise coupling performance using optimized Teflon liner with different TSV structures for 3D IC integration. 1-4 - Takafumi Fukushima
New concept of TSV formation methodology using Directed Self-Assembly (DSA). 1-4 - Fang Qiao, Ilgweon Kang, Daniel Kane, Fung Yu Young, Chung-Kuan Cheng, Ronald L. Graham:
3D floorplan representations: Corner links and partial order. 1-5 - C. Roda Neve, Mikael Detalle, Philip Nolmans, Yunlong Li, Joeri De Vos, Geert Van der Plas, Gerald Beyer, Eric Beyne
High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer. 1-4 - Séverine Cheramy, Amandine Jouve, Lucile Arnaud, Claire Fenouillet-Béranger, Perrine Batude, Maud Vinet:
Towards high density 3D interconnections. 1-2 - Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi, Hidekazu Kikuchi, Azusa Yanagisawa, Akio Nakamura:
Wet cleaning process for high-yield via-last TSV formation. 1-4 - Kang Wook Lee, Ai Nakamura, Jicheol Bea, Takafumi Fukushima
Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications. 1-5 - Anne Jourdain, Joeri De Vos, Fumihiro Inoue
Extreme wafer thinning optimization for via-last applications. 1-5 - Makoto Motoyoshi, Kohki Yanagimura, Taikoh Fushimi, Junichi Takanohashi, Mariappan Murugesan, Masahiro Aoyagi, Mitsumasa Koyanagi:
3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctions. 1-4 - Montserrat Fernandez-Bolaños, Wolfgang A. Vitale, Mariazel Maqueda Lopez, Adrian M. Ionescu, Armin Klumpp, Karl-Reinhard Merkel, Josef Weber, Peter Ramm, Ilja Ocket, Walter De Raedt
3D TSV based high frequency components for RF IC and RF MEMS applications. 1-4 - Hisashi Kino
Drastic reduction of keep-out-zone in 3D-IC by local stress suppression with negative-CTE filler. 1-4 - Yang Zhang, Xuchen Zhang, William Wahby, Muhannad S. Bakir:
Design considerations for 2.5-D and 3-D integration accounting for thermal constraints. 1-5 - Kentaro Akiyama, Yusuke Oike, Yoshiaki Kitano, Junichiro Fjimagari, Wakiyama Satoru, Yorito Sakano, Takayuki Toyama, Hayato Iwamoto, Takayuki Ezaki, Takuya Nakamura, Tetsunori Imaizumi, Nonaka Yasuhiro:
A front-illuminated stacked global-shutter CMOS image sensor with multiple chip-on-chip integration. 1-3 - Ryusuke Egawa, Wataru Uno, Masayuki Sato
A power-aware LLC control mechanism for the 3D-stacked memory system. 1-4 - Rosa R. Lahiji, Timothy T. Lee, Warren P. Snapp:
3D integration and challenges for advanced RF and microwave systems: EDA perspective. 1-3 - Randy Widialaksono, Rangeen Basu Roy Chowdhury, Zhenqian Zhang, Joshua Schabel, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon
Physical design of a 3D-stacked heterogeneous multi-core processor. 1-5 - Séverine Cheramy, Amadine Jouve, Lucile Arnaud, Claire Fenouillet-Béranger, Perrine Batude, Maud Vinet:
Towards high density 3D interconnections. 1-5 - Rafael Prieto, Perceval Coudrain
Heat spreading packaging solutions for hybrid bonded 3D-ICs. 1-6 - Yangyang Yan, Ziyue Zhang
Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias. 1-5 - Rosa R. Lahiji, Timothy T. Lee, Warren P. Snapp:
3D integration and challenges for advanced RF and microwave systems: EDA perspective. 1-2
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