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WCAE@ISCA 2004: Munich, Germany
- Edward F. Gehringer:
Proceedings of the 2004 workshop on Computer architecture education - Held in conjunction with the 31st International Symposium on Computer Architecture, WCAE@ISCA 2004, Munich, Germany, June 19, 2004. ACM 2004, ISBN 978-1-4503-4733-4
Welcome and invited talk
- Edward F. Gehringer:
Welcome. 1 - Reiner W. Hartenstein:
The changing role of computer architecture education within CS curricula: invited presentation. 2
Field programmable gate arrays
- Yutaka Sugawara, Kei Hiraki:
A computer architecture education curriculum through the design and implementation of original processors using FPGAs. 3 - Vanderlei Bonato
, Ricardo Menotti
Teaching embedded systems with FPGAs throughout a computer science course. 4 - Michael Manzke
Extending FPGA based teaching boards into the area of distributed memory multiprocessors. 5
HDLs and other topics
- Sandro Rigo, Marcio Juliato, Rodolfo Azevedo
Teaching computer architecture using an architecture description language. 6 - Hagen Schendel, Carsten Albrecht, Erik Maehle:
RTeasy: an algorithmic design environment on register transfer level. 7 - Rajendra G. Singh, Margaret A. Bernard, Ross Gardler:
Creating sharable learning objects from existing digital course content. 8 - Paul Amblard, Fabienne Lagnier, Michel Lévy:
Introduction to formal processor verification at logic level: a case study. 9
Keynote
- William J. Dally:
The case for broader computer architecture education: keynote address. 10
Visualization
- Axel Böttcher
Visualizing the MMIX superscalar pipeline: not only for teaching purposes. 11 - Peter Marwedel, Birgit Sirocic:
Bridges to computer architecture education. 12
Poster session
- José M. Claver
Improving Instruction Set Architecture learning results. 13 - Mouna Nakkar
Integrating research and e-learning in advanced computer architecture courses. 14 - Liang Cheng, Dale Parson:
Bridging undergraduate learning and research in software and hardware. 15 - Milos Becvár:
Teaching basics of instruction pipelining with HDLDLX. 16 - Marius Cornea:
Software implementations of division and square root operations for Intel® Itanium® processors. 17 - Anastas Misev
Visual simulator for ILP dynamic OOO processor. 18 - Irina Branovic, Roberto Giorgi, Enrico Martinelli:
WebMIPS: a new web-based MIPS simulation environment for computer architecture education. 19 - Roger Luis Uy
DARC2: 2nd generation DLX architecture simulator. 20 - Seikoh Nishita:
MKit simulator for introduction of computer architecture. 21
Simulation environments
- Vijay Janapa Reddi, Alex Settle, Daniel A. Connors, Robert S. Cohn:
PIN: a binary instrumentation tool for computer architecture research and education. 22 - Roland N. Ibbett:
A simulation applet for microcoding exercises. 23 - Kenji Kise, Takahiro Katagiri, Hiroki Honda, Toshitsugu Yuba:
The SimCore/Alpha Functional Simulator. 24 - Helmut Bähring, Jörg Keller, Wolfram Schiffmann:
A combined virtual and remotely accessible microprocessor laboratory. 25
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