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A computer architecture education curriculum through the design and implementation of original processors using FPGAs

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WCAE '04: Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture

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https://doi.org/10.1145/1275571.1275576

Published: 19 June 2004 Publication History

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In this paper, we present the new curriculum of the processor laboratory of the Department of Computer Science at the University of Tokyo. This laboratory is a part of the computer architecture education curriculum. In this laboratory, students design and implement their own processors using field-programmable gate arrays (FPGAs), and write the necessary software. In 2003, the curriculum of the laboratory was changed, the main change being that the FPGA was changed to a large one to increase the range of design trade-offs. As a result, students have been enabled to implement the techniques used in modern processors such as FPU, cache, branch prediction, and superscalar architecture. In this paper, we detail the new curriculum and note the educational results of the year following the changes. Especially, we focus on the educational advantages of the large FPGA size.

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Curtsinger CWeinman J(2021)PIPS: An Instruction Set Architecture for Teaching Computer Organization2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)10.1109/WCAE53984.2021.9707151(1-8)Online publication date: 17-Jun-2021
https://doi.org/10.1109/WCAE53984.2021.9707151
Sundar STayal V(2021)8-Bit Electromechanical Processor Design for Education in Digital ComputationRecent Advances in Manufacturing, Automation, Design and Energy Technologies10.1007/978-981-16-4222-7_60(533-541)Online publication date: 12-Oct-2021
https://doi.org/10.1007/978-981-16-4222-7_60
Tomari HHiraki K(2015)Keeping old computers alive for deeper understanding of computer architectureProceedings of the Workshop on Computer Architecture Education10.1145/2795122.2795127(1-7)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2795122.2795127
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A computer architecture education curriculum through the design and implementation of original processors using FPGAs
1. Social and professional topics
  1. Professional topics
    1. Computing education
      1. Computing education programs

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WCAE '04: Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture

June 2004

139 pages

ISBN:9781450347334

DOI:10.1145/1275571

Conference Chair:
Edward F. Gehringer

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 19 June 2004

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Curtsinger CWeinman J(2021)PIPS: An Instruction Set Architecture for Teaching Computer Organization2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)10.1109/WCAE53984.2021.9707151(1-8)Online publication date: 17-Jun-2021
https://doi.org/10.1109/WCAE53984.2021.9707151
Sundar STayal V(2021)8-Bit Electromechanical Processor Design for Education in Digital ComputationRecent Advances in Manufacturing, Automation, Design and Energy Technologies10.1007/978-981-16-4222-7_60(533-541)Online publication date: 12-Oct-2021
https://doi.org/10.1007/978-981-16-4222-7_60
Tomari HHiraki K(2015)Keeping old computers alive for deeper understanding of computer architectureProceedings of the Workshop on Computer Architecture Education10.1145/2795122.2795127(1-7)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2795122.2795127
Udugama LGeeganage JGehringer E(2006)Students' experimental processorProceedings of the 2006 workshop on Computer architecture education: held in conjunction with the 33rd International Symposium on Computer Architecture10.1145/1275620.1275632(7-es)Online publication date: 17-Jun-2006
https://dl.acm.org/doi/10.1145/1275620.1275632

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A program design for computer education for teacher education colleges

Harnessing FPGAs for Computer Architecture Education

Introduction to using FPGAs in the computer science curriculum (abstract only)

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