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39th ESSCIRC 2013, Bucharest, Romania
- ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference, Bucharest, Romania, September 16-20, 2013. IEEE 2013, ISBN 978-1-4799-0643-7
- Reinhard Ploss:
Presentation "Automotive electronics and energy efficiency". 1-2 - Witold P. Maszara, M.-R. Lin:
FinFETs - Technology and circuit design challenges. 3-8 - Stefan Finkbeiner:
MEMS for automotive and consumer electronics. 9-14 - Timothy J. Blanche, Joshua Paul van Kleef, Peter Ledochowitsch, Travis L. Massey, Rikky Muller, Dongjin Seo, Michel M. Maharbiz:
Cyborg insects, neural dust and other things: Building interfaces between the synthetic and the multicellular. 15 - Jesús A. del Alamo:
Nanometer-scale InGaAs Field-Effect Transistors for THz and CMOS technologies. 16-21 - Emmanuel J. Candès, Stephen Becker:
Compressive sensing: Principles and hardware implementations. 22-23 - Boris Murmann
:
Digitally assisted data converter design. 24-31 - Peter R. Kinget
Scaling analog circuits. 32 - Zhipeng Li, Yan Li, Yehuda Avniel, Alexandre Megretski, Vladimir Stojanovic:
Design trade-offs in signal component separators for outphasing power amplifiers. 33-36 - Vinod Kumar, Mohd. Rizvi:
Power sequence free 400Mbps 90µW 6000µm2 1.8V-3.3V stress tolerant I/O buffer in 28nm CMOS. 37-40 - Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung:
All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate. 41-44 - Yusuke Niki, Daisuke Miyashita, Hiroyuki Kobayashi, Shouhei Kousai:
A supply-noise-rejection technique in ADPLL with noise-cancelling current source. 45-48 - Michele Caruso, Matteo Bassi
Wideband 2-16GHz local oscillator generation for short-range radar applications. 49-52 - Chih-Hsiang Chang, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng, Nai-Chen Cheng:
A 3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS. 53-56 - Edith Beigné
A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. 57-60 - Michael Schaffner, Pierre Greisen, Simon Heinzle, Frank K. Gürkaynak, Hubert Kaeslin, Aljoscha Smolic:
MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping. 61-64 - Christos Vezyrtzis, Weiwei Jiang, Steven M. Nowick, Yannis P. Tsividis:
A flexible, clockless digital filter. 65-68 - Stefan Shopov, Andreea Balteanu, Sorin P. Voinigescu:
A 19-dBm, 15-Gbaud, 9-bit SOI CMOS power-DAC cell for high-order QAM W-band transmitters. 69-72 - Chuang Lu, Marion K. Matters-Kammerer, Reza Mahmoudi, Peter G. M. Baltus, Ernst Habekotté, Koen van Hartingsveldt, Floris van der Wilt:
A 48 GHz 6-bit LO-path phase shifter in 40-nm CMOS for 60 GHz applications. 73-76 - Samuel Foulon, Sébastien Pruvost, Denis Pache, Christophe Loyez
A 142GHz fully integrated wireless chip to chip communication system for high data rate operation. 77-80 - Konstantin Statnikov, Erik Öjefors, Janusz Grzyb, Pascal Chevalier
A 0.32 THz FMCW radar system based on low-cost lens-integrated SiGe HBT front-ends. 81-84 - Yang Guo, Christopher Aquino, David Zhang, Boris Murmann
A four-channel, ±36 V, 780 kHz piezo driver chip for structural health monitoring. 85-88 - Haifeng Ma, Ronan A. R. van der Zee
An integrated 80-V class-D power output stage with 94% efficiency in a 0.14µm SOI BCD process. 89-92 - Weixun Yan, Thomas Christen:
A 443-µA 37.8-nV/√Hz CMOS multi-stage bandgap voltage reference. 93-96 - Fabrizio Conso, Gabriele Rescio
A 0.25-mm CMOS, 7-ppm/°C, 8-mA quiescent current, ±5-mA output current low-dropout voltage regulator. 97-100 - Vladimir M. Milovanovic, Horst Zimmermann
A 40 nm LP CMOS self-biased continuous-time comparator with sub-100ps delay at 1.1V & 1.2mW. 101-104 - Rolf Becker, Aleksandar Zhelyazkov, Bernie Kim:
On-chip temperature compensation of driver voltage for LC-displays. 105-108 - Albert H. Chang, Hae-Seung Lee, Duane S. Boning:
A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration. 109-112 - Jayanth Kuppambatti, Peter R. Kinget
A low power zero-crossing pipeline-SAR ADC with on-chip dynamically loaded pre-charged reference. 113-116 - Vaibhav Tripathi, Boris Murmann
An 8-bit 450-MS/s single-bit/cycle SAR ADC in 65-nm CMOS. 117-120 - Yu Lin, Kostas Doris, Erwin Janssen, Athon Zanikopoulos, Alessandro Murroni, Gerard van der Weide, Hans Hegt, Arthur H. M. van Roermund:
An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals. 121-124 - Jorge Pernillo, Michael P. Flynn:
A 9b 2GS/s 45mW 2X-interleaved ADC. 125-128 - Francesco Radice, Melchiorre Bruccoleri, Marcello Ganzerli, Giorgio Spelgatti, Davide Sanzogni, Massimo Pozzoni, Andrea Mazzanti:
A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS. 129-132 - Patrick P. Mercier
A 78 pW 1 b/s 2.4 GHz radio transmitter for near-zero-power sensing applications. 133-136 - Meysam Zargham, P. Glenn Gulak:
A 0.13µm CMOS integrated wireless power receiver for biomedical applications. 137-140 - Sohmyung Ha
85 dB dynamic range 1.2 mW 156 kS/s biopotential recording IC for high-density ECoG flexible active electrode array. 141-144 - Shintaro Izumi, Ken Yamashita, Masanao Nakano, Toshihiro Konishi, Hiroshi Kawaguchi
A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system. 145-148 - Philipp Schönle
A DC-connectable multi-channel biomedical data acquisition ASIC with mains frequency cancellation. 149-152 - Sujan K. Manohar, Poras T. Balsara:
94.6% peak efficiency DCM buck converter with fast adaptive dead-time control. 153-156 - Ruei-Hong Peng, Tsu-Wei Tsai, Ke-Horng Chen
Switching-based charger with continuously built-in resistor detector (CBIRD) and analog multiplication-division unit (AMDU) for fast charging in Li-Ion battery. 157-160 - Rares Bodnar, William Redman-White:
An integrated ultracapacitor fast mains charger with combined power/current optimisation. 161-164 - Piet Callemeyn, Michiel Steyaert
A monolithic stacked Class-D approach for high voltage DC-AC conversion in standard CMOS. 165-168 - Davide Cartasegna, Piero Malcovati
A 0.18-µm CMOS, -92-dB THD, 105-dBA DR, third-order audio class-D amplifier. 169-172 - Songting Li, Jiancheng Li, Xiaochen Gu, Hongyi Wang, Jianfei Wu, Dun Yan, Zhaowen Zhuang:
Dual-band RF receiver for GPS and compass systems in 55-nm CMOS. 173-176 - Nan Qi, Baoyong Chi, Yang Xu, Zhou Chen, Yang Xu, Jun Xie, Zheng Song, Zhihua Wang:
A 180nm fully-integrated dual-channel reconfigurable receiver for GNSS interoperations. 177-180 - Alan W. L. Ng, S. Y. Zheng, H. Leung, Y. Chao, Howard C. Luong
A 0.9GHz-5.8GHz SDR receiver front-end with transformer-based current-gain boosting and 81-dB 3rd-order-harmonic rejection ratio. 181-184 - Ashkan Borna, Chris Hull, Yanjie Wang, Hua Wang
An RF receiver with an integrated adaptive notch filter for multi-standard applications. 185-188 - Gauthier Tant, Alexandre Giry, Pierre Vincent, Jean-Daniel Arnould, Jean-Michel Fournier:
A 2.14GHz watt-level power amplifier with passive load modulation in a SOI CMOS technology. 189-192 - Mihail Jefremow, Thomas Kern, Ulrich Backhausen, J. Elbs, B. Rousseau, Christoph Roll, L. Castro, T. Roehr, E. Paparisto, K. Herfurth, R. Bartenschlager, Stefanie Thierold, R. Renardy, Stephan Kassenetter, N. Lawal, M. Strasser, W. Trottmann, Doris Schmitt-Landsiedel:
A 65nm 4MB embedded flash macro for automotive achieving a read throughput of 5.7GB/s and a write throughput of 1.4MB/s. 193-196 - Oskar Andersson
Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS. 197-200 - Bram Rooseleer, Wim Dehaene:
A 40 nm, 454MHz 114 fJ/bit area-efficient SRAM memory with integrated charge pump. 201-204 - Fady Abouzeid
Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI. 205-208 - Anh Tuan Do, Chun Yin, Kiat Seng Yeo, Tony Tae-Hyoung Kim:
Design of a power-efficient CAM using automated background checking scheme for small match line swing. 209-212 - Dan Stoica, Mario Motz:
A dual vertical Hall latch with direction detection. 213-216 - J. Jiang, Kofi A. A. Makinwa, Wilko J. Kindt:
A continuous-time ripple reduction technique for spinning-current Hall sensors. 217-220 - Kamran Souri, Kianoush Souri, Kofi A. A. Makinwa:
A 40µW CMOS temperature sensor with an inaccuracy of ±0.4°C (3σ) from -55°C to 200°C. 221-224 - Mina Shahmohammadi, Kianoush Souri, Kofi A. A. Makinwa:
A resistor-based temperature sensor for MEMS frequency references. 225-228 - Cyril Condemine, Jérôme Willemin
128 nodes 4.5 mm pitch 15-bit pressure sensor ribbon. 229-232 - Raghavasimhan Thirunarayanan, David Ruffieux, Christian C. Enz:
An injection-locking based programmable fractional frequency divider with 0.2 division step for quantization noise reduction. 233-236 - Tapio Rapinoja, Kari Stadius, Jussi Ryynänen
A 0.3-to-8.5GHz frequency synthesizer based on digital period synthesis. 237-240 - Seyed Amir Reza Ahmadi Mehr
Frequency translation through fractional division for a two-channel pulling mitigation. 241-244 - Michael Peter Kennedy, Brian Fitzgibbon, Austin Harney, Hyman Shanan, Mike Keaveney:
High speed, high accuracy fractional-N frequency synthesizer using nested mixed-radix digital Δ-Σ modulators. 245-248 - Bichoy Bahr, Radhika Atul Marathe, Wentao Wang, Dana Weinstein:
Solid state RF MEMS resonators in standard CMOS. 249-252 - Arokia Nathan, Sungsik Lee, Sanghun Jeon:
Oxide electronics for imaging and displays. 253-254 - Krishna V. Palem, Avinash Lingamneni, Christian C. Enz, Christian Piguet:
Why design reliable chips when faulty ones are even better. 255-258 - Junyoung Park, Byeong-Gyu Nam
A high-throughput 16× super resolution processor for real-time object recognition SoC. 259-262 - Upasna Vishnoi, Tobias G. Noll:
Cross-layer optimization of QRD accelerators. 263-266 - Toshinobu Akazawa, Seiryu Sasaki, Hans Jürgen Mattausch:
Word-parallel coprocessor architecture for digital nearest Euclidean distance search. 267-270 - Tobias Gemmeke
In-situ performance monitor employing threshold based notifications (TheBaN). 271-274 - Charles Wu, Borivoje Nikolic
A 0.4 GHz - 4 GHz direct RF-to-digital ΣΔ multi-mode receiver. 275-278 - Anders Nejdel, Markus Törmänen, Henrik Sjöland
A 0.7 - 3.7 GHz six phase receiver front-end with third order harmonic rejection. 279-282 - Nicola Codega, Antonio Liscidini
A low out-of-band noise LTE transmitter with current-mode approach. 283-286 - Eric Muijs, Paulo Silva, Arie van Staveren, Wouter A. Serdijn:
A 39 dB DR CMOS log-amp RF power detector with ±1.1 dB temperature drift from -40 to 85°C. 287-290 - Ilkka Nissinen
2×(4×)128 time-gated CMOS single photon avalanche diode line detector with 100 ps resolution for Raman spectroscopy. 291-294 - Lucio Pancheri
Compact analog counting SPAD pixel with 1.9% PRNU and 530ps time gating. 295-298 - Andreas Süss, Christian Nitta, Andreas Spickermann, Daniel Durini
Speed considerations for LDPD based time-of-flight CMOS 3D image sensors. 299-302 - Michele Benetti, Massimo Gottardi, Zeev Smilansky:
A 80µW 30fps 104 × 104 all-nMOS pixels CMOS imager with 7-bit PWM ADC for robust detection of relative intensity change. 303-306 - Valentijn De Smedt
A 40nm-CMOS, 72 µW injection-locked timing reference and 1.8 Mbit/s coordination receiver for wireless sensor networks. 307-310 - Mino Kim, Woo-Yeol Shin, Gi-Moon Hong, Jihwan Park, Joo-Hyung Chae
High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line. 311-314 - Keishi Tsubaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A 32.55-kHz, 472-nW, 120ppm/°C, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application. 315-318 - Sebastian Zeller, Christian Muenker, Robert Weigel:
A 0.039mm2 inverter-based 1.82mW 68.6dB-SNDR 10MHz-BW CT-ΣΔ-ADC in 65nm CMOS. 319-322 - Mattias Andersson, Martin Anderson, Lars Sundström
A 9MHz filtering ADC with additional 2nd-order ΔΣ modulator noise suppression. 323-326 - Xinpeng Xing, Peng Gao
A 40MHz-BW two-step open-loop VCO-based ADC with 42fJ/step FoM in 40nm CMOS. 327-330 - Noël Deferm, Wouter Volkaerts, Juan F. Osorio, Anton de Graauw, Michiel Steyaert
A 120GHz fully integrated 10Gb/s wireless transmitter with on-chip antenna in 45nm low power CMOS. 331-334 - Maarten Tytgat, Patrick Reynaert
A plastic waveguide receiver in 40nm CMOS with on-chip bondwire antenna. 335-338 - Cecilia Gimeno, Carlos Sánchez-Azqueta
A 1-V 1.25-Gbps CMOS analog front-end for short reach optical links. 339-342 - Giovanni Capodivacca, Paolo Milanesi, Andrea Scenini:
Integrated buck LED driver with application specific digital architecture. 343-346 - Vlad Anghel
Variable off time current-mode floating buck controller - A different approach. 347-350 - Wen-Shen Chou, Po-Hsien Huang, Ming-Yan Fan, Ke-Horng Chen
Embedded fully self-biased switched-capacitor for energy and area-efficient cholesteric LCD drivers. 351-354 - Jan Nissinen
A 4 a peak current and 2 ns pulse width CMOS laser diode driver for high measurement rate applications. 355-358 - Alexander Schmidt, Holger Kappert, Rainer Kokozinski
High temperature analog circuit design in PD-SOI CMOS technology using reverse body biasing. 359-362 - Philipp Schröter, Magnus-Maria Hell, Martin Frey:
EMC compliant LIN transceiver. 363-366 - Serena Porrazzo, Venkata Narasimha Manyam
A 1-V 99-to-75dB SNDR, 256Hz-16kHz bandwidth, 8.6-to-39µW reconfigurable SC ΔΣ Modulator for autonomous biomedical applications. 367-370 - Yao Liu, Edoardo Bonizzoni, Alessandro D'Amato, Franco Maloberti:
A 105-dB SNDR, 10 kSps multi-level second-order incremental converter with smart-DEM consuming 280 µW and 3.3-V supply. 371-374 - Fabio Sebastiano
A 0.1-mm2 3-channel area-optimized ΣΔ ADC in 0.16-µm CMOS with 20-kHz BW and 86-dB DR. 375-378 - Jia Mao, Zhuo Zou, Li-Rong Zheng:
A 35 pJ/pulse injection-locking based UWB transmitter for wirelessly-powered RFID tags. 379-382 - Toshiki Wada, Masayuki Ikebe, Eiichi Sano:
60-GHz, 9-µW wake-up receiver for short-range wireless communications. 383-386 - Heinrich Milosiu, Frank Oehler, Markus Eppel, Dieter Frühsorger, Stephan Lensing, Gralf Popken, Thomas Thönes:
A 3-µW 868-MHz wake-up receiver with -83 dBm sensitivity and scalable data rate. 387-390 - Fridolin Michel, Michiel Steyaert
EMI resisting voltage regulator with large signal PSR up to 1GHz. 391-394 - Stefan Dietrich, Lei Liao, Frank Vanselow, Ralf Wunderlich, Stefan Heinen:
A 1mV voltage ripple 0.97mm2 fully integrated low-power hybrid buck converter. 395-398 - Pierre Gasnier
An autonomous piezoelectric energy harvesting IC based on a synchronous multi-shots technique. 399-402 - Teerachot Siriburanon
A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs. 403-406 - Luca Fanori, Pietro Andreani:
A high-swing complementary class-C VCO. 407-410 - Wouter Steyaert, Patrick Reynaert
A 0.54 THz signal generator in 40 nm bulk CMOS with 22 GHz tuning range. 411-414 - Vivek Asthana, Malathi Kar, Jean Jimenez, Jean-Philippe Noel, Sébastien Haendler, Philippe Galy:
Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control. 415-418 - Jente B. Kuang, Keith A. Jenkins, Kevin Stawiasz, Jeremy D. Schaub:
Performance impact of through-silicon vias (TSVs) in three-dimensional technology measured by SRAM ring oscillators. 419-422 - Ramkumar Ganesan, Jürgen Krumm, Sebastian Pankalla, Klaus Ludwig, Manfred Glesner:
Design of an organic electronic label on a flexible substrate for temperature sensing. 423-426 - Viorel Banu
High temperature-low temperature coefficient analog voltage reference integrated circuit implemented with SiC MESFETs. 427-430
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