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DSD 2014: Verona, Italy
- 17th Euromicro Conference on Digital System Design, DSD 2014, Verona, Italy, August 27-29, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-5793-4
Reconfigurable Computing 1 (RC1)
- Princewill Akpojotor, Ayodeji Oluwatope, Kayode Ayodele, G. Adesola Aderounmu
, Emmanuel Rotimi Adagunodo:
A Field Programmable Gate Array-Based Digital Temperature Sensor with Improved Immunity to Static Supply Shift. 1-8 - Antonios Prodromakis, Stelios Korkotsides, Theodore Antonakopoulos:
A Versatile Emulator for the Aging Effect of Non-volatile Memories: The Case of NAND Flash. 9-15
Flexible Digital Radio (FDR)
- Vincent Berg, Jean-Baptiste Dore
A Multiuser FBMC Receiver Implementation for Asynchronous Frequency Division Multiple Access. 16-21 - Matthieu Gautier
Design Space Exploration in an FPGA-Based Software Defined Radio. 22-27 - Nikolaos Zompakis
Systematic Exploration of Power-Aware Scenarios for IEEE 802.11ac WLAN Systems. 28-35 - Frederic Drillet, Mohamad Hamieh, Lounis Zerioul, Alexandre Briere, Eren Unlu, Myriam Ariaudo, Yves Louët, Emmanuelle Bourdel, Julien Denoulet, Andréa Pinna, Bertrand Granado
Flexible Radio Interface for NoC RF-Interconnect. 36-41
Reconfigurable Computing 2 (RC2)
- Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee
Morphable Compression Architecture for Efficient Configuration in CGRAs. 42-49 - Bouthaina Damak, Rachid Benmansour
Design Space Exploration for Customized Asymmetric Heterogeneous MPSoC. 50-57
Reconfigurable Computing 3 (RC3)
- Pierre Bomel, Kevin J. M. Martin, Jean-Philippe Diguet:
Virtual Devices for Hot-Pluggable Processors. 58-65 - B. Sharat Chandra Varma
High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs. 66-73 - Éricles Sousa, Deepak Gangadharan
Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures. 74-81
High Performance Video Processing (HPVP)
- Ang Li, Akash Kumar
Accelerating Volume Image Registration through Correlation Ratio Based Methods on GPUs. 82-89 - Luis Araneda, Miguel E. Figueroa
Real-Time Digital Video Stabilization on an FPGA. 90-97
Dependability, Testing and Fault Tolerance in Digital Systems
- Halil Kukner, Pieter Weckx, Sebastien Morrison, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre
NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes. 98-107 - Jaak Kousaar, Raimund Ubar
Critical Path Tracing Based Simulation of Transition Delay Faults. 108-113 - Ralph Nyberg, Jürgen Nolles, Johann Heyszl, Dirk Rabe, Georg Sigl:
Closing the Gap between Speed and Configurability of Multi-bit Fault Emulation Environments for Security and Safety-Critical Designs. 114-121
Power Design (PD)
- Manuel Menghin, Norbert Druml, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid:
Development Framework for Model Driven Architecture to Accomplish Power-Aware Embedded Systems. 122-128 - Daniel Lorenz, Kim Grüttner, Wolfgang Nebel:
Data-and State-Dependent Power Characterisation and Simulation of Black-Box RTL IP Components at System Level. 129-136
Synchronisation (SYNC)
- Christoph Roth, Simon Reder, Harald Bucher, Oliver Sander, Jürgen Becker
Adaptive Algorithm and Tool Flow for Accelerating System C on Many-Core Architectures. 137-145 - Fardin Derogarian, João Canas Ferreira
A Time Synchronization Circuit with an Average 4.6 ns One-Hop Skew for Wired Wearable Networks. 146-153
MultiProcessor System On Chip (MPSOC)
- Yong Zhao, Hans G. Kerkhoff:
Design of an Embedded Health Monitoring Infrastructure for Accessing Multi-processor SoC Degradation. 154-160 - Alessandro Cilardo, Luca Gallo:
Generating On-Chip Heterogeneous Systems from High-Level Parallel Code. 161-168
Architectures and Hardware for Security Applications 1 (AHSA1)
- Apostolos P. Fournaris, John Zafeirakis, Odysseas G. Koufopavlou:
Designing and Evaluating High Speed Elliptic Curve Point Multipliers. 169-174 - Wolfgang Wieser, Michael Hutter:
Efficient Multiplication on Low-Resource Devices. 175-182 - Kuan-Yu Tseng, Dao Lu, Zbigniew Kalbarczyk, Ravishankar K. Iyer:
AHEMS: Asynchronous Hardware-Enforced Memory Safety. 183-190
European Projects in Digital System Design 1 (EPDSD1)
- Santhosh Kumar Rethinagiri, Oscar Palomar
ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy. 191-198 - Stefano Di Carlo
Cross-Layer Early Reliability Evaluation for the Computing cOntinuum. 199-205
European Projects in Digital System Design 2 (EPDSD2)
- Yves Durand, Paul M. Carpenter
EUROSERVER: Energy Efficient Node for European Micro-Servers. 206-213 - Luís Miguel Pinho
P-SOCRATES: A Parallel Software Framework for Time-Critical Many-Core Systems. 214-221
Application Specific Pocessor 1 (ASP1)
- Rui Fiel Cordeiro, Arnaldo S. R. Oliveira
Gigasample Time-Interleaved Delta-Sigma Modulator for FPGA-Based All-Digital Transmitters. 222-227 - Massimiliano Zilli, Wolfgang Raschke, Reinhold Weiss, Johannes Loinig, Christian Steger
Instruction Folding Compression for Java Card Runtime Environment. 228-235
Design of Heterogeneous Cyber-Physical Systems (DHCPS)
- Toni Mancini
Anytime System Level Verification via Random Exhaustive Hardware in the Loop Simulation. 236-245 - Markus Becker, Christoph Kuznik, Wolfgang Mueller:
Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System Software. 246-253 - Alejandro Masrur, Michal Kit, Tomás Bures
Towards Component-Based Design of Safety-Critical Cyber-Physical Applications. 254-261 - Michele Lora, Riccardo Muradore, Riccardo Reffato, Franco Fummi:
Simulation Alternatives for Modeling Networked Cyber-Physical Systems. 262-269
Application Specific Pocessor 2 (ASP2)
- Massimiliano Zilli, Wolfgang Raschke, Reinhold Weiss, Johannes Loinig, Christian Steger
A High Performance Java Card Virtual Machine Interpreter Based on an Application Specific Instruction-Set Processor. 270-278 - Shen-Fu Hsiao, Chia-Sheng Wen, Po-Han Wu:
Compression of Lookup Table for Piecewise Polynomial Function Evaluation. 279-284
Mixed Criticality System Design, Implementation and Analysis
- Shubhendu Sinha, Martijn Koedam, Rob van Wijk, Andrew Nelson, Ashkan Beyranvand Nejad, Marc Geilen
Composable and Predictable Dynamic Loading for Time-Critical Partitioned Systems. 285-292 - Roman Obermaisser, Zaher Owda, Mohammed Abuteir, Hamidreza Ahmadian, Donatus Weber:
End-to-End Real-Time Communication in Mixed-Criticality Systems Based on Networked Multicore Chips. 293-302 - Daniel Münch, Michael Paulitsch, Michael Honold, Wolfgang Schlecker, Andreas Herkersdorf:
Iterative FPGA Implementation Easing Safety Certification for Mixed-Criticality Embedded Real-Time Systems. 303-311
Dependability, Testing and Fault Tolerance in Digital Systems
- Jakub Podivinsky, Ondrej Cekan
The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications. 312-319 - Pavel Vit, Jaroslav Borecký, Martin Kohlík, Hana Kubátová:
Fault Tolerant Duplex System with High Availability for Practical Applications. 320-325 - Lucie Matuova, Jan Kastil
Automatic Construction of On-line Checking Circuits Based on Finite Automata. 326-332 - Josef Strnadel, Martin Pokorny:
Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework. 333-340
Architecture Optimization (ARCH)
- Marianne J. Jantz, Katherine Wu, Prasad A. Kulkarni:
Properties of Dynamically Dead Instructions for Contemporary Architectures. 341-348 - KuangLun Chen, Ehsan Atoofian, Ali Manzak
Improving Power of Cache and Register File through Critical Path Instructions. 349-355
Emerging Technologies and Circuit Synthesis (ETCS)
- Pai-Shun Ting, John Patrick Hayes:
Stochastic Logic Realization of Matrix Operations. 356-364 - Sandeep Miryala, Andrea Calimera
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates. 365-371
Architectures and Hardware for Security Applications 2 (AHSA2)
- Norbert Druml, Manuel Menghin, Adnan Kuleta, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid:
A Flexible and Lightweight ECC-Based Authentication Solution for Resource Constrained Systems. 372-378 - Noemie Beringuier-Boher, Kamil Gomina, David Hély
Voltage Glitch Attacks on Mixed-Signal Systems. 379-386 - Matthias Hiller
Seesaw: An Area-Optimized FPGA Viterbi Decoder for PUFs. 387-393
Mixed Criticality System Design, Implementation and Analysis
- Jon Pérez
A Safety Certification Strategy for IEC-61508 Compliant Industrial Mixed-Criticality Systems Based on Multicore Partitioning. 394-400 - Leonidas Kosmidis
Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture. 401-410
Logic Synthesis 1 (LS1)
- Anna Bernasconi
2-SPP Approximate Synthesis for Error Tolerant Applications. 411-418 - Shuo Li, Ahmed Hemani:
Three-Dimensional Design Space Exploration for System Level Synthesis. 419-426
Logic Synthesis 2 (LS2)
- Jan Schmidt, Petr Fiser
On Robustness of EDA Tools. 427-434 - Liyuan Zhang, Joachim Falk, Tobias Schwarzer, Michael Glaß
Communication-Driven Automatic Virtual Prototyping for Networked Embedded Systems. 435-442
Logic Synthesis 3 (LS3)
- Alejandro Nicolás, Pablo Peñil
Automatic Synthesis over Multiple APIs from Uml/Marte Models for Easy Platform Mapping and Reuse. 443-450 - Matthew M. Kim, Paul Beckett:
Design Techniques for NCL-Based Asynchronous Circuits on Commercial FPGA. 451-458
Application Specific Processor 3 (ASP3)
- Pavel Benácek, Hana Kubátová, Viktor Pus:
Architecture of Effective High-Speed Network Stream Merger. 459-464 - Hassan Anwar, Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila
Parameterized AES-Based Crypto Processor for FPGAs. 465-472
Verification and Reliable Design (VRD)
- Alexandru Amaricai, Sergiu Nimara, Oana Boncalo, Jiaoyan Chen, Emanuel M. Popovici:
Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits. 473-479 - Michael Lackner, Reinhard Berlach, Michael Hraschan, Reinhold Weiss, Christian Steger:
A Fault Attack Emulation Environment to Evaluate Java Card Virtual-Machine Security. 480-487 - Usman Khalid, Antonio Mastrandrea
Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops. 488-495
Network on Chip (NoC)
- Sergei Dytckov
Efficient STDP Micro-Architecture for Silicon Spiking Neural Networks. 496-503 - Feng Wang, Xiantuo Tang, Qinglin Wang, Zuocheng Xing, Hengzhu Liu:
Flexible Virtual Channel Power-Gating for High-Throughput and Low-Power Network-on-Chip. 504-511
Architectures and Hardware for Security Applications 3 (AHSA3)
- Markus Stefan Wamser:
Ultra-Small Designs for Inversion-Based S-Boxes. 512-519 - Partha De, Kunal Banerjee, Chittaranjan A. Mandal, Debdeep Mukhopadhyay:
Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks. 520-527 - Shahin Tajik, Dmitry Nedospasov, Clemens Helfmeier, Jean-Pierre Seifert, Christian Boit:
Emission Analysis of Hardware Implementations. 528-534 - Simon Pontie, Paolo Maistri, Régis Leveugle:
An Elliptic Curve Crypto-Processor Secured by Randomized Windows. 535-542
Real-Time Custom Computing (RTCC)
- Maryam Hemmati
HOG Feature Extractor Hardware Accelerator for Real-Time Pedestrian Detection. 543-550 - Shen-Fu Hsiao, Guan-Fu Yeh, Je-Chi Chen:
Design and Implementation of Multiple-Vehicle Detection and Tracking Systems with Machine Learning. 551-558 - Oliver Stecklina, Michael Methfessel:
A Tiny Scale VLIW Processor for Real-Time Constrained Embedded Control Tasks. 559-566
Dependability, Testing and Fault Tolerance in Digital Systems
- Mohsen Raji
An Efficient Approach for Soft Error Rate Estimation of Combinational Circuits. 567-574 - Stanislaw J. Piestrak, Piotr Patronik:
Design of Fault-Secure Transposed FIR Filters Protected Using Residue Codes. 575-582 - Stefano Di Carlo
On Enhancing Fault Injection's Capabilities and Performances for Safety Critical Systems. 583-590 - Stefan Krämer, Peter Raab, Jürgen Mottok, Stanislav Racek:
Comparison of Enhanced Markov Models and Discrete Event Simulation: For Evaluation of Probabilistic Faults in Safety-Critical Real-Time Task Sets. 591-598
Synthesis (SYNT)
- Shuo Yang, Robert Wille
Improving Coverage of Simulation-Based Verification by Dedicated Stimuli Generation. 599-606 - Mahdi Jelodari Mamaghani, Jim D. Garside
Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA. 607-614
Multiprocessing Partitioning and Scheduling (MPS)
- Pranav Tendulkar, Peter Poplavko, Ioannis Galanommatis, Oded Maler:
Many-Core Scheduling of Data Parallel Applications Using SMT Solvers. 615-622 - Philip S. Wilmanns, Joost P. H. M. Hausmans, Stefan J. Geuns, Marco Jan Gerrit Bekooij:
Accuracy Improvement of Dataflow Analysis for Cyclic Stream Processing Applications Scheduled by Static Priority Preemptive Schedulers. 623-630
Poster Papers
- Suleyman Tosun, Vahid Babaei Ajabshir, Ozge Mercanoglu, Özcan Özturk:
Fault-Tolerant Irregular Topology Design Method for Network-on-Chips. 631-634 - Alper Sen, Gökçehan Kara, Etem Deniz, Smaïl Niar:
Fast System Level Benchmarks for Multicore Architectures. 635-638 - Daniel Piso Fernandez, Javier Diaz Bruguera:
A New Rounding Method Based on Parallel Remainder Estimation for Goldschmidt and Newton-Raphson Algorithms. 639-642 - Muzaffar Rao
Efficient High Speed Implementation of Secure Hash Algorithm-3 on Virtex-5 FPGA. 643-646 - Enrico Boni
Multi-channel Raw-Data Acquisition for Ultrasound Research. 647-650 - Sebastian Graf, Michael Glaß
Design Space Exploration for Automotive E/E Architecture Component Platforms. 651-654 - Wei Quan, Andy D. Pimentel
Towards Exploring Vast MPSoC Mapping Design Spaces Using a Bias-Elitist Evolutionary Approach. 655-658 - Davide Bresolin
Verification of Robotic Surgery Tasks by Reachability Analysis: A Comparison of Tools. 659-662 - Alessia Damilano, Marco Crepaldi
A 130 nm Event-Driven Voltage and Temperature Insensitive Capacitive ROC. 663-666 - Muhammad Khurram Bhatti
Noodle: A Heuristic Algorithm for Task Scheduling in MPSoC Architectures. 667-670 - Erica Tena-Sánchez
Low-Power Differential Logic Gates for DPA Resistant Circuits. 671-674 - Paris Kitsos
FPGA Trojan Detection Using Length-Optimized Ring Oscillators. 675-678 - Jiri Balcarek, Petr Fiser, Jan Schmidt:
PBO-Based Test Compression. 679-682 - David Macii
Design of a Redundant FPGA-Based Safety System for Railroad Vehicles. 683-686 - Alessandro Beghi, Fabio Marcuzzi, Mirco Rampazzo, Marco Virgulin:
Enhancing the Simulation-Centric Design of Cyber-Physical and Multi-physics Systems through Co-simulation. 687-690 - Odysseas Zografos, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Praveen Raghavan, Giovanni De Micheli
Majority Logic Synthesis for Spin Wave Technology. 691-694
Systems through Co-simulation687
- Giuseppe Vitello, Vincenzo Conti, Antonio Gentile, Salvatore Vitabile
Design and Implementation of an Efficient Fingerprint Features Extractor. 695-699 - Janek Mann, Ion Emilian Radoi, D. K. Arvind:
Prospeckz-5 - A Wireless Sensor Platform for Tracking and Monitoring of Wild Horses. 700-703 - Karel Szurman, Lukas Miculka, Zdenek Kotásek:
State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System. 704-707 - Martin Lukac, Maher Hawash, Michitaka Kameyama, Marek A. Perkowski, Pawel Kerntopf:
Minimizing Reversible Circuits in the 2n Scheme Using Two and Three Bits Patterns. 708-711
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