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Josef Strnadel
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2020 – today
- 2024
- [c29]Jakub Lojda, Josef Strnadel, Václav Simek, Pavel Smrz, Mike Hayes, Ralf Popp:
The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things. DSD 2024: 604-611 - 2022
- [c28]Josef Strnadel:
Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking. DDECS 2022: 88-93 - 2021
- [c27]Josef Strnadel:
Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults. DDECS 2021: 111-114 - 2020
- [c26]Josef Strnadel
:
Statistical Model Checking of Approximate Circuits: Challenges and Opportunities. DATE 2020: 1574-1577
2010 – 2019
- 2019
- [c25]Josef Strnadel
Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates. DATE 2019: 614-617 - 2018
- [j4]Josef Strnadel
Predictability Analysis of Interruptible Systems by Statistical Model Checking. IEEE Des. Test 35(2): 57-63 (2018) - [c24]Josef Strnadel
Statistical Model Checking of Processor Systems in Various Interrupt Scenarios. ISoLA (2) 2018: 414-429 - 2017
- [c23]Josef Strnadel:
On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking. DSD 2017: 352-355 - 2016
- [c22]Josef Strnadel:
On Creation and Analysis of Reliability Models by Means of Stochastic Timed Automata and Statistical Model Checking: Principle. ISoLA (1) 2016: 166-181 - 2015
- [c21]Josef Strnadel:
Comparison of Generally Applicable Mechanisms for Preventing Embedded Event-Driven Real-Time Systems from Interrupt Overloads. ECBS-EERC 2015: 39-44 - 2014
- [j3]Josef Strnadel, Frantisek Slimarik:
Impact of Software Fault Tolerance to Fault Effects in OS-Driven RT Systems. Comput. Informatics 33(4): 757-782 (2014) - [c20]Josef Strnadel, Martin Pokorny:
Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework. DSD 2014: 333-340 - 2013
- [c19]Josef Strnadel
Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates. ARCS 2013: 98-109 - [c18]Josef Strnadel:
On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems. DDECS 2013: 24-29 - 2012
- [c17]Josef Strnadel
Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systems. DDECS 2012: 121-126 - [c16]Josef Strnadel
On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels. DSD 2012: 272-279 - 2011
- [c15]Michal Rumplík, Josef Strnadel
On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits. DSD 2011: 367-374 - 2010
- [c14]Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel
Reduction of power dissipation through parallel optimization of test vector and scan register sequences. DDECS 2010: 364-369 - [c13]Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel
The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. DSD 2010: 644-651 - [c12]Jaroslav Skarvada, Zdenek Kotásek, Josef Strnadel
The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. ICES 2010: 181-192
2000 – 2009
- 2008
- [j2]Josef Strnadel, Tomas Pecenka, Zdenek Kotásek:
Measuring CADeT Performance by Means of FITTest_BENCH06 Benchmark Circuits. Comput. Informatics 27(6): 913-930 (2008) - [c11]Josef Strnadel
TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path. DSD 2008: 865-872 - 2007
- [c10]Richard Ruzicka, Josef Strnadel:
Test Controller Synthesis Constrained by Circuit Testability Analysis. DSD 2007: 626-633 - 2006
- [j1]Josef Strnadel:
Testability Analysis and Improvements of Register-Transfer Level Digital Circuits. Comput. Artif. Intell. 25(5): 441-464 (2006) - [c9]Josef Strnadel:
Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-Space. DDECS 2006: 161-162 - [c8]Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina:
Testability Estimation Based on Controllability and Observability Parameters. DSD 2006: 504-514 - [c7]Josef Strnadel, Arghya Kumar Dhali:
Novel Optimizing Approach in the Area of STEP-Based Construction of Sessionless, Power-Constrainted, TAM and Time Optimal Test Schedules. ECBS 2006: 360-367 - [c6]Josef Strnadel, Zdenek Kotásek:
SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. ECBS 2006: 497-498 - 2005
- [c5]Josef Strnadel, Zdenek Kotásek:
Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. DSD 2005: 420-427 - [c4]Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel:
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Evolvable Hardware 2005: 51-58 - 2004
- [c3]Daniel Mika, Josef Strnadel, Zdenek Kotásek:
The Identification of registers in RTL Structures for the Test Application. ISoLA (Preliminary proceedings) 2004: 317-319 - 2003
- [c2]Zdenek Kotásek, Daniel Mika, Josef Strnadel
Test scheduling for embedded systems. DSD 2003: 463-467 - 2002
- [c1]Josef Strnadel, Zdenek Kotásek:
Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. DSD 2002: 166-173
Coauthor Index
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