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NANOARCH 2007: San Jose, CA, USA
- 2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH 2007, San Jose, CA, USA, October 21-22, 2007. IEEE Computer Society 2007, ISBN 978-1-4244-1790-2
- Shuo Wang, Lei Wang, Faquir C. Jain:
Dynamic redundancy allocation for reliable and high-performance nanocomputing. 1-6 - Tzvetan S. Metodi, Andrew W. Cross
, Darshan D. Thaker, Isaac L. Chuang, Frederic T. Chong
Design-space exploration of fault-tolerant building blocks for large-scale quantum computing. 7-14 - Ashish Kumar Singh, Hady Ali Zeineddine, Adnan Aziz, Sriram Vishwanath, Michael Orshansky:
A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions. 15-20 - Jianwei Dai, Lei Wang, Faquir C. Jain:
Analysis of defect tolerance in molecular electronics using information-theoretic measures. 21-26 - Kyosun Kim, Ramesh Karri
Design automation for hybrid CMOS-nonoelectronics crossbars. 27-32 - Tom J. Kazmierski, Dafeng Zhou, Bashir M. Al-Hashimi:
A fast, numerical circuit-level model of carbon nanotube transistor. 33-37 - Dennis Huo, Qiaoyan Yu, Paul Ampadu:
A ballistic nanoelectronic device simulator. 38-45 - Drew C. Ness, Christian J. Hescott, David J. Lilja:
Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations. 46-53 - Baris Taskin, Andy Chiu, Jonathan Salkind, Daniel Venutolo:
A shift-register-based QCA memory architecture. 54-61 - Hua Li
Thermally-induced soft errors in nanoscale CMOS circuits. 62-69 - Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi:
Robust self-assembly of interconnects by parallel DNA growth. 70-76 - Girish Venkatasubramanian, P. Oscar Boykin, Renato J. O. Figueiredo
Design of high-yield defect-tolerant self-assembled nanoscale memories. 77-84 - Susmit Biswas, Frederic T. Chong
A pageable, defect-tolerant nanoscale memory system. 85-92 - Zhengfei Wang, Huaixiu Zheng, Qinwei Shi, Jie Chen:
Emerging nanocircuit paradigm: Graphene-based electronics for nanoscale computing. 93-100 - Teng Wang, Pritish Narayanan, Csaba Andras Moritz:
Combining 2-level logic families in grid-based nanoscale fabrics. 101-108 - Dmitri B. Strukov
Prospects for the development of digital CMOL circuits. 109-116 - Tamer Mohamed, Graham A. Jullien, Wael M. Badawy
Crossbar latch-based combinational and sequential logic for nano FPGA. 117-122 - Shamik Das, Matthew F. Bauwens:
Clocking nanocircuits for nanocomputers and other nanoelectronic systems. 123-128
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