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GALA - an automatic layout system for high density CMOS gate arrays

Authors:

B. N. Tien,

B. S. Ting,

J. Cheam,

K. Chow,

S. C. EvansAuthors Info & Claims

DAC '84: Proceedings of the 21st Design Automation Conference

Pages 657 - 662

Published: 25 June 1984 Publication History

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Abstract

This paper describes the automatic layout software system - GALA (Gate Array Layout Automation) - developed at Hughes Aircraft Company for a high density CMOS gate array family with 3u design rules. The system layout and hierarchical decomposition schemes used in GALA are presented. The particular design environment and style are discussed. The system has been used in production for the various sizes of the Hughes HCMOS gate array family for over 2 years. Routing results for some designs produced during that period are presented.

References

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Jerry Lee, STC Computer Research, private communication.

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J. Munkres, "Algorithms for the Assignment and Transportation Problems", J. Siam 5, March 1957, pp. 32-38.

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A. Hashimoto, J. Stevens, "Wire Routing by Optimizing Channel Cell Within Large Aperatures", Proceedings of 8th Design Automation Workshop, 1971, pp. 155-169.

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J. Cheam, K. Chow, B. Tien, B. Ting, "Routing Techniques for Gate Array Layout", IEEE International Symposium on Circuits and Systems Proceedings, 1983, pp. 1009-1012.

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C. K. Cheng and E. S. Kuh, "Partitioning and Placement Based on Network Optimization", IEEE International Conference on Computer-Aided Design, 1983, pp. 86-87.

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B. S. Ting and B. N. Tien, "Routing Techniques for Gate Arrays", IEEE Transaction on Computer Aided Design, Oct. 1983, pp. 301-312.

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Cited By

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Hsu CTien BChow KPerry RTang JOfek HO'Neill L(1985)ALPS2Proceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317926(443-448)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317926
Spira PHage COfek HO'Neill L(1985)Hardware acceleration of gate array layoutProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317913(359-366)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317913

Index Terms

GALA - an automatic layout system for high density CMOS gate arrays
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
    2. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

DAC '84: Proceedings of the 21st Design Automation Conference

June 1984

715 pages

ISBN:0818605421

Publisher

IEEE Press

Publication History

Published: 25 June 1984

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DAC '84 Paper Acceptance Rate 116 of 290 submissions, 40%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Hsu CTien BChow KPerry RTang JOfek HO'Neill L(1985)ALPS2Proceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317926(443-448)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317926
Spira PHage COfek HO'Neill L(1985)Hardware acceleration of gate array layoutProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317913(359-366)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317913

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Recommendations

Quasi-damascene metal gate/high-k CMOS using oxygenation through gate electrodes

Breakdowns in high-k gate stacks of nano-scale CMOS devices

High-Performance High- K /Metal Planar Self-Aligned Gate-All-Around CMOS Devices