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research-article

Impact of process-variations in STTRAM and adaptive boosting for robustness

Authors:

Seyedhamidreza Motaman,

Nitin RathiAuthors Info & Claims

DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition

Pages 1431 - 1436

Published: 09 March 2015 Publication History

Abstract

Spin-Torque Transfer Random Access Memory (STTRAM) is a promising technology for high density on-chip cache due to low standby power. Additionally, it offers fast access time, good endurance and retention. However, it suffers from poor write latency and write power. Additionally we observe that process variation can result in large spread in write and read latency variations. The performance of conventionally designed STTRAM cache can degrade as much as 10% due to process variations. We propose a novel and adaptive write current boosting to address this issue. The bits experiencing worst-case write latency are fixed through write current boosting. Simulations show 80% power improvement compared to boosting all bit-cells and 13% performance improvement compared to worst case latency due to process variation over a wide range of PARSEC benchmarks.

References

[1]

Hosomi, M., et al. "A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM." Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International. IEEE, 2005.

[2]

Kryder, Mark H., and Chang Soo Kim. "After hard drives---What comes next?." Magnetics, IEEE Transactions on 45.10 (2009): 3406--3413.

[3]

Xuanyao, Fong, et al. "SPICE Models for Magnetic Tunnel Junctions Based on Monodomain Approximation," https://nanohub.org/resources/19048.

[4]

Gem5, http://www.gem5.org.

[5]

Parsec, http://parsec.cs.princeton.edu/index.htm.

[6]

McPAT, http://www.hpl.hp.com/research/mcpat

[7]

CACTI. http://www.hpl.hp.com/research/cacti/.

[8]

Zhou, Ping, et al. "Energy reduction for STT-RAM using early write termination." Computer-Aided Design-Digest of Technical Papers, 2009. ICCAD 2009. IEEE/ACM International Conference on. IEEE, 2009.

Digital Library

[9]

Smullen, Clinton W., et al. "Relaxing non-volatility for fast and energy-efficient STT-RAM caches." High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on. IEEE, 2011.

Digital Library

[10]

Sun, Hongbin, et al. "Design techniques to improve the device write margin for MRAM-based cache memory." Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI. ACM, 2011.

Digital Library

[11]

Bi, Xiuyuan, et al. "Probabilistic design methodology to improve run-time stability and performance of stt-ram caches." Proceedings of the International Conference on Computer-Aided Design. ACM, 2012.

Digital Library

[12]

Lee, Dongsoo, and Kaushik Roy. "Energy-Delay Optimization of STT MRAM Write Operation Under Process Variations." (2014): 1--1.

[13]

Rasquinha, Mitchelle, et al. "An energy efficient cache design using spin torque transfer (STT) RAM." Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design. ACM, 2010.

Digital Library

[14]

Sun, Zhenyu, et al. "Multi retention level STT-RAM cache designs with a dynamic refresh scheme." Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture. ACM, 2011.

Digital Library

[15]

Swaminathan, Karthik, et al. "When to forget: A system-level perspective on STT-RAMs." ASP-DAC. 2012.

[16]

Xu, Cong, et al. "Device-architecture co-optimization of STT-RAM based memory for low power embedded systems." Proceedings of the International Conference on Computer-Aided Design. IEEE Press, 2011.

Digital Library

[17]

Li, Jing, et al. "Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective." Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 18.12 (2010): 1710--1723.

Digital Library

[18]

Park, Sang Phill, et al. "Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture." Proceedings of the 49th Annual Design Automation Conference. ACM, 2012.

Digital Library

[19]

Kim, Yusung, et al. "Write-optimized reliable design of STT MRAM." Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design. ACM, 2012.

Digital Library

[20]

Lee, Dongsoo, Sumeet Kumar Gupta, and Kaushik Roy. "High-performance low-energy STT MRAM based on balanced write scheme." Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design. ACM, 2012.

Digital Library

[21]

Zhou, Ping, et al. "A durable and energy efficient main memory using phase change memory technology." ACM SIGARCH Computer Architecture News. Vol. 37. No. 3. ACM, 2009.

Digital Library

[22]

Qureshi, Moinuddin K., Michele M. Franceschini, and Luis Alfonso Lastras-Montaño. "Improving read performance of phase change memories via write cancellation and write pausing." High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on. IEEE, 2010.

[23]

Schechter, Stuart, et al. "Use ECP, not ECC, for hard failures in resistive memories." ACM SIGARCH Computer Architecture News. Vol. 38. No. 3. ACM, 2010.

Digital Library

[24]

Bushnell, Michael, and Vishwani D. Agrawal. Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Vol. 17. Springer, 2000.

Digital Library

[25]

Motaman, Seyedhamidreza, and Swaroop Ghosh. "Simultaneous Sizing, Reference Voltage and Clamp Voltage Biasing for Robustness, Self-Calibration and Testability of STTRAM Arrays." Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference. ACM, 2014.

Digital Library

[26]

Motaman, Seyedhamidreza, Anirudh Iyengar, and Swaroop Ghosh. "Synergistic circuit and system design for energy-efficient and robust domain wall caches." Proceedings of the 2014 international symposium on Low power electronics and design. ACM, 2014.

Digital Library

Cited By

Sayed NMao LBishnoi RTahoori M(2019)Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache DesignACM Transactions on Design Automation of Electronic Systems10.1145/332169324:4(1-25)Online publication date: 29-May-2019
https://dl.acm.org/doi/10.1145/3321693
George SLiao MJiang HKotra JKandemir MSampson JNarayanan VOskin MInoue K(2018)MDACacheProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00073(841-854)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00073
Nair SBishnoi RGolanbari MOboril FTahoori M(2017)VAET-STTProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130721(1460-1465)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130721
Show More Cited By

Index Terms

Impact of process-variations in STTRAM and adaptive boosting for robustness
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Semiconductor memory

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Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition

March 2015

1827 pages

ISBN:9783981537048

General Chair:
Wolfgang Nebel
OFFIS & University of Oldenburg, DE
,
Program Chair:
David Atienza
EPFL, CH

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
Russian Acadamy of Sciences: Russian Acadamy of Sciences
IEEE Council on Electronic Design Automation (CEDA)

Publisher

EDA Consortium

San Jose, CA, United States

Publication History

Published: 09 March 2015

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Research-article

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DATE '15

Sponsor:

EDAA
EDAC
SIGDA
Russian Acadamy of Sciences

DATE '15: Design, Automation and Test in Europe

March 9 - 13, 2015

Grenoble, France

Acceptance Rates

DATE '15 Paper Acceptance Rate 206 of 915 submissions, 23%;

Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Sayed NMao LBishnoi RTahoori M(2019)Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache DesignACM Transactions on Design Automation of Electronic Systems10.1145/332169324:4(1-25)Online publication date: 29-May-2019
https://dl.acm.org/doi/10.1145/3321693
George SLiao MJiang HKotra JKandemir MSampson JNarayanan VOskin MInoue K(2018)MDACacheProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00073(841-854)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00073
Nair SBishnoi RGolanbari MOboril FTahoori M(2017)VAET-STTProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130721(1460-1465)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130721
Bishnoi ROboril FTahoori M(2017)Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-FlopsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263031525:4(1421-1432)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2630315

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