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WO2024222560A1 - 稳压电路、低压差线性稳压器芯片、芯片系统及电子设备 - Google Patents

稳压电路、低压差线性稳压器芯片、芯片系统及电子设备 Download PDF

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Publication number
WO2024222560A1
WO2024222560A1 PCT/CN2024/088570 CN2024088570W WO2024222560A1 WO 2024222560 A1 WO2024222560 A1 WO 2024222560A1 CN 2024088570 W CN2024088570 W CN 2024088570W WO 2024222560 A1 WO2024222560 A1 WO 2024222560A1
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Prior art keywords
voltage
terminal
circuit
output
coupled
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PCT/CN2024/088570
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English (en)
French (fr)
Inventor
王毛冬
郭斐
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华为技术有限公司
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Publication of WO2024222560A1 publication Critical patent/WO2024222560A1/zh

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  • the present application relates to the field of electronic technology, and in particular to a voltage stabilizing circuit, a low voltage drop linear regulator chip, a chip system and an electronic device.
  • low dropout regulator As one of the core modules of power management system, low dropout regulator (LDO) is widely used in new memory and high-speed digital circuits due to its advantages of simple circuit structure, small size, low noise and few peripheral electronic devices.
  • LDO low dropout regulator
  • the transient amplitude of its output voltage will have a large overshoot or undershoot, resulting in voltage ripple (instability) in the output voltage.
  • the embodiments of the present application provide a voltage stabilizing circuit, a low voltage dropout linear regulator chip, a chip system and an electronic device for improving the problem of unstable output voltage.
  • a voltage stabilizing circuit comprising a voltage input terminal, a voltage output terminal, a first voltage terminal and a second voltage terminal, and further comprising a low voltage dropout linear regulator, a first comparator, a first delay circuit and a plurality of first switch circuits, wherein the low voltage dropout linear regulator serves as a low voltage dropout linear regulator main module (or body module) in the voltage stabilizing circuit, and the first comparator, the first delay circuit and the plurality of first switch circuits can serve as a transient response enhancement module in the voltage stabilizing circuit.
  • the low voltage dropout linear regulator is configured to receive a reference voltage at the voltage input terminal and output a first voltage.
  • the voltage output terminal is configured to receive a first voltage and output a second voltage.
  • the first comparator is configured to receive a first threshold voltage and a second voltage at the first voltage terminal and output a first comparison result.
  • the first delay circuit is configured to receive a first comparison result and output a plurality of first control signals.
  • the plurality of first switch circuits are arranged in parallel, and each first switch circuit is configured to receive a first control signal and regulate the on-off between the second voltage terminal and the voltage output terminal.
  • a voltage stabilizing circuit structure of a digital-analog hybrid architecture is adopted, and a first comparator is set in the voltage stabilizing circuit, which can quickly respond to the change of the second voltage outputted from the voltage output terminal.
  • the conduction of multiple first switch circuits is controlled step by step through the first delay circuit to form a compensation path from the second voltage terminal to the voltage output terminal, so as to compensate for the substantial change of the second voltage (output voltage of the voltage stabilizing circuit) caused by the instantaneous change of the load current, and keep the second voltage within the threshold range to improve the stability of the output voltage of the voltage stabilizing circuit.
  • the current value injected (or discharged) into the voltage output terminal can be adjusted by multiple first switch circuits, the current value injected (or discharged) from the second voltage terminal to the voltage input terminal can be determined according to the actual application scenario, and the load current change range that can be coped with is relatively large.
  • the conduction of some first switch circuits can compensate the second voltage to the threshold range, so the remaining first switch circuits do not need to be turned on again, which is conducive to reducing dynamic power consumption.
  • the circuit structures included in the voltage stabilizing circuit can all be on-chip integrated structures, which can reduce the area of the voltage stabilizing circuit and remove the additional cost caused by introducing off-chip capacitors.
  • the second voltage terminal is the power supply voltage terminal
  • the charging path where the first switch circuit is located will draw a large current from the second voltage terminal, due to the presence of the parasitic inductance of the bonding line of the second voltage terminal pad, the current drawn from the second voltage terminal will cause the power supply voltage of the second voltage terminal to generate noise fluctuations, affecting the normal operation of other modules.
  • the amount of current drawn from the second voltage terminal each time can be reduced. The smaller the current drawn each time, the smaller the amplitude of the noise fluctuation generated by the power supply voltage, so the problem of large power supply voltage fluctuations can be improved.
  • the voltage stabilization circuit further includes a first current source circuit; the first current source circuit is coupled between the second voltage terminal and the plurality of first switch circuits.
  • the first current source circuit By arranging a first current source circuit between the second voltage terminal and the first switch circuit, the first current source circuit can provide accurate
  • the fixed charging current value is used to improve the compensation accuracy of the second voltage and improve the problem of large charging and discharging current variation within a wide power supply voltage range.
  • the voltage stabilization circuit further includes a first reverse coupling circuit; the first reverse coupling circuit is coupled between the first delay circuit and the first current source circuit.
  • the static operating point of the first current source circuit can be stabilized, the charging and discharging current fluctuation of the first current source circuit can be compensated, the influence of coupling noise on the accuracy of the charging current value can be reduced, and the current of the first current source circuit can be more accurately copied to the voltage output terminal to maintain the stability of the charging current value.
  • the influence of noise on the power supply voltage can also be reduced.
  • the first delay circuit includes a plurality of first delay modules connected in series, a first comparison result input terminal, and a plurality of first control signal output terminals; the input terminal and the output terminal of each first delay module are configured with a first control signal output terminal; the first delay circuit is configured to receive the first comparison result from the first comparison result input terminal, and output the first control signal from the first control signal output terminal.
  • the first delay circuit includes a plurality of first delay modules, and the plurality of first delay modules are used to control the plurality of first switch circuits to be turned on in sequence, and the paths where the plurality of first switch circuits are located obtain current from the second voltage terminal in stages, which can effectively reduce the voltage fluctuation of the second voltage terminal.
  • the hierarchical conduction of the first switch circuits is conducive to reducing dynamic power consumption.
  • the first delay circuit further includes a plurality of OR gates; the OR gates are configured to receive signals from the input and output ends of the first delay module, and output OR-operated signals to the first control signal output end.
  • the first comparison result output by the first comparator will control all the first switch circuits to be directly closed, thereby improving the over-compensation of the second voltage caused by the delayed closing of the subsequent first switch circuit.
  • the first delay circuit further includes a plurality of AND gates; the AND gates are configured to receive signals from the input and output ends of the first delay module, and output signals after AND operation to the first control signal output end.
  • the first comparison result outputted by the first comparator will control all the first switch circuits to be directly closed, thereby improving the over-compensation of the second voltage caused by the delayed closing of the subsequent first switch circuit.
  • the first comparator includes a plurality of cascaded first operational amplifiers.
  • the gain of the first comparator can be greatly increased.
  • the first comparator further includes a multi-stage first inverter coupled to output terminals of the multi-stage first operational amplifier.
  • the driving capability of the first switch circuit can be improved, thereby increasing the variation range (swing) of the voltage outputted by the voltage output terminal, and realizing a high-gain and high-speed first comparator.
  • the high-gain and high-speed first comparator can increase the processing speed of the first comparator, thereby increasing the response speed of the charging module, shortening the recovery time of the second voltage outputted by the voltage output terminal, and improving the transient response characteristics of the voltage stabilization circuit.
  • the first switch circuit includes a first transistor; a control electrode of the first transistor is coupled to the first delay circuit, a first electrode of the first transistor is coupled to the second voltage terminal, and a second electrode of the first transistor is coupled to the voltage output terminal.
  • the first transistor is a P-type transistor
  • the second voltage terminal is a power supply voltage terminal.
  • the voltage stabilizing circuit can adjust the undershoot of the voltage output by the voltage output terminal.
  • the first transistor is an N-type transistor
  • the second voltage terminal is a reference ground voltage terminal.
  • the voltage stabilization circuit can adjust the overshoot of the voltage output by the voltage output terminal.
  • the first current source circuit includes a current mirror.
  • the charging current value is relatively stable and can be applied to medium and high frequency (hundreds of megahertz level) chips (such as MCU chips) with a wide power supply voltage range.
  • the first current source circuit includes a second transistor, a first current source, and multiple third transistors; the control electrode of the second transistor is coupled to the control electrodes of the multiple third transistors and the second electrode of the second transistor, the first electrode of the second transistor is coupled to the second voltage terminal, and the second electrode of the second transistor is coupled to the first current source; the first current source is also coupled to the third voltage terminal; the first electrode of each third transistor is coupled to the second voltage terminal, and the second electrode of each third transistor is coupled to a first switching circuit.
  • This is a current mirror structure with a simple structure.
  • the second voltage terminal and the third voltage terminal are a power supply voltage terminal and a reference ground voltage terminal, respectively.
  • the voltage stabilizing circuit can adjust the overshoot or undershoot of the voltage output by the voltage output terminal.
  • the first reverse coupling circuit includes a second inverter and a first capacitor; the second inverter and the first capacitor are coupled in series between the first control signal output terminal and the control electrode of the third transistor. This is a first reverse coupling circuit with a simple structure.
  • the voltage stabilizing circuit further includes a second comparator, a second delay circuit, a plurality of second switch circuits connected in parallel, a fourth voltage terminal, and a fifth voltage terminal.
  • the second comparator is configured to receive a second threshold voltage and a second voltage of the fourth voltage terminal, and output a second comparison result.
  • the second delay circuit is configured to receive the second comparison result, and output a plurality of second control signals.
  • Each second switch circuit is configured to receive a second control signal, and regulate the on-off between the fifth voltage terminal and the voltage output terminal. In this way, the voltage stabilizing circuit can have the ability to adjust the overshoot and undershoot of the voltage outputted by the voltage output terminal.
  • the voltage stabilization circuit further includes a second current source circuit; the second current source circuit is coupled between the fifth voltage terminal and the plurality of second switch circuits.
  • the second current source circuit can provide an accurate and fixed charging current value to improve the compensation accuracy of the second voltage, thereby improving the problem of large charging and discharging current variation within a wide power supply voltage range.
  • the voltage stabilization circuit further includes a second reverse coupling circuit; the second reverse coupling circuit is coupled between the second delay circuit and the second current source circuit.
  • the static operating point of the second current source circuit can be stabilized, the charging and discharging current fluctuation of the second current source circuit can be compensated, the influence of coupling noise on the accuracy of the charging current value can be reduced, and the current of the second current source circuit can be more accurately copied to the voltage output end to maintain the stability of the charging current value.
  • the influence of noise on the power supply voltage can also be reduced.
  • a low voltage difference linear regulator chip comprising a substrate and a voltage stabilizing circuit according to any one of the first aspects, wherein the voltage stabilizing circuit is arranged on the substrate.
  • a chip system comprising the voltage stabilizing circuit of any one of the first aspect or the low voltage difference linear regulator chip of the second aspect and a load circuit; the voltage output end of the voltage stabilizing circuit is coupled to the load circuit.
  • a fourth aspect of an embodiment of the present application provides an electronic device, comprising the voltage stabilizing circuit of any one of the first aspect or the low voltage difference linear regulator chip of the second aspect or the chip system and circuit board of the third aspect, wherein the voltage stabilizing circuit is arranged on the circuit board.
  • a driving method of a voltage stabilizing circuit comprising: a reference voltage is inputted into a voltage input terminal, a low voltage difference linear regulator receives the reference voltage, and outputs a first voltage; a voltage output terminal receives the first voltage and outputs a second voltage; a first voltage terminal inputs a first threshold voltage, a first comparator receives the second voltage and the first threshold voltage, and outputs a first comparison result; a first delay circuit receives the first comparison result, and outputs a plurality of first control signals; a plurality of first switch circuits respectively receive the first control signal, and regulate the on-off between the second voltage terminal and the voltage output terminal;
  • FIG1 is a schematic diagram of the architecture of an MCU provided in an embodiment of the present application.
  • 2A-2C are topological diagrams of a voltage stabilization circuit provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of the architecture of a voltage stabilizing circuit provided in an embodiment of the present application.
  • FIG4 is a topological diagram of a voltage stabilization circuit provided in an embodiment of the present application.
  • 5A and 5B are schematic diagrams of the structure of a first comparator provided in an embodiment of the present application.
  • 6A and 6B are schematic diagrams of the structure of a first delay circuit provided in an embodiment of the present application.
  • FIG7 is a detailed structural diagram of a voltage stabilization circuit provided in an embodiment of the present application.
  • FIG8 is a diagram showing the transient response of a voltage stabilizing circuit to an undershoot provided by an embodiment of the present application.
  • FIG9 is a topological diagram of a voltage stabilization circuit provided in an embodiment of the present application.
  • FIG10 is a schematic diagram of the structure of a second delay circuit provided in an embodiment of the present application.
  • FIG11 is a schematic diagram of the structure of a voltage stabilizing circuit provided in an embodiment of the present application.
  • FIG. 12 is a topological diagram of a voltage stabilization circuit provided in an embodiment of the present application.
  • directional terms such as “up”, “down”, “left” and “right” may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.
  • connection should be understood in a broad sense.
  • connection can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • coupled can be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • contact can be a direct contact or an indirect contact through an intermediate medium.
  • a and/or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural.
  • the character “/” generally indicates that the associated objects are in an "or” relationship.
  • the transistor involved in the embodiment of the present application may be a metal oxide semiconductor (MOS) field effect transistor (hereinafter referred to as MOS tube).
  • MOS metal oxide semiconductor
  • the control terminal of the transistor in the embodiment of the present application may refer to the gate of the transistor; in one possible embodiment, the first electrode of the transistor may refer to the source electrode, and the second electrode may refer to the drain electrode; in another possible embodiment, the first electrode of the transistor may refer to the drain electrode, and the second electrode may refer to the source electrode.
  • the present application provides an electronic device, which is, for example, a consumer electronic product, a home electronic product, a financial terminal product, a communication electronic product, a medical instrument electronic product, an automotive electronic product, etc.
  • consumer electronic products are such as mobile phones, tablet computers (pad), laptop computers, e-readers, personal computers (PC), personal digital assistants (PDA), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc.
  • Home electronic products are such as smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (e.g., soybean milk machines, sweeping robots), etc.
  • Financial terminal products are such as automated teller machines (ATMs), self-service terminals, etc.
  • Communication electronic products are such as servers, non-volatile memories, radars, base stations, and other communication electronic devices.
  • Medical instrument electronic products are such as various testing instruments, oxygen generators, etc. The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned electronic device.
  • a microcontroller also known as a microcontroller unit, MCU
  • MCU microprocessor chip designed for control processing of specific applications. It can integrate a central processing unit (CPU), memory (including volatile memory and non-volatile memory), and multiple input/output (I/O) interfaces on a single chip to form a chip-level computer. MCU is widely used in industrial control, smart electronic devices, home appliances, medical instruments, automotive electronics and other fields.
  • the electronic device provided in the embodiment of the present application may include, for example, an MCU, and the MCU may be arranged on a circuit board of the electronic device.
  • FIG1 is a schematic diagram of the architecture of an MCU provided in an embodiment of the present application.
  • an MCU is illustrated, and the MCU includes a CPU, a memory, and a voltage stabilizing circuit 10.
  • the CPU and the memory are used to provide processing and storage functions for electronic devices, and the two can be integrated in the MCU.
  • the voltage stabilizing circuit 10 is used to provide the MCU with the power supply voltage required for operation.
  • the voltage regulator circuit 10 has become the mainstream choice for MCU power supply modules due to its advantages such as simple circuit structure, small size, low noise, and few peripheral electronic devices.
  • the operating current of the MCU can reach up to tens of mA, and the operating current will change rapidly due to changes in application scenarios.
  • 2A-2C are topological diagrams of a voltage stabilization circuit provided in an embodiment of the present application.
  • the voltage stabilizing circuit 10 includes a low dropout regulator (LDO).
  • LDO low dropout regulator
  • the LDO may include an error amplifier (EA), a transistor M0, and a feedback circuit.
  • the feedback circuit includes a first resistor R1 and a second resistor R2.
  • the transistor M0 is a P-type metal field effect transistor (positive channel metal oxide semiconductor, PMOS)
  • the output end of the error amplifier EA is coupled to the control end of the transistor M0 (i.e., the gate of the PMOS).
  • the first pole of the transistor M0 e.g., the drain of the PMOS
  • the second pole of the transistor M0 e.g., the source of the PMOS
  • the output end of the feedback circuit is coupled to the negative phase input end of the error amplifier EA, and the positive phase input end of the error amplifier EA is used to receive the reference voltage Vref.
  • the received reference voltage Vref can be generated, for example, by a bandgap reference (BG) circuit.
  • the voltage output end VOT provides a fixed voltage value for the subsequent load that is independent of the power supply voltage Vdd of the power supply voltage end VDD.
  • the second voltage v2 output by the voltage output terminal VOT of the LDO will have an overshoot or undershoot phenomenon.
  • the feedback circuit samples the second voltage v2 through the first resistor R1 and the second resistor R2, and transmits the sampled feedback voltage Vfb to the negative input terminal of the error amplifier EA.
  • the error amplifier EA compares and amplifies the feedback voltage Vfb and the reference voltage Vref received at the positive input terminal, and the amplified voltage is used as the gate voltage Vg of the transistor M0.
  • the gate voltage Vg dynamically adjusts the second voltage v2 by changing the on-current Ip flowing through the transistor M0 to achieve the regulated output of the LDO.
  • the feedback voltage Vfb decreases, and the decrease in the feedback voltage Vfb causes the gate voltage Vg to decrease.
  • the on-current Ip increases, thereby increasing the second voltage v2.
  • the feedback voltage Vfb increases, and the increase in the feedback voltage Vfb causes the gate voltage Vg to increase.
  • the on-current Ip decreases, thereby reducing the second voltage v2.
  • the voltage stabilizing circuit 10 includes, in addition to the LDO, an off-chip capacitor C and an equivalent parasitic resistor Resr introduced by the off-chip capacitor C.
  • the equivalent parasitic resistor Resr introduces a zero point into the voltage stabilizing circuit 10, which can offset the influence of the secondary pole and meet the stability requirement.
  • the off-chip capacitor type voltage stabilizing circuit 10 mainly relies on the charging and discharging of the off-chip capacitor C to maintain the stability of the second voltage v2, avoiding excessive undershoot and overshoot of the second voltage v2.
  • the transistor M0 cannot immediately provide enough current, and the remaining current is provided by the off-chip capacitor C in a short time.
  • the following formula is the definition of the undershoot value of the second voltage v2, where ⁇ I OUT is the change value of the load current, t1 is the undershoot time, the size of which depends on the closed-loop bandwidth and slew rate of the LDO, and ⁇ V ESR is the voltage difference across the equivalent parasitic resistance Resr. It can be seen from the following formula (1) that within the same time, the larger the off-chip capacitor C is, the smaller the undershoot value of the second voltage v2 is.
  • the off-chip capacitor type voltage regulator circuit 10 it is easier to ensure system stability by selecting an output capacitor with a larger equivalent parasitic resistance Resr, so expensive tantalum capacitors have to be selected, which increases the cost of the design.
  • the capacitance of the off-chip capacitor C usually needs to be at the uF level, and a special pin needs to be reserved during the design to connect the off-chip capacitor C.
  • the parasitic inductance and antenna effect on the connection line (such as a bonding line) between the LDO and the off-chip capacitor C will reduce the quality of the second voltage v2 of the voltage regulator circuit 10.
  • the voltage stabilizing circuit 10 includes not only the LDO but also an on-chip integrated regulating circuit, and the structure of the regulating circuit is shown in FIG. 2C .
  • the feedback voltage Vfb changes synchronously.
  • the adjustment circuit senses the change of the feedback voltage Vfb and directly compensates the detected overshoot or undershoot through the adjustment circuit.
  • the adjustment circuit charges and discharges the voltage outputted from the voltage output terminal VOT to reduce the overshoot and undershoot.
  • the voltage stabilizing circuit 10 of this solution has a simple structure, but the charging and discharging current is directly drawn through the transistor T1 and the transistor T2, which will cause a large noise impact on the power supply voltage.
  • the load current adjustment capability is limited, and it is not suitable for a wide power supply voltage range.
  • an embodiment of the present application further provides a voltage stabilizing circuit 10, which improves the instability of the output voltage of the voltage stabilizing circuit 10 while reducing the noise impact on the power supply voltage.
  • the voltage stabilizing circuit 10 provided in the embodiment of the present application is schematically illustrated below with several examples.
  • FIG3 is a schematic diagram of the architecture of a voltage stabilizing circuit provided in an embodiment of the present application
  • FIG4 is a schematic diagram of the topology of a voltage stabilizing circuit provided in an embodiment of the present application.
  • an embodiment of the present application provides a voltage stabilizing circuit 10 , which can be integrated into a chip (a bare chip or a packaged chip).
  • the voltage stabilizing circuit 10 includes a voltage input terminal VI, a voltage output terminal VOT, a first voltage terminal V1 and a second voltage terminal V2.
  • the voltage input terminal VI is used, for example, to receive a reference voltage Vref, which is provided, for example, by a bandgap reference (BG) circuit.
  • the voltage output terminal VOT is used to output a stable second voltage v2 to the load.
  • the first voltage terminal V1 is used, for example, to receive a first threshold voltage, which is used as a comparison voltage to determine whether an undershoot occurs in the voltage stabilization circuit 10.
  • the second voltage terminal V2 can be, for example, a power supply voltage terminal VDD, which is used to receive a power supply voltage Vdd.
  • the voltage stabilizing circuit 10 further includes a low dropout linear regulator LDO and a charging module.
  • the charging module includes a first comparator 11 , a first delay circuit 12 and a plurality of first switch circuits 13 .
  • the low dropout linear regulator LDO is configured to receive a reference voltage Vref at a voltage input terminal VI and output a first voltage v1.
  • the low dropout linear regulator LDO includes an error amplifier EA, a transistor M0 and a feedback circuit.
  • the feedback circuit includes a first resistor R1 and a second resistor R2.
  • a first input terminal of the error amplifier EA is coupled to the voltage input terminal VI, a second input terminal of the error amplifier EA is coupled between the first resistor R1 and the second resistor R2, and an output terminal of the error amplifier EA is coupled to the control electrode of the transistor M0.
  • a first electrode of the transistor M0 is coupled to the first end of the first resistor R1 , and a second electrode of the transistor M0 is coupled to the second voltage end.
  • a first end of the second resistor R2 is coupled to the first end of the first resistor R1 , and a second end of the second resistor R2 is coupled to the reference ground voltage terminal GND.
  • the output end of the low-dropout linear regulator LDO is coupled between the first electrode of the transistor M0 and the first end of the first resistor R1 , and the output end of the low-dropout linear regulator LDO is used to output a first voltage v1 .
  • the embodiment of the present application does not limit the structure of the low-dropout linear regulator LDO.
  • the low-dropout linear regulator LDO in the related art is applicable to the embodiment of the present application.
  • the structure of the low-dropout linear regulator LDO shown in FIG. 4 is only a schematic diagram.
  • the voltage output terminal VOT is configured to receive a first voltage v1 output by the low dropout linear regulator LDO, and output a second voltage v2.
  • the second voltage v2 is equal to the first voltage v1.
  • the second voltage v2 is a stable voltage after the first voltage v1 is injected with compensation.
  • the first comparator 11 is configured to receive the first threshold voltage V1 and the second voltage v2 of the first voltage terminal V1, and output a first comparison result Vcp after comparing the first threshold voltage V1 and the second voltage v2.
  • the first input terminal of the first comparator 11 is coupled to the first voltage terminal V1, and the first input terminal of the first comparator 11 is used to receive the first threshold voltage V1.
  • the second input terminal of the first comparator 11 is coupled to the output terminal of the low-dropout linear regulator LDO, and the second input terminal of the first comparator 11 is used to receive the second voltage v2.
  • the output terminal of the first comparator 11 is coupled to the first delay circuit 12, and the output terminal of the first comparator 11 is used to output the first comparison result to the first delay circuit 12.
  • the first comparator 11 is used to detect the change of the second voltage v2, and takes the first threshold voltage V1 as the minimum reference voltage within the acceptable range.
  • the first threshold voltage V1 When the second voltage v2 is less than the first threshold voltage V1, it is determined that the second voltage v2 has an undershoot, and the first comparison result Vcp is used to indicate that the second voltage v2 has an undershoot.
  • the second voltage v2 is greater than the first threshold voltage V1
  • the first comparison result Vcp is used to indicate that the second voltage v2 has not an undershoot.
  • the first comparator 11 is a P-type comparator, and when the second voltage v2 undershoots, the first comparison result Vcp is “0”. When the second voltage v2 does not undershoot, the first comparison result Vcp is “1”.
  • the embodiment of the present application does not limit the type of the first comparator 11, nor does it limit the type of the first comparison result Vcp.
  • the first comparison result Vcp output by the first comparator 11 can control the first switch circuit 13 to turn on.
  • the first comparator 11 is only a P-type comparator.
  • the first comparison result Vcp is "0".
  • the first comparison result Vcp is "1" as an example for illustration.
  • the embodiment of the present application does not limit the value of the first threshold voltage V1.
  • the embodiment of the present application does not limit the structure of the first comparator 11 , and all comparators in the related art are applicable to the embodiment of the present application.
  • the first comparator 11 is a high-speed comparator.
  • the first comparator 11 is a comparator with an output delay of nanoseconds.
  • 5A and 5B are schematic diagrams of the structure of a first comparator 11 provided in an embodiment of the present application.
  • the first comparator 11 includes a plurality of cascaded first operational amplifiers OP1 .
  • FIG. 5A takes the example that the first comparator 11 includes three cascaded first operational amplifiers OP1 as an example.
  • the input terminal of the first-stage first operational amplifier OP1 is used as the input terminal of the first comparator 11.
  • the first input terminal of the first-stage first operational amplifier OP1 is coupled to the first voltage terminal V1
  • the second input terminal of the first-stage first operational amplifier OP1 is coupled to the output terminal of the low-dropout linear regulator LDO.
  • the second-stage first operational amplifier OP1 is cascaded with the first-stage first operational amplifier OP1
  • the third-stage first operational amplifier OP1 is cascaded with the second-stage first operational amplifier OP1.
  • the output terminal of the third-stage first operational amplifier OP1 is used as the output terminal of the first comparator 11.
  • the gain of the first comparator 11 can be greatly increased.
  • the first comparator 11 in the embodiment of the present application may also include only one stage of first operational amplifier.
  • the first comparator 11 further includes a multi-stage first inverter INV1 coupled to the output terminal of the multi-stage first operational amplifier OP1 .
  • FIG5B takes the example that the first comparator 11 includes two-stage first inverters INV1 as an example.
  • the input end of the first-stage first inverter INV1 is coupled to the output end of the last-stage first operational amplifier OP1
  • the input end of the second-stage first inverter INV1 is coupled to the input end of the first-stage first inverter INV1
  • the output end of the second-stage first inverter INV1 serves as the output end of the first comparator 11.
  • the driving capability of the first switch circuit 13 can be improved, thereby increasing the variation range (swing) of the voltage outputted by the voltage output terminal VOT, and realizing a high-gain and high-speed first comparator 11.
  • the high-gain and high-speed first comparator 11 can increase the processing speed of the first comparator 11, thereby increasing the response speed of the charging module, shortening the recovery time of the second voltage v2 outputted by the voltage output terminal VOT, and improving the transient response characteristics of the voltage stabilizing circuit 10.
  • the first comparator 11 in the embodiment of the present application may also include only one stage of the first inverter INV1.
  • the first comparator 11 is, for example, a P-type comparator.
  • the first delay circuit 12 is configured to receive the first comparison result Vcp and output a plurality of first control signals Vc ⁇ 1:n>.
  • the first delay circuit 12 includes a first comparison result input terminal and a plurality of first control signal output terminals.
  • the first comparison result input terminal of the first delay circuit 12 is coupled to the output terminal of the first comparator 11, and the first control signal output terminal of the first delay circuit 12 is used to receive the first comparison result Vcp.
  • the plurality of first control signal output terminals of the first delay circuit 12 are coupled to the plurality of first switch circuits 13 correspondingly, for example, one first control signal output terminal of the first delay circuit 12 is coupled to the input terminal of one first switch circuit 13.
  • the first delay circuit 12 is configured to receive the first comparison result through the first comparison result input terminal and output the first control signal through the first control signal output terminal.
  • the multiple first control signal output terminals of the first delay circuit 12 are used to output the delayed signal after delaying the first comparison result Vcp.
  • the first control signals output by the multiple first control signal output terminals of the first delay circuit 12 are delayed relative to the first comparison result Vcp. Then, each first switch circuit 13 receives the delayed signal after the delay.
  • one first control signal output terminal is used to output a non-delayed signal (that is, directly output the first comparison result Vcp), and the other first control signal output terminals are used to output a delayed signal after delaying the first comparison result Vcp.
  • one first switch circuit 13 directly receives the first comparison result Vcp), and the other first switch circuits 13 all receive the delayed signal after the delay.
  • the other first switch circuits 13 receive the delayed signal in sequence, or it can be understood that the delay degrees of the delayed signals received by the other first switch circuits 13 are different, so that the other first switch circuits 13 are turned on in sequence.
  • 6A and 6B are schematic diagrams of the structure of a first delay circuit 12 provided in an embodiment of the present application.
  • the first delay circuit 12 includes a plurality of first delay modules 121 connected in series, a first comparison result input terminal VCP, and a plurality of first control signal output terminals (eg, VC1 , VC2 , VC3 ).
  • the structures (delay degrees) of the multiple first delay modules 121 may be the same, or the structures (delay degrees) of the multiple first delay modules 121 may be different.
  • each first delay module 121 is configured with a first control signal output end. In this way, the first control signal output by each first control signal output end is a delayed signal after delaying the first comparison result Vcp.
  • the output ends of some first delay modules 121 are configured with the first control signal output end, and the output ends of some first delay modules 121 are not configured with the first control signal output end.
  • each first delay module 121 are both configured with a first control signal output end.
  • a first control signal output terminal is provided between two adjacent first delay modules 121.
  • the first control signal output terminal between the two adjacent first delay modules 121 serves as a first control signal output terminal configured corresponding to the output terminal of the previous first delay module 121, and also serves as a first control signal output terminal configured corresponding to the input terminal of the next first delay module 121.
  • two first control signal output terminals are provided between two adjacent first delay modules 121, one first control signal terminal is used as a first control signal output terminal configured corresponding to the output terminal of the first delay module 121 of the previous stage, and the other first control signal output terminal is used as a first control signal output terminal configured corresponding to the input terminal of the first delay module 121 of the next stage.
  • the delay degrees of the first control signals output by the two first control signal output terminals relative to the first comparison result Vcp are the same.
  • first delay circuit 12 takes the first delay circuit 12 including three first control signal output terminals as an example for illustration, wherein the three first control signal output terminals are respectively a first-stage first control signal output terminal VC1, a second-stage first control signal output terminal VC2 and a third-stage first control signal output terminal VC3.
  • each first delay module 121 the delay degree of each first delay module 121 is 5nS, then the first control signal Vc1 output by the first-stage first control signal output terminal VC1 is not delayed relative to the first comparison result Vcp, the first control signal Vc2 output by the second-stage first control signal output terminal VC1 is delayed by 5nS relative to the first comparison result Vcp, and the first control signal Vc3 output by the third-stage first control signal output terminal VC3 is delayed by 10nS relative to the first comparison result Vcp and delayed by 5nS relative to the first control signal Vc2.
  • the input and output ends of some first delay modules 121 are both configured with the first control signal output end, and the input and/or output ends of some first delay modules 121 are not configured with the first control signal output end.
  • the first delay circuit 12 includes a plurality of first delay modules 121, and the plurality of first delay modules 121 are used to control the plurality of first switch circuits 13 to be turned on in sequence, and the paths where the plurality of first switch circuits 13 are located obtain current from the second voltage terminal V2 in batches, which can effectively reduce the voltage fluctuation of the second voltage terminal V2.
  • the hierarchical conduction of the first switch circuits 13 is conducive to reducing dynamic power consumption.
  • the first delay circuit 12 further includes a plurality of OR gates.
  • the OR gate is configured to receive signals from the input and output ends of the first delay module 121 and output the OR-operated signal to the first control signal output end.
  • the OR gate is coupled between the first delay module 121 and the first control signal output terminal.
  • the OR gate includes a first input terminal, a second input terminal, and an output terminal, the first input terminal of the OR gate is coupled to the input terminal of the first delay module 121, the second input terminal of the OR gate is coupled to the output terminal of the first delay module 121, and the output terminal of the OR gate is coupled to the first control signal output terminal.
  • the first input terminal of the first-stage OR gate is coupled to the input terminal of the first-stage first delay module 121 (that is, the first-stage first control signal output terminal VC1)
  • the second input terminal of the first-stage OR gate is coupled to the output terminal of the first-stage first delay module 121
  • the output terminal of the first-stage OR gate is coupled to the second-stage first control signal output terminal VC2.
  • the first input terminal of the second-stage OR gate is coupled to the input terminal of the second-stage first delay module 121 (that is, the second-stage first control signal output terminal VC2), the second input terminal of the second-stage OR gate is coupled to the output terminal of the second-stage first delay module 121, and the output terminal of the second-stage OR gate is coupled to the third-stage first control signal output terminal VC3.
  • the first comparison result Vcp output by the first comparator 11 is "0"
  • the first comparison result Vcp is still "0” after the delay after the first delay module 121, and after the OR gate operation
  • the output is still "0”
  • the multiple first switch circuits 13 are turned on in sequence under the control of the first control signal output by the multi-stage first control signal output terminal.
  • an OR gate is set in the first delay circuit 12.
  • the first comparison result Vcp output by the first comparator 11 will control all the first switch circuits 13 to be directly turned off, thereby improving the over-compensation of the second voltage v2 caused by the delayed closing of the subsequent first switch circuit 13.
  • FIG6B illustrates an example in which the output end of each first delay module 121 is coupled to an OR gate. It is also possible that the output ends of some first delay modules 121 are coupled to an OR gate, while the output ends of some first delay modules 121 are not coupled to an OR gate.
  • each first switch circuit 13 is configured to receive the first control signal Vc and regulate the on-off between the second voltage terminal V2 and the voltage output terminal VOT.
  • the first delay circuit 12 outputs n first control signals Vc ⁇ 1:n>.
  • the first first switch circuit 13 receives the first control signal Vc1 output by the first-stage control signal output terminal VC1
  • the second first switch circuit 13 receives the first control signal Vc2 output by the second-stage first control signal output terminal VC2
  • the third first switch circuit 13 receives the first control signal Vc3 output by the third-stage first control signal output terminal VC3, and so on.
  • the first switch circuit 13 includes a first transistor M1 , and the plurality of first switch circuits 13 are a plurality of first transistors M1 ⁇ 1:n>.
  • each first transistor M1 is coupled to the first control signal output terminal of the first delay circuit 12 , the first electrode of the first transistor M1 is coupled to the second voltage terminal V2 , and the second electrode of the first transistor M1 is coupled to the voltage output terminal VOT.
  • the first comparator 11 is a P-type comparator
  • the corresponding first transistor M1 is a P-type transistor, which is turned on under the control of a low-level signal.
  • the second voltage terminal V2 is the power supply voltage terminal VDD.
  • the first switch circuit 13 forms an injection path to perform injection compensation on the second voltage v2 so that the second voltage v2 output by the voltage output terminal VOT is stable within the threshold range.
  • a voltage stabilizing circuit 10 structure with a digital-analog hybrid architecture is adopted, and a first comparator 11 is set in the voltage stabilizing circuit 10, which can quickly respond to the change of the second voltage v2 output by the voltage output terminal VOT.
  • the conduction of multiple first switch circuits 13 is controlled step by step through the first delay circuit 12 to form a compensation path from the second voltage terminal V2 to the voltage output terminal VOT, so as to compensate for the substantial change of the second voltage v2 (the output voltage of the voltage stabilizing circuit 10) caused by the instantaneous change of the load current, and keep the second voltage v2 within the threshold range.
  • the current value injected into the voltage output terminal VOT can be adjusted by multiple first switch circuits 13, the current value injected from the second voltage terminal V2 to the voltage input terminal VOT can be determined according to the actual application scenario, and the load current change range that can be coped with is relatively large. Furthermore, since the charging path where the first switch circuit 13 is located will draw a large current from the second voltage terminal V2, due to the presence of the parasitic inductance of the bonding line of the second voltage terminal V2 pad, the current drawn from the second voltage terminal V2 will cause the power supply voltage of the second voltage terminal V2 to generate noise fluctuations, affecting the normal operation of other modules.
  • the number of times of drawing can be increased through multi-stage control logic, and the amount of current drawn from the second voltage terminal V2 can be reduced each time.
  • the smaller the current drawn each time the smaller the amplitude of the noise fluctuation generated by the power supply voltage, so the problem of large power supply voltage fluctuation can be improved.
  • the second voltage v2 can be compensated to the threshold range by turning on some of the first switch circuits 13, then the remaining first switch circuits 13 do not need to be turned on again, which is conducive to reducing dynamic power consumption.
  • the circuit structure included in the voltage stabilizing circuit 10 can all be an on-chip integrated structure, which can reduce the area of the voltage stabilizing circuit 10 and remove the additional cost caused by introducing off-chip capacitors.
  • the voltage stabilizing circuit 10 further includes a first current source circuit 14 .
  • the first current source circuit 14 is coupled between the second voltage terminal V2 and the plurality of first switch circuits 13 .
  • the first switch circuit 13 directly draws current from the second voltage terminal V2, and the current fluctuation will be relatively large.
  • the first current source circuit 14 can provide an accurate and fixed charging current value to improve the compensation accuracy of the second voltage v2, and improve the problem of large charging and discharging current variation in a wide power supply voltage range.
  • the first current source circuit 14 includes a current mirror.
  • the charging current value is relatively stable and can be applied to medium and high frequency (hundreds of megahertz level) chips (such as MCU chips) with a wide power supply voltage range.
  • the first current source circuit 14 includes a second transistor M2 , a first current source, and a plurality of third transistors M3 ⁇ 1:n>.
  • the control electrode of the second transistor M2 is coupled to the control electrodes of the plurality of third transistors M3 ⁇ 1:n> and the second electrode of the second transistor M2, the first electrode of the second transistor M2 is coupled to the second voltage terminal V2, the second electrode of the second transistor M2 is coupled to the first current source, and the first current source is also coupled to the third voltage terminal V3.
  • a first electrode of each third transistor M3 is coupled to the second voltage terminal V2 , and a second electrode of each third transistor M3 is coupled to a first switch circuit 13 (eg, a first electrode of the first transistor M1 ).
  • the second voltage terminal V2 and the third voltage terminal V3 are a power supply voltage terminal VDD and a reference ground voltage terminal GND to each other.
  • the second voltage terminal V2 is a power supply voltage terminal VDD
  • the third voltage terminal V3 is a reference ground voltage terminal GND.
  • the current of the current source branch where the second transistor M2 and the first current source are located is mirrored to the branch where the third transistor M3 is located.
  • the voltage stabilizing circuit 10 further includes a first reverse coupling circuit 15 .
  • the first reverse coupling circuit 15 is coupled between the first delay circuit 12 and the first current source circuit 14 .
  • the first direction coupling circuit 15 is coupled between the first control signal output terminal of the first delay circuit 12 and the control electrode of the third transistor M3 .
  • the first reverse coupling circuit 15 and the third transistors M3 may be arranged in a one-to-one correspondence, or the control electrodes of some third transistors M3 may be coupled to the first reverse coupling circuit 15 .
  • the static operating point of the first current source circuit 14 can be stabilized, the charging and discharging current fluctuation caused by the switch of the third transistor M3 can be compensated, and the influence of coupling noise on the accuracy of the charging current value can be reduced, so that the current of the first current source circuit 14 can be more accurately copied to the voltage output terminal VOT, and the stability of the charging current value can be maintained. At the same time, the influence of noise on the power supply voltage can also be reduced.
  • the first reverse coupling circuit 15 includes a second inverter INV2 and a first capacitor C1.
  • the second inverter INV2 and the first capacitor C1 are coupled in series between the first control signal output terminal VC and the control electrode of the third transistor M3.
  • the first end of the first capacitor C1 is coupled to the control electrode of the third transistor M3
  • the second end of the first capacitor C1 is coupled to the output end of the inverter INV2
  • the input end of the second inverter INV2 is coupled to the first control signal output end VC of the first delay circuit 12 .
  • FIG. 4 is only a schematic diagram.
  • the embodiment of the present application also provides a driving method of a voltage stabilizing circuit, including:
  • the voltage input terminal VI inputs a reference voltage Vref
  • the low-dropout linear regulator LDO receives the reference voltage Vref, and outputs a first voltage v1.
  • the voltage output terminal VOT is used to receive the first voltage v1 and output the second voltage v2.
  • the first voltage terminal V1 inputs the first threshold voltage V1
  • the first comparator 11 receives the second voltage v2 and the first threshold voltage V1, and outputs a first comparison result Vcp.
  • the first delay circuit 12 receives the first comparison result Vcp and outputs a plurality of first control signals Vc.
  • the plurality of first switch circuits 13 receive the first control signal Vc respectively, and regulate the on-off between the second voltage terminal V2 and the voltage output terminal VOT.
  • FIG7 is a detailed structural diagram of a voltage stabilizing circuit 10 provided in an embodiment of the present application
  • FIG8 is a transient response effect diagram of a voltage stabilizing circuit to undershoot provided in an embodiment of the present application.
  • the voltage stabilizing circuit 10 includes three first switch circuits 13.
  • Fig. 8 illustrates the control effect of the voltage stabilizing circuit 10 on the undershoot of the second voltage v2 outputted by the voltage output terminal VOT when the load circuit becomes larger.
  • the second voltage v2 output by the voltage output terminal VOT will change suddenly, generating an undershoot voltage.
  • the first comparator 11 senses that the input positive terminal voltage is lower than the input negative terminal voltage. After a delay of t1, the first comparator 11 outputs a low-level first comparison result Vcp.
  • the low-level first comparison result Vcp (for example, "0") is output to the first-stage first transistor M1 through the input end of the first-stage first delay module 121.
  • the low-level controls the first-stage first transistor M1 to turn on, and the third transistor M3 coupled to the first transistor M1 injects the first current I1 into the voltage output terminal VOT to form a first charging path to compensate for the undershoot of the second voltage v2 (increase in load current), and the undershoot of the second voltage v2 of the voltage output terminal VOT is quickly restored.
  • the second-stage first transistor M1 is turned on after a delay t2, and the current I2 continues to be injected into the voltage output terminal VOT through the third transistor M3 coupled to the second-stage first transistor M1, forming a second charging path, which together with the first charging path injects current into the voltage output terminal VOT.
  • the first comparator 11 senses that the input positive terminal voltage is higher than the input negative terminal voltage, and thus outputs a high level (e.g., "1").
  • the high level simultaneously controls the first-stage first transistor M1, the second-stage first transistor M1, and the third-stage first transistor M1 to be turned off, and the second charging path and the first charging path are cut off at the same time.
  • the path where the third-stage first transistor M1 is located is not turned on and continues to be cut off, thereby preventing the second voltage v2 of the voltage output terminal VOT from excessively rising. This ensures that the second voltage v2 is within the range specified by the undershoot threshold.
  • Example 2 The main difference between Example 2 and Example 1 is that the voltage stabilizing circuit 10 in Example 1 includes a charging module for adjusting undershoot, while the voltage stabilizing circuit 10 in this example includes a discharging module for adjusting overshoot.
  • FIG. 9 is a topological diagram of a voltage stabilization circuit provided in an embodiment of the present application.
  • the voltage stabilizing circuit 10 includes a voltage input terminal VI, a voltage output terminal VOT, a fourth voltage terminal V4 and a fifth voltage terminal V5.
  • the voltage input terminal VI is used, for example, to receive a reference voltage Vref, which is provided, for example, by a bandgap reference (BG) circuit.
  • the voltage output terminal VOT is used to output a stable second voltage v2 to the load.
  • the fourth voltage terminal V4 is used, for example, to receive a second threshold voltage, which is used as a comparison voltage to determine whether an overshoot occurs in the voltage stabilization circuit 10.
  • the fifth voltage terminal V5 can be, for example, a reference ground voltage terminal GND, which is used to receive a reference ground voltage gnd.
  • the voltage stabilization circuit 10 further includes a low dropout linear regulator LDO and a discharge module.
  • the discharge module includes a second comparator 21 , a second delay circuit 22 and a plurality of second switch circuits 23 .
  • the low-dropout linear regulator LDO is configured to receive a reference voltage Vref at a voltage input terminal VI and output a first voltage v1.
  • the structure of the low-dropout linear regulator LDO may be the same as that in Example 1, and will not be described in detail herein.
  • the second comparator 21 is configured to receive the second threshold voltage Vh of the fourth voltage terminal V4 and the second voltage v2 output by the voltage output terminal VOT, and output a second comparison result Vcn after comparing the second threshold voltage Vh with the second voltage v2.
  • the embodiment of the present application does not limit the value of the second threshold voltage Vh.
  • the structure of the second comparator 21 may be the same as that of the first comparator 11 in Example 1, except that the first input terminal of the second comparator 21 is used to receive the second threshold voltage Vh, while the first input terminal of the first comparator 11 is used to receive the first threshold voltage Vl.
  • the second comparator 21 is used to detect the change of the second voltage v2, and uses the second threshold voltage Vh as the maximum reference voltage within the acceptable range.
  • the second threshold voltage Vh is greater than the second threshold voltage Vh, it is determined that the second voltage v2 has overshoot, and the second comparison result Vcn is used to indicate that the second voltage v2 has overshoot.
  • the second comparison result Vcn is used to indicate that the second voltage v2 has not overshoot.
  • the second comparator 21 is an n-type comparator, and when the second voltage v2 overshoots, the second comparison result Vcn is "1". When the second voltage v2 does not overshoot, the second comparison result Vcn is "0".
  • the embodiment of the present application does not limit the type of the second comparator 21, nor does it limit the type of the second comparison result Vcn.
  • the second comparison result Vcn output by the second comparator 21 can control the second switch circuit 23 to turn on.
  • the second delay circuit 22 is configured to receive the second comparison result Vcn and output a plurality of second control signals Vc′ ⁇ 1:n>.
  • the structure of the second delay circuit 22 is the same as the structure of the first delay circuit 12 in Example 1, and reference may be made to the relevant description in Example 1.
  • FIG. 10 is a schematic diagram of the structure of a second delay circuit 22 provided in an embodiment of the present application.
  • the second delay circuit 22 includes a plurality of second delay modules 221 connected in series, a plurality of AND gates, a second comparison result input terminal VCN, and a plurality of second control signal output terminals (eg, VC1′, VC2′, VC3′).
  • the second delay module 221, the second comparison result input terminal VCN and the plurality of second control signal output terminals in the second delay circuit 22 may correspond to the first delay module 121, the first comparison result input terminal VCP and the plurality of first control signal input terminals in the first delay circuit 12 shown in FIG6B .
  • the main difference is that the OR gate in FIG6B is replaced by the AND gate in FIG10 .
  • the AND gate is configured to receive signals from the input and output terminals of the second delay module 221 and output the AND-operated signal to the second control signal output terminal.
  • the AND gate is coupled between the second delay module 221 and the second control signal output terminal.
  • the AND gate includes a first input terminal, a second input terminal, and an output terminal, the first input terminal of the AND gate is coupled to the input terminal of the second delay module 221, the second input terminal of the AND gate is coupled to the output terminal of the second delay module 221, and the output terminal of the AND gate is coupled to the second control signal output terminal.
  • the first input terminal of the first-stage AND gate is coupled to the input terminal of the first-stage second delay module 221 (that is, the first-stage second control signal output terminal VC1′), the second input terminal of the first-stage AND gate is coupled to the output terminal of the first-stage second delay module 221, and the output terminal of the first-stage AND gate is coupled to the second-stage second control signal output terminal VC2′.
  • the first input terminal of the second-stage AND gate is coupled to the The input end of the second-stage second delay module 221 (that is, the second-stage second control signal output end VC2′) is coupled, the second input end of the second-stage AND gate is coupled to the output end of the second-stage second delay module 221, and the output end of the second-stage AND gate is coupled to the third-stage second control signal output end VC3′.
  • the second comparison result Vcn outputted from the second comparator 21 is "1"
  • the second comparison result Vcn is still “1” after the delay after the second delay module 221, and after the AND gate operation
  • the output is still "1”
  • the plurality of second switch circuits 23 are turned on in sequence under the control of the second control signal outputted from the multi-stage second control signal output terminal.
  • an AND gate is set in the second delay circuit 22.
  • the second comparison result Vcn output by the second comparator 21 will control all the second switch circuits 23 to be directly closed, thereby improving the over-compensation of the second voltage v2 caused by the delayed closing of the subsequent second switch circuit 23.
  • FIG. 10 illustrates an example in which the output end of each second delay module 221 is coupled to an AND gate. It is also possible that the output ends of some second delay modules 221 are coupled to an AND gate, while the output ends of some second delay modules 221 are not coupled to an AND gate.
  • each second switch circuit 23 is configured to receive the second control signal Vc′ and regulate the on-off between the fifth voltage terminal V5 and the voltage output terminal VOT.
  • the second switch circuit 23 in this example is arranged in the same position and in the same principle as the first switch circuit 13 in Example 1, and reference may be made to the relevant description in Example 1.
  • the second switch circuit 23 includes a fourth transistor M4 , and the plurality of second switch circuits 23 are a plurality of fourth transistors M4 ⁇ 1:n>.
  • the corresponding relationship between the plurality of fourth transistors M4 ⁇ 1:n> and the second delay circuit 22 may be the same as the corresponding relationship between the plurality of first transistors M1 ⁇ 1:n> and the first delay circuit 12 .
  • the second comparator 21 is an N-type comparator
  • the corresponding fourth transistor M4 is an N-type transistor, which is turned on under the control of a high-level signal.
  • the fifth voltage terminal V5 is the reference ground voltage terminal GND.
  • the solution of this example can be understood as replacing the first transistor M1 in Example 1 from a P-type transistor to an N-type transistor, and replacing the second voltage terminal V2 from the power supply voltage terminal VDD to the reference ground voltage terminal GND.
  • the voltage stabilizing circuit 10 in Example 1 can compensate for undershoot of the output voltage.
  • the voltage stabilizing circuit 10 can compensate for overshoot of the output voltage.
  • Other effects are the same as those in Example 1 and will not be described here.
  • the voltage stabilizing circuit 10 further includes a second current source circuit 24 .
  • the second current source circuit 24 is coupled between the fifth voltage terminal V5 and the plurality of second switch circuits 23 .
  • the structure and principle of the second current source circuit 24 may be the same as the structure and principle of the first current source circuit 14 in Example 1, and will not be described in detail here.
  • the second current source circuit 24 includes a fifth transistor M5 , a second current source, and a plurality of sixth transistors M6 ⁇ 1:n>.
  • the control electrode of the fifth transistor M5 is coupled to the control electrodes of multiple sixth transistors M6 ⁇ 1:n> and the second electrode of the fifth transistor M5, the first electrode of the fifth transistor M5 is coupled to the second voltage terminal V2, the second electrode of the fifth transistor M5 is coupled to the second current source, and the second current source is also coupled to the sixth voltage terminal V6.
  • a first electrode of each sixth transistor M6 is coupled to the fifth voltage terminal V5 , and a second electrode of each sixth transistor M6 is coupled to a second switch circuit 23 (eg, a first electrode of the fourth transistor M4 ).
  • the fifth voltage terminal V5 and the sixth voltage terminal V6 are a power supply voltage terminal VDD and a reference ground voltage terminal GND to each other.
  • the sixth voltage terminal V6 is the power supply voltage terminal VDD
  • the fifth voltage terminal V5 is the reference ground voltage terminal GND.
  • the voltage stabilizing circuit 10 further includes a second reverse coupling circuit 25 .
  • the second reverse coupling circuit 25 is coupled between the second delay circuit 22 and the second current source circuit 24 .
  • the structure and principle of the second reverse coupling circuit 25 may be the same as the structure and principle of the first reverse coupling circuit 15 in Example 1, and will not be described in detail here.
  • FIG. 11 is a schematic diagram of the structure of a voltage stabilizing circuit 10 provided in an embodiment of the present application.
  • the second comparator 21 senses that the input positive terminal voltage is higher than the input negative terminal voltage, and the second comparator 21 outputs a high-level second comparison result Vcn.
  • the high-level second comparison result Vcn (for example, "1") is outputted to the first-stage fourth transistor M4 through the input terminal of the first-stage second delay module 221.
  • the high-level controls the first-stage fourth transistor M4 to turn on, and the sixth transistor M6 coupled to the fourth transistor M4 provides a current path to the ground for the voltage output terminal VOT, forming a first discharge path.
  • the excess current of the voltage output terminal VOT can be discharged through the first discharge path, thereby compensating for the overshoot of the second voltage v2 (reduction of the load current), and the overshoot of the second voltage v2 of the voltage output terminal VOT is quickly restored. If the load current variation exceeds the maximum current that the sixth transistor M6 can provide, the second-stage fourth transistor M4 is turned on after a delay, and the sixth transistor M6 coupled to the second-stage fourth transistor M4 continues to provide a current path to the ground for the voltage output terminal VOT, forming a second discharge path. The first discharge path and the second discharge path together discharge current for the voltage output terminal VOT.
  • the second comparator 21 senses that the input positive terminal voltage is lower than the input negative terminal voltage, and thus outputs a low level (e.g., "0").
  • This low level simultaneously controls the first-stage fourth transistor M4, the second-stage fourth transistor M4, and the third-stage fourth transistor M4 to be turned off, and the second discharge path and the first discharge path are cut off at the same time, and the path where the third-stage fourth transistor M4 is located is not turned on and continues to be cut off, thereby preventing the second voltage v2 of the voltage output terminal VOT from being excessively reduced. This ensures that the second voltage v2 is within the range specified by the overshoot threshold.
  • the second voltage terminal V2 in Example 1 is the reference ground voltage terminal GND (equivalent to the fifth voltage terminal V5 of this example)
  • the third voltage terminal V3 is the power supply voltage terminal VDD (equivalent to the sixth voltage terminal V6 of this example)
  • the first transistor M1, the second transistor M2, and the third transistor M3 are N-type transistors
  • the first comparator 11 is an N-type comparator
  • the voltage stabilizing circuit 10 can also compensate for overshoot.
  • the voltage stabilizing circuit 10 provided in Example 3 includes both the charging module for adjusting undershoot and the discharging module for adjusting overshoot in Example 1.
  • FIG. 12 is a topological diagram of a voltage stabilization circuit provided in an embodiment of the present application.
  • the voltage stabilizing circuit 10 includes both the charging module in Example 1 and the discharging module in Example 2, so that the second voltage v2 output by the voltage stabilizing circuit 10 is within the range specified by the overshoot threshold and the undershoot threshold.
  • the voltage stabilizing circuit 10 provided in the embodiment of the present application can be integrated in the same chip, and the voltage stabilizing circuit 10 is arranged on a substrate (such as a silicon substrate) as a low voltage drop linear regulator chip provided in the embodiment of the present application.
  • the low voltage drop linear regulator chip provided in the embodiment of the present application can be a bare chip or a packaged chip.
  • the embodiment of the present application further provides a chip system, which includes a load circuit and a voltage regulator circuit 10 provided in the embodiment of the present application, and a voltage output terminal VOT of the voltage regulator circuit 10 is coupled to the load circuit.
  • the chip system includes a load circuit and a low voltage drop linear regulator chip provided in the embodiment of the present application, and a voltage output terminal VOT in the low voltage drop linear regulator chip is coupled to the load circuit.
  • the chip system can be, for example, a microcontroller unit (MCU), a radio frequency (RF) transceiver, a high-speed digital circuit (for example, a chip system SoC), etc.
  • MCU microcontroller unit
  • RF radio frequency
  • SoC chip system SoC
  • An embodiment of the present application also provides an electronic device, which includes any one of the voltage stabilizing circuits 10 or low voltage difference linear regulator chips or chip systems provided above.
  • the voltage stabilizing circuit 10 is used to power a load circuit.
  • the voltage stabilizing circuit 10 can be arranged on a circuit board in the electronic device.

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Abstract

本申请提供一种稳压电路、低压差线性稳压器芯片、芯片系统及电子设备，涉及电子技术领域，用于改善输出电压不稳定的问题，可以应用于MCU中。稳压电路包括电压输入端、电压输出端、第一电压端、第二电压端、LDO、第一比较器、第一延时电路以及多个第一开关电路。LDO被配置为接收电压输入端的基准电压，并输出第一电压。电压输出端被配置为接收第一电压，并输出第二电压。第一比较器被配置为接收第一电压端的第一阈值电压和第第一电压，并输出第一比较结果。第一延时电路被配置为接收第一比较结果，并输出多个第一控制信号。多个第一开关电路并联设置，每个第一开关电路被配置为接收第一控制信号，并调控第二电压端与电压输出端之间的通断。

Description

稳压电路、低压差线性稳压器芯片、芯片系统及电子设备
本申请要求于2023年04月25日提交国家知识产权局、申请号为202310476998.1、申请名称为“稳压电路、低压差线性稳压器芯片、芯片系统及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，尤其涉及一种稳压电路、低压差线性稳压器芯片、芯片系统及电子设备。
背景技术
低压差线性稳压器(low dropout regulator，LDO)作为电源管理系统的核心模块之一，凭借电路结构简单、尺寸小、噪声低、外围电子设备少等优势被广泛应用在新型存储器和高速数字电路中。目前，在LDO的应用过程中，当LDO的外部负载电流发生变化时，其输出电压的瞬态幅度会出现较大的上冲或下冲，导致输出电压出现电压纹波(不稳定)。
然而，输出电压的稳定性对负载性能有着直接的影响。
发明内容
本申请实施例提供一种稳压电路、低压差线性稳压器芯片、芯片系统及电子设备，用于改善输出电压不稳定的问题。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种稳压电路，包括电压输入端、电压输出端、第一电压端以及第二电压端，还包括低压差线性稳压器、第一比较器、第一延时电路以及多个第一开关电路，低压差线性稳压器作为稳压电路中的低压差线性稳压器主模块(或者本体模块)，第一比较器、第一延时电路以及多个第一开关电路可以作为稳压电路中的瞬态响应增强模块。低压差线性稳压器被配置为接收电压输入端的基准电压，并输出第一电压。电压输出端被配置为接收第一电压，并输出第二电压。第一比较器被配置为接收第一电压端的第一阈值电压和第二电压，并输出第一比较结果。第一延时电路被配置为接收第一比较结果，并输出多个第一控制信号。多个第一开关电路并联设置，每个第一开关电路被配置为接收第一控制信号，并调控第二电压端与电压输出端之间的通断。
本申请实施例中，采用数模混合架构的稳压电路结构，在稳压电路中设置第一比较器，可快速响应电压输出端输出的第二电压的变化。并通过第一延时电路逐级控制多个第一开关电路的导通，构成第二电压端到电压输出端的补偿通路，以补偿负载电流瞬间变化所引起的第二电压(稳压电路的输出电压)的大幅变化，保持第二电压在阈值范围内，以提高稳压电路输出电压的稳定性。另外，由于对电压输出端注入(或者泄放)的电流值可以由多个第一开关电路调节，因此，第二电压端向电压输入端注入(或者泄放)的电流值可根据实际应用场景而定，可应对的负载电流变化范围较大。此外，在多个第一开关电路分级导通的情况下，对于负载电流变化较小的应用场景，部分第一开关电路导通即可将第二电压补偿至阈值范围内，那么，其余第一开关电路则无需再开启，有利于减小动态功耗。再者，稳压电路所包括的电路结构可以均为片内集成结构，可减小稳压电路的面积，去除引入片外电容所带来的额外成本。再次，在第二电压端为电源电压端时，由于第一开关电路所在的充电通路会从第二电压端处抽取较大电流，由于第二电压端焊盘绑定(bonding)线的寄生电感的存在，从第二电压端抽拉电流会导致第二电压端的电源电压产生噪声波动，影响其他模块的正常工作。而本申请实施例中通过将第一开关电路设置为逐级开启的多个，通过多级控制逻辑，增多抽拉次数，可以减小每次从第二电压端抽拉的电流量。而每次抽拉的电流越小，电源电压产生的噪声波动的幅值越小，因此可以改善电源电压波动较大的问题。
在一种可能的实现方式中，稳压电路还包括第一电流源电路；第一电流源电路耦接于第二电压端与多个第一开关电路之间。
通过在第二电压端与第一开关电路之间设置第一电流源电路，第一电流源电路可以提供准确 固定的充电电流值，以提高对第二电压的补偿精准度，改善了宽电源电压范围内充放电电流变化值较大的问题。
在一种可能的实现方式中，稳压电路还包括第一反向耦合电路；第一反向耦合电路耦接于第一延时电路与第一电流源电路之间。
通过设置第一反向耦合电路，可以稳定第一电流源电路的静态工作点，补偿第一电流源电路的充放电电流波动，减少耦合噪声对充电电流值精度的影响，使第一电流源电路的电流能够更精确的复制到电压输出端，保持充电电流值的稳定性。同时也可以减小对电源电压的噪声影响。
在一种可能的实现方式中，第一延时电路包括串联的多个第一延时模块、第一比较结果输入端以及多个第一控制信号输出端；每个第一延时模块的输入端和输出端均配置有第一控制信号输出端；第一延时电路被配置为由第一比较结果输入端接收第一比较结果，由第一控制信号输出端输出第一控制信号。
本申请实施例中，第一延时电路包括多个第一延时模块，多个第一延时模块用于控制多个第一开关电路依次导通，多个第一开关电路所在的通路分次从第二电压端获取电流，可有效减小第二电压端的电压的波动。此外，对于负载电流变化较小的应用场景，分级导通第一开关电路有利于减小动态功耗。
在一种可能的实现方式中，第一延时电路还包括多个或门；或门被配置为接收第一延时模块的输入端和输出端的信号，并向第一控制信号输出端输出或运算后的信号。
通过在第一延时电路中设置或门，当电压输出端输出的第二电压被调节至正常范围后，第一比较器输出的第一比较结果将控制所有第一开关电路直接关闭，可改善由于后级第一开关电路延时关闭而导致的第二电压过补偿的情况。
在一种可能的实现方式中，第一延时电路还包括多个与门；与门被配置为接收第一延时模块的输入端和输出端的信号，并向第一控制信号输出端输出与运算后的信号。
通过在第一延时电路中设置与门，当电压输出端输出的第二电压被调节至正常范围后，第一比较器输出的第一比较结果将控制所有第一开关电路直接关闭，可改善由于后级第一开关电路延时关闭而导致的第二电压过补偿的情况。
在一种可能的实现方式中，第一比较器包括级联的多级第一运算放大器。
通过在第一比较器中设置多级第一运算放大器，可以大幅增加第一比较器的增益。
在一种可能的实现方式中，第一比较器还包括与多级第一运算放大器的输出端耦接的多级第一反相器。
通过在第一比较器中设置多级第一反相器，可以提高对第一开关电路的驱动能力，从而提高电压输出端输出的电压的变化范围(摆幅)，实现高增益高速的第一比较器。高增益高速的第一比较器可以提高第一比较器的处理速度，以提高充电模块的响应速度，缩短电压输出端输出的第二电压的恢复时间，提高了稳压电路的瞬态响应特性。
在一种可能的实现方式中，第一开关电路包括第一晶体管；第一晶体管的控制极与第一延时电路耦接，第一晶体管的第一极与第二电压端耦接，第一晶体管的第二极与电压输出端耦接。这是一种结构简单的第一开关电路。
在一种可能的实现方式中，第一晶体管为P型晶体管，第二电压端为电源电压端。这样一来，稳压电路可以调整电压输出端输出的电压出现的下冲。
在一种可能的实现方式中，第一晶体管为N型晶体管，第二电压端为参考地电压端。这样一来，稳压电路可以调整电压输出端输出的电压出现的过冲。
在一种可能的实现方式中，第一电流源电路包括电流镜。
采用电流镜作为电流源，充电电流值较为稳定，可适用于宽电源电压范围的中高频(百兆赫兹级别)芯片(例如MCU芯片)。
在一种可能的实现方式中，第一电流源电路包括第二晶体管、第一电流源、多个第三晶体管；第二晶体管的控制极与多个第三晶体管的控制极和第二晶体管的第二极耦接，第二晶体管的第一极与第二电压端耦接，第二晶体管的第二极与第一电流源耦接；第一电流源还与第三电压端耦接；每个第三晶体管的第一极与第二电压端耦接，每个第三晶体管的第二极与一个第一开关电路耦接。 这是一种结构简单的电流镜结构。
在一种可能的实现方式中，第二电压端和第三电压端互为电源电压端和参考地电压端。这样一来，稳压电路可以调整电压输出端输出的电压出现的过冲或者下冲。
在一种可能的实现方式中，第一反向耦合电路包括第二反相器和第一电容；第二反相器和第一电容串联耦接于第一控制信号输出端与第三晶体管的控制极之间。这是一种结构简单的第一反向耦合电路。
在一种可能的实现方式中，稳压电路还包括第二比较器、第二延时电路、并联的多个第二开关电路、第四电压端以及第五电压端。第二比较器被配置为接收第四电压端的第二阈值电压和第二电压，并输出第二比较结果。第二延时电路被配置为接收第二比较结果，并输出多个第二控制信号。每个第二开关电路被配置为接收第二控制信号，并调控第五电压端与电压输出端之间的通断。这样一来，稳压电路可以具有调整电压输出端输出的电压出现的过冲和下冲的能力。
在一种可能的实现方式中，稳压电路还包括第二电流源电路；第二电流源电路耦接于第五电压端与多个第二开关电路之间。
通过在第五电压端与第二开关电路之间设置第二电流源电路，第二电流源电路可以提供准确固定的充电电流值，以提高对第二电压的补偿精准度，改善了宽电源电压范围内充放电电流变化值较大的问题。
在一种可能的实现方式中，稳压电路还包括第二反向耦合电路；第二反向耦合电路耦接于第二延时电路与第二电流源电路之间。
通过设置第二反向耦合电路，可以稳定第二电流源电路的静态工作点，补偿第二电流源电路的充放电电流波动，减少耦合噪声对充电电流值精度的影响，使第二电流源电路的电流能够更精确的复制到电压输出端，保持充电电流值的稳定性。同时也可以减小对电源电压的噪声影响。
本申请实施例的第二方面，提供一种低压差线性稳压器芯片，包括基底和第一方面任一项的稳压电路，稳压电路设置在基底上。
本申请实施例的第三方面，提供一种芯片系统，包括第一方面任一项的稳压电路或者第二方面的低压差线性稳压器芯片以及负载电路；稳压电路的电压输出端与负载电路耦接。
本申请实施例的第四方面，提供一种电子设备，包括第一方面任一项的稳压电路或者第二方面的低压差线性稳压器芯片或者第三方面的芯片系统和电路板，稳压电路设置在电路板上。
本申请实施例的第五方面，提供一种稳压电路的驱动方法，包括：电压输入端输入基准电压，低压差线性稳压器接收基准电压，并输出第一电压；电压输出端接收第一电压并输出第二电压；第一电压端输入第一阈值电压，第一比较器接收第二电压和第一阈值电压，并输出第一比较结果；第一延时电路接收第一比较结果，并输出多个第一控制信号；多个第一开关电路分别接收第一控制信号，并调控第二电压端与电压输出端之间的通断；
附图说明
图1为本申请实施例提供的一种MCU的构架示意图；
图2A-图2C为本申请实施例提供的一种稳压电路的拓扑示意图；
图3为本申请实施例提供的一种稳压电路的架构示意图；
图4为本申请实施例提供的一种稳压电路的拓扑示意图；
图5A和图5B为本申请实施例提供的一种第一比较器的结构示意图；
图6A和图6B为本申请实施例提供的一种第一延时电路的结构示意图；
图7为本申请实施例提供的一种稳压电路的详细结构示意图；
图8为本申请实施例提供的一种稳压电路对下冲的瞬态响应效果图；
图9为本申请实施例提供的一种稳压电路的拓扑示意图；
图10为本申请实施例提供的一种第二延时电路的结构示意图；
图11为本申请实施例提供的一种稳压电路的结构示意图；
图12为本申请实施例提供的一种稳压电路的拓扑示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述 的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第二”、“第一”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第二”、“第一”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请实施例中，“上”、“下”、“左”、“右”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“相耦接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。术语“接触”可以是直接接触，也可以是通过中间媒介间接的接触。
本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
本申请实施例中所涉及的晶体管可以是金属氧化物半导体(metal oxide semiconductor，MOS)场效应晶体管(可以简称为MOS管)。本申请实施例中晶体管的控制端可以是指晶体管的栅极；在一种可能的实施例中，晶体管的第一极可以是指源极，第二极可以是指漏极；在另一种可能的实施例中，晶体管的第一极可以是指漏极，第二极可以是指源极。
本申请实施例提供一种的电子设备，该电子设备例如为消费性电子产品、家居式电子产品、金融终端产品、通信电子产品、医疗仪器电子产品、汽车电子产品等。其中，消费性电子产品如为手机(mobile phone)、平板电脑(pad)、笔记本电脑、电子阅读器、个人计算机(personal computer，PC)、个人数字助理(personal digital assistant，PDA)、桌面显示器、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)电子设备、增强现实(augmented reality，AR)电子设备、无人机等。家居式电子产品如为智能门锁、电视、遥控器、冰箱、充电家用小型电器(例如豆浆机、扫地机器人)等。金融终端产品如为自动取款机(automated teller machine，ATM)机、自助办理业务的终端等。通信电子产品如为服务器、非易失存储器、雷达、基站等通信电子设备。医疗仪器电子产品例如各种检测仪器、制氧机等。本申请实施例对上述电子设备的具体形式不做特殊限制。
微控制器(又称微控制单元，microcontroller unit，MCU)是一种针对特定应用的控制处理而设计的微处理器芯片，可以将中央处理器(central processing unit，CPU)、存储器(包括易失性存储器和非易失性存储器)、多种输入/输出(I/O)接口等集成在一片芯片上，以形成芯片级计算机。MCU在工业控制、智能电子设备、家用电器、医疗仪器、汽车电子等领域都有广泛的应用。
本申请实施例提供的电子设备例如可以包括MCU，MCU可以设置在电子设备的电路板上。
图1为本申请实施例提供的一种MCU的构架示意图。
如图1所示，示例一种MCU，MCU包括CPU、存储器以及稳压电路10。CPU和存储器用于为电子设备提供处理和存储功能，可将二者集成在MCU中。稳压电路10用于为MCU提供工作所需的电源电压。
稳压电路10凭借电路结构简单、尺寸小、噪声低、外围电子设备少等优势，成为MCU供电模块的主流选择。
通常MCU的工作电流最高可达几十毫安，且会因为应用场景的变化，工作电流会快速变化，这要求稳压电路10能在各种应用场景下提供较为稳定的输出电压。
图2A-图2C为本申请实施例提供的一种稳压电路的拓扑示意图。
关于稳压电路10的结构，在一些实施例中，如图2A所示，稳压电路10包括低压差线性稳压器(low dropout regulator，LDO)。
该LDO可以包括：误差放大器(error amplifier，EA)、晶体管M0和反馈电路。反馈电路包括第一电阻R1和第二电阻R2。
以晶体管M0为P型金属场效应晶体管(positive channel metal oxide semiconductor，PMOS) 为例，误差放大器EA的输出端与晶体管M0的控制端(即PMOS的栅极)耦合。晶体管M0的第一极(比如，PMOS的漏极)作为该LDO的电压输出端VOT，同时与反馈电路的输入端相耦合。晶体管M0的第二极(比如，PMOS的源极)与电源电压端VDD耦合。反馈电路的输出端与误差放大器EA的负相输入端耦合，误差放大器EA的正相输入端用于接收参考电压Vref。接收参考电压Vref例如可以是通过带隙基准(bandgap，BG)电路产生。电压输出端VOT为后级负载提供了与电源电压端VDD的电源电压Vdd无关的固定电压值。
具体的，当该LDO在上电或者后级负载发生变化时，该LDO的电压输出端VOT输出的第二电压v2会出现上冲或下冲的现象，此时该反馈电路通过第一电阻R1和第二电阻R2对第二电压v2进行采样，并将采样到的反馈电压Vfb传输至误差放大器EA的负相输入端。误差放大器EA对该反馈电压Vfb和正相输入端接收的参考电压Vref进行比较并放大，放大后的电压作为晶体管M0的栅极电压Vg，该栅极电压Vg通过改变流过晶体管M0的导通电流Ip来动态的调整第二电压v2，以实现该LDO的稳压输出。
示例性的，当第二电压v2减小时反馈电压Vfb减小，反馈电压Vfb的减小会引起栅极电压Vg减小，随着栅极电压Vg的减小导通电流Ip增大，从而增大第二电压v2。同理，当第二电压v2增大时反馈电压Vfb增大，反馈电压Vfb的增大会引起栅极电压Vg增大，随着栅极电压Vg的增大导通电流Ip减小，从而减小第二电压v2。
在另一些实施例中，如图2B所示，稳压电路10在包括LDO的基础上，还包括片外电容C和由该片外电容C引入的等效寄生电阻Resr。等效寄生电阻Resr为稳压电路10引入一个零点，利用该零点可抵消次极点的影响，满足稳定性要求。
当负载电流发生突变，片外电容型稳压电路10主要依靠片外电容C的充放电来维持第二电压v2的稳定，避免第二电压v2出现过大的下冲与过冲。例如，负载由轻载变为重载时，由于带宽限制，晶体管M0无法立刻提供足够的电流，在短时间内由片外电容C提供其余的电流。下式为第二电压v2下冲值的定义式，其中△IOUT为负载电流的变化值，t1为下冲时间，其大小取决于LDO的闭环带宽与压摆率，△VESR为等效寄生电阻Resr两端的电压差。由下式(1)可知，在同样的时间内，片外电容C越大，则第二电压v2的下冲值越小。
对于片外电容型稳压电路10，选用具有较大等效寄生电阻Resr的输出电容更易保证系统稳定，因此不得不选用价格昂贵的钽电容，提高了设计的成本。此外，片外电容C的容值通常需要在uF级别，在设计时需要留出专门的管脚连接片外电容C，LDO和片外电容C之间的连线(例如绑定(bonding)线)上的寄生电感和天线效应会降低稳压电路10的第二电压v2的质量。
在又一些实施例中，如图2C所示，稳压电路10在包括LDO的基础上，还包括片内集成的调整电路，调整电路的结构如图2C所示。
当电压输出端VOT输出的电压发生过冲与下冲时，反馈电压Vfb随之同步变化，调整电路感知到反馈电压Vfb的变化，把检测出的过冲或下冲直接通过调整电路进行补偿。调整电路对电压输出端VOT输出的电压进行充放电，以减小过冲与下冲。
这种方案的稳压电路10结构简单，但是充放电电流通过晶体管T1和晶体管T2直接抽拉，会给电源电压造成较大噪声影响。而且在应对大负载电流变化时，具有较大的静态功耗，调整的负载电流能力有限，且不适用于宽电源电压范围。
基于此，本申请实施例还提供一种稳压电路10，在改善稳压电路10的输出电压不稳定的同时，降低对电源电压的噪声影响。
下面以几个示例对本申请实施例提供的稳压电路10进行示意性说明。
示例一
图3为本申请实施例提供的一种稳压电路的架构示意图，图4为本申请实施例提供的一种稳压电路的拓扑示意图。
如图3所示，本申请实施例提供一种稳压电路10，稳压电路10可以集成在一个芯片(裸芯片或者封装后的芯片)中。
稳压电路10包括电压输入端VI、电压输出端VOT、第一电压端V1以及第二电压端V2，电 压输入端VI例如用于接收基准电压Vref，基准电压Vref例如由带隙基准(bandgap，BG)电路提供。电压输出端VOT用于向负载输出稳定的第二电压v2。第一电压端V1例如用于接收第一阈值电压，第一阈值电压用于作为对比电压，以判断稳压电路10是否出现下冲(undershoot)。第二电压端V2例如可以为电源电压端VDD，用于接收电源电压Vdd。
稳压电路10还包括低压差线性稳压器LDO和充电模块，充电模块包括第一比较器(comparator)11、第一延时电路12以及多个第一开关电路13。
低压差线性稳压器LDO被配置为接收电压输入端VI的基准电压Vref，并输出第一电压v1。
在一些实施例中，如图4所示，低压差线性稳压器LDO包括误差放大器EA、晶体管M0和反馈电路。反馈电路包括第一电阻R1和第二电阻R2。
误差放大器EA的第一输入端与电压输入端VI耦接，误差放大器EA的第二输入端耦接至第一电阻R1和第二电阻R2之间，误差放大器EA的输出端与晶体管M0的控制极耦接。
晶体管M0的第一极与第一电阻R1的第一端耦接，晶体管M0的第二极与第二电压端耦接。
第二电阻R2的第一端与第一电阻R1的第一端耦接，第二电阻R2的第二端与参考地电压端GND耦接。
低压差线性稳压器LDO的输出端耦接至晶体管M0的第一极与第一电阻R1的第一端之间，低压差线性稳压器LDO的输出端用于输出第一电压v1。
当然，本申请实施例对低压差线性稳压器LDO的结构不作限定，相关技术中的低压差线性稳压器LDO均适用于本申请实施例中，图4所示的低压差线性稳压器LDO的结构仅为一种示意。
电压输出端VOT被配置为接收低压差线性稳压器LDO输出的第一电压v1，并输出第二电压v2。
可以理解的是，在第一电压v1在阈值范围内时，第二电压v2等于第一电压v1。在第一电压v1出现下冲时，第二电压v2为对第一电压v1注入补偿后的稳定电压。
请继续参考图3，第一比较器11被配置为接收第一电压端V1的第一阈值电压Vl和第二电压v2，对第一阈值电压Vl和第二电压v2进行比较后，输出第一比较结果Vcp。
示例的，第一比较器11的第一输入端与第一电压端V1耦接，第一比较器11的第一输入端用于接收第一阈值电压Vl。第一比较器11的第二输入端与低压差线性稳压器LDO的输出端耦接，第一比较器11的第二输入端用于接收第二电压v2，第一比较器11的输出端与第一延时电路12耦接，第一比较器11的输出端用于将第一比较结果输出至第一延时电路12。
第一比较器11用于检测第二电压v2的变化，将第一阈值电压Vl作为可接受范围内的最小参照电压，在第二电压v2小于第一阈值电压Vl的情况下，判定第二电压v2出现下冲，第一比较结果Vcp用于指示第二电压v2出现下冲。在第二电压v2大于第一阈值电压Vl的情况下，判定第二电压v2未出现下冲，第一比较结果Vcp用于指示第二电压v2未出现下冲。
示例的，第一比较器11为P型比较器，在第二电压v2出现下冲的情况下，第一比较结果Vcp为“0”。在第二电压v2未出现下冲的情况下，第一比较结果Vcp为“1”。
本申请实施例对第一比较器11的类型不作限定，对第一比较结果Vcp的类型也不作限定，在第二电压v2出现下冲的情况下，第一比较器11输出的第一比较结果Vcp可以控制第一开关电路13开启即可。本申请实施例中仅是以第一比较器11为P型比较器，在第二电压v2出现下冲的情况下，第一比较结果Vcp为“0”。在第二电压v2未出现下冲的情况下，第一比较结果Vcp为“1”为例进行示意。
当然，本申请实施例对第一阈值电压Vl的取值不作限定。
本申请实施例对第一比较器11的结构不作限定，相关技术中的比较器均适用于本申请实施例中。
在一些实施例中，第一比较器11为高速比较器。例如，第一比较器11为输出延时为纳秒级别的比较器。
图5A和图5B为本申请实施例提供的一种第一比较器11的结构示意图。
在一些实施例中，如图5A所示，第一比较器11包括级联的多级第一运算放大器(operational amplifier)OP1，图5A中以第一比较器11包括三级级联的第一运算放大器OP1为例进行示意。
第一级第一运算放大器OP1的输入端作为第一比较器11的输入端。例如，第一级第一运算放大器OP1的第一输入端与第一电压端V1耦接，第一级第一运算放大器OP1的第二输入端与低压差线性稳压器LDO的输出端耦接。第二级第一运算放大器OP1与第一级第一运算放大器OP1级联，第三级第一运算放大器OP1与第二级第一运算放大器OP1级联。第三级第一运算放大器OP1的输出端作为第一比较器11的输出端。
通过在第一比较器11中设置多级第一运算放大器OP1，可以大幅增加第一比较器11的增益。
当然，本申请实施例中的第一比较器11也可以仅包括一级第一运算放大器。
在一些实施例中，如图5B所示，第一比较器11还包括与多级第一运算放大器OP1的输出端耦接的多级第一反相器(inverter)INV1，图5B中以第一比较器11包括两级第一反相器INV1为例进行示意。
第一级第一反相器INV1的输入端与最后一级第一运算放大器OP1的输出端耦接，第二级第一反相器INV1的输入端与第一级第一反相器INV1的输入端耦接，第二级第一反相器INV1的输出端作为第一比较器11的输出端。
通过在第一比较器11中设置多级第一反相器INV1，可以提高对第一开关电路13的驱动能力，从而提高电压输出端VOT输出的电压的变化范围(摆幅)，实现高增益高速的第一比较器11。高增益高速的第一比较器11可以提高第一比较器11的处理速度，以提高充电模块的响应速度，缩短电压输出端VOT输出的第二电压v2的恢复时间，提高了稳压电路10的瞬态响应特性。
当然，本申请实施例中的第一比较器11也可以仅包括一级第一反相器INV1。
在一些实施例中，第一比较器11例如为P型比较器。
请继续参考图3，第一延时电路12被配置为接收第一比较结果Vcp，并输出多个第一控制信号Vc<1:n>。
示例的，第一延时电路12包括第一比较结果输入端和多个第一控制信号输出端，第一延时电路12的第一比较结果输入端与第一比较器11的输出端耦接，第一延时电路12的第一控制信号输出端用于接收第一比较结果Vcp。第一延时电路12的多个第一控制信号输出端与多个第一开关电路13对应耦接，例如，第一延时电路12的一个第一控制信号输出端与一个第一开关电路13的输入端耦接。
第一延时电路12被配置为由第一比较结果输入端接收第一比较结果，由第一控制信号输出端输出第一控制信号。
在一些实施例中，第一延时电路12的多个第一控制信号输出端均用于输出对第一比较结果Vcp进行延时后的延时信号。或者理解为，第一延时电路12的多个第一控制信号输出端输出的第一控制信号均相对第一比较结果Vcp有所延时。那么，每个第一开关电路13均收到延时后的延时信号。
在另一些实施例中，第一延时电路12的多个第一控制信号输出端中，一个第一控制信号输出端用于输出未延时的信号(也就是直接输出第一比较结果Vcp)，其他第一控制信号输出端用于输出对第一比较结果Vcp进行延时后的延时信号。那么，一个第一开关电路13直接收到第一比较结果Vcp)，其他第一开关电路13均收到延时后的延时信号。例如，其他第一开关电路13陆续依次收到延时信号，或者理解为，其他第一开关电路13收到的延时信号的延时程度不同，以使其他第一开关电路13依次开启。
图6A和图6B为本申请实施例提供的一种第一延时电路12的结构示意图。
在一些实施例中，如图6A所示，第一延时电路12包括串联的多个第一延时(delay)模块121、第一比较结果输入端VCP以及多个第一控制信号输出端(例如VC1、VC2、VC3)。
可以理解的是，多个第一延时模块121的结构(延时程度)可以相同，多个第一延时模块121的结构(延时程度)也可以不相同。
在一些实施例中，每个第一延时模块121的输出端均配置有第一控制信号输出端。这样一来，每个第一控制信号输出端输出的第一控制信号均为对第一比较结果Vcp进行延时后的延时信号。
当然，也可以是部分第一延时模块121的输出端配置有第一控制信号输出端，部分第一延时模块121的输出端未配置第一控制信号输出端。
在另一些实施例中，如图6A所示，每个第一延时模块121的输入端和输出端均配置有第一控制信号输出端。
示例的，如图6A所示，相邻两级第一延时模块121之间设置有一个第一控制信号输出端，相邻两级第一延时模块121之间的第一控制信号输出端作为前一级第一延时模块121的输出端对应配置的第一控制信号输出端，同时又作为后一级第一延时模块121的输入端对应配置的第一控制信号输出端。
或者，示例的，相邻两级第一延时模块121之间设置有两个第一控制信号输出端，一个第一控制信号端作为位于前一级第一延时模块121的输出端对应配置的第一控制信号输出端，另一个第一控制信号输出端作为后一级第一延时模块121的输入端对应配置的第一控制信号输出端。但两个第一控制信号输出端输出的第一控制信号的相对第一比较结果Vcp的延时程度相同。
图6A中以第一延时电路12包括三个第一控制信号输出端为例进行示意，三个第一控制信号输出端分别为第一级第一控制信号输出端VC1、第二级第一控制信号输出端VC2以及第三级第一控制信号输出端VC3。
例如，每个第一延时模块121的延时程度为5nS，那么，第一级第一控制信号输出端VC1输出的第一控制信号Vc1相对第一比较结果Vcp未延时，第二级第一控制信号输出端VC1输出的第一控制信号Vc2相对第一比较结果Vcp延时5nS，第三级第一控制信号输出端VC3输出的第一控制信号Vc3相对第一比较结果Vcp延时10nS、相对第一控制信号Vc2延迟5nS。
当然，也可以是部分第一延时模块121的输入端和输出端均配置有第一控制信号输出端，部分第一延时模块121的输入端和/或输出端未配置第一控制信号输出端。
本申请实施例中，第一延时电路12包括多个第一延时模块121，多个第一延时模块121用于控制多个第一开关电路13依次导通，多个第一开关电路13所在的通路分次从第二电压端V2获取电流，可有效减小第二电压端V2的电压的波动。此外，对于负载电流变化较小的应用场景，分级导通第一开关电路13有利于减小动态功耗。
在一些实施例中，如图6B所示，第一延时电路12还包括多个或门。
或门被配置为接收第一延时模块121的输入端和输出端的信号，并向第一控制信号输出端输出或运算后的信号。
示例的，或门耦接于第一延时模块121与第一控制信号输出端之间。例如，或门包括第一输入端、第二输入端、以及输出端，或门的第一输入端与第一延时模块121的输入端耦接，或门的第二输入端与第一延时模块121的输出端耦接，或门的输出端与第一控制信号输出端耦接。
以图6B为例，第一级或门的第一输入端与第一级第一延时模块121的输入端(也就是第一级第一控制信号输出端VC1)耦接，第一级或门的第二输入端与第一级第一延时模块121的输出端耦接，第一级或门的输出端与第二级第一控制信号输出端VC2耦接。第二级或门的第一输入端与第二级第一延时模块121的输入端(也就是第二级第一控制信号输出端VC2)耦接，第二级或门的第二输入端与第二级第一延时模块121的输出端耦接，第二级或门的输出端与第三级第一控制信号输出端VC3耦接。
示例的，在稳压电路10输出的第二电压v2出现下冲的情况下，第一比较器11输出的第一比较结果Vcp为“0”，第一比较结果Vcp经第一延时模块121后依旧为延时后的“0”，经过或门运算后，输出的依旧为“0”，多个第一开关电路13在多级第一控制信号输出端输出的第一控制信号的控制下依次开启。而在稳压电路10输出的第二电压v2未出现下冲的情况下，第一比较结果Vcp为“1”。只要出现“1”，或门运算输出全为“1”，多个第一开关电路13同步关断。
本申请实施例中，通过在第一延时电路12中设置或门，当电压输出端VOT输出的第二电压v2被调节至正常范围后，第一比较器11输出的第一比较结果Vcp将控制所有第一开关电路13直接关闭，可改善由于后级第一开关电路13延时关闭而导致的第二电压v2过补偿的情况。
当然，图6B中以每个第一延时模块121的输出端均耦接有或门为例进行示意，也可以是部分第一延时模块121的输出端耦接有或门、部分第一延时模块121的输出端没有耦接或门。
请继续参考图3，并联的多个第一开关电路13中，每个第一开关电路13被配置为接收第一控制信号Vc，并调控第二电压端V2与电压输出端VOT之间的通断。
示例的，如图4所示，第一延时电路12会输出n个第一控制信号Vc<1:n>。第一个第一开关电路13接收第一级控制信号输出端VC1输出的第一控制信号Vc1，第二个第一开关电路13接收第二级第一控制信号输出端VC2输出的第一控制信号Vc2，第三个第一开关电路13接收第三级第一控制信号输出端VC3输出的第一控制信号Vc3，以此类推。
如图4所示，在一些实施例中，第一开关电路13包括第一晶体管M1，多个第一开关电路13为多个第一晶体管M1<1:n>。
每个第一晶体管M1的控制极与第一延时电路12的第一控制信号输出端耦接，第一晶体管M1的第一极与第二电压端V2耦接，第一晶体管M1的第二极与电压输出端VOT耦接。
示例的，第一比较器11为P型比较器，对应的第一晶体管M1为P型晶体管，在低电平信号的控制下开启，第二电压端V2为电源电压端VDD，在第二电压v2出现下冲时，第一开关电路13构成注入通路，对第二电压v2进行注入补偿，以使电压输出端VOT输出的第二电压v2稳定在阈值范围内。
本申请实施例中，采用数模混合架构的稳压电路10结构，在稳压电路10中设置第一比较器11，可快速响应电压输出端VOT输出的第二电压v2的变化。并通过第一延时电路12逐级控制多个第一开关电路13的导通，构成第二电压端V2到电压输出端VOT的补偿通路，以补偿负载电流瞬间变化所引起的第二电压v2(稳压电路10的输出电压)的大幅变化，保持第二电压v2在阈值范围内。另外，由于对电压输出端VOT注入的电流值可以由多个第一开关电路13调节，因此，第二电压端V2向电压输入端VOT注入的电流值可根据实际应用场景而定，可应对的负载电流变化范围较大。再者，由于第一开关电路13所在的充电通路会从第二电压端V2处抽取较大电流，由于第二电压端V2焊盘绑定(bonding)线的寄生电感的存在，从第二电压端V2抽拉电流会导致第二电压端V2的电源电压产生噪声波动，影响其他模块的正常工作。而本申请实施例中通过将第一开关电路13设置为逐级开启的多个，通过多级控制逻辑，增多抽拉次数，可以减小每次从第二电压端V2抽拉的电流量。而每次抽拉的电流越小，电源电压产生的噪声波动的幅值越小，因此可以改善电源电压波动较大的问题。此外，在多个第一开关电路13分级导通的情况下，对于负载电流变化较小的应用场景，部分第一开关电路13导通即可将第二电压v2补偿至阈值范围内，那么，其余第一开关电路13则无需再开启，有利于减小动态功耗。再者，稳压电路10所包括的电路结构可以均为片内集成结构，可减小稳压电路10的面积，去除引入片外电容所带来的额外成本。
请继续参考图3，在一些实施例中，稳压电路10还包括第一电流源电路14，第一电流源电路14耦接于第二电压端V2与多个第一开关电路13之间。
第一开关电路13直接从第二电压端V2抽拉电流，电流的波动会比较大。而通过在第二电压端V2与第一开关电路13之间设置第一电流源电路14，第一电流源电路14可以提供准确固定的充电电流值，以提高对第二电压v2的补偿精准度，改善了宽电源电压范围内充放电电流变化值较大的问题。
在一些实施例中，第一电流源电路14包括电流镜。
采用电流镜作为电流源，充电电流值较为稳定，可适用于宽电源电压范围的中高频(百兆赫兹级别)芯片(例如MCU芯片)。
示例一种电流镜结构，如图4所示，在一些实施例中，第一电流源电路14包括第二晶体管M2、第一电流源、多个第三晶体管M3<1:n>。
第二晶体管M2的控制极与多个第三晶体管M3<1:n>的控制极和第二晶体管M2的第二极耦接，第二晶体管M2的第一极与第二电压端V2耦接，第二晶体管M2的第二极与第一电流源耦接，第一电流源还与第三电压端V3耦接。
每个第三晶体管M3的第一极与第二电压端V2耦接，每个第三晶体管M3的第二极与一个第一开关电路13(例如第一晶体管M1的第一极)耦接。
在一些实施例中，第二电压端V2和第三电压端V3互为电源电压端VDD和参考地电压端GND。
例如，第二电压端V2为电源电压端VDD，第三电压端V3为参考地电压端GND。
第二晶体管M2和第一电流源所在的电流源支路的电流，镜像到第三晶体管M3所在支路。
请继续参考图3，在一些实施例中，稳压电路10还包括第一反向耦合电路15，第一反向耦合电路15耦接于第一延时电路12与第一电流源电路14之间。
示例的，如图4所示，第一方向耦合电路15耦接于第一延时电路12的第一控制信号输出端与第三晶体管M3的控制极之间。
本申请实施例中，第一反向耦合电路15与第三晶体管M3可以为一一对应的设置关系，也可以是部分第三晶体管M3的控制极耦接有第一反向耦合电路15。
通过设置第一反向耦合电路15，可以稳定第一电流源电路14的静态工作点，补偿第三晶体管M3开关导致的充放电电流波动，减少耦合噪声对充电电流值精度的影响，使第一电流源电路14的电流能够更精确的复制到电压输出端VOT，保持充电电流值的稳定性。同时也可以减小对电源电压的噪声影响。
在一些实施例中，如图4所示，第一反向耦合电路15包括第二反相器INV2和第一电容C1。第二反相器INV2和第一电容C1串联耦接于第一控制信号输出端VC与第三晶体管M3的控制极之间。
示例的，第一电容C1的第一端耦接于第三晶体管M3的控制极，第一电容C1的第二端耦接于反相器INV2的输出端，第二反相器INV2的输入端与第一延时电路12的第一控制信号输出端VC耦接。
当然，本申请实施例对第一方向耦合电路15的结构不作限定，图4中仅为一种示意。
本申请实施例还提供一种稳压电路的驱动方法，包括：
电压输入端VI输入基准电压Vref，低压差线性稳压器LDO接收基准电压Vref，并输出第一电压v1。
电压输出端VOT用于接收第一电压v1并输出第二电压v2。
第一电压端V1输入第一阈值电压Vl，第一比较器11接收第二电压v2和第一阈值电压Vl，并输出第一比较结果Vcp。
第一延时电路12接收第一比较结果Vcp，并输出多个第一控制信号Vc。
多个第一开关电路13分别接收第一控制信号Vc，并调控第二电压端V2与电压输出端VOT之间的通断。
图7为本申请实施例提供的一种稳压电路10的详细结构示意图，图8为本申请实施例提供的一种稳压电路对下冲的瞬态响应效果图。
示例的，如图7所示，以稳压电路10包括三个第一开关电路13为例进行说明。图8示意了当负载电路变大时，稳压电路10对电压输出端VOT输出的第二电压v2下冲时的控制效果。
结合图7和图8所示，当负载电流由小变大，由于稳压电路10还未响应，电压输出端VOT输出的第二电压v2将随之发生突变，产生下冲电压。当第二电压v2低于第一电压端V1输入的第一阈值电压Vl(下冲阈值电压)时，第一比较器11感应到输入正端电压低于输入负端电压，延时t1后，第一比较器11输出低电平的第一比较结果Vcp。并将低电平的第一比较结果Vcp(例如“0”)经过第一级第一延时模块121的输入端输出至第一级第一晶体管M1。该低电平控制第一级第一晶体管M1导通，与第一晶体管M1耦接的第三晶体管M3向电压输出端VOT注入第一电流I1，形成第一充电通路，以补偿第二电压v2下冲(负载电流的增大)，电压输出端VOT的第二电压v2的下冲得到迅速恢复。若负载电流的变化幅度超过第三晶体管M3所能提供的最大电流，第二级第一晶体管M1在经过延时t2后开启，通过与第二级第一晶体管M1耦接的第三晶体管M3继续向电压输出端VOT注入电流I2，形成第二充电通路，与第一充电通路共同为电压输出端VOT注入电流。
当电压输出端VOT的第二电压v2高于第一阈值电压Vl后，第一比较器11感应到输入正端电压高于输入负端电压，从而输出高电平(例如“1”)。该高电平同时控制第一级第一晶体管M1、第二级第一晶体管M1以及第三级第一晶体管M1关闭，第二充电通路与第一充电通路被同时切断，第三级第一晶体管M1所在的路径未开启，继续保持切断，避免电压输出端VOT的第二电压v2过度升高。从而保证第二电压v2在下冲阈值规定的范围之内。
示例二
示例二与示例一的主要不同之处在于，示例一中的稳压电路10包括用于调整下冲的充电模块，而本示例中的稳压电路10包括用于调整过冲的放电模块。
图9为本申请实施例提供的一种稳压电路的拓扑示意图。
如图9所示，稳压电路10包括电压输入端VI、电压输出端VOT、第四电压端V4以及第五电压端V5。
电压输入端VI例如用于接收基准电压Vref，基准电压Vref例如由带隙基准(bandgap，BG)电路提供。电压输出端VOT用于向负载输出稳定的第二电压v2。第四电压端V4例如用于接收第二阈值电压，第二阈值电压用于作为对比电压，以判断稳压电路10是否出现过冲(overshoot)。第五电压端V5例如可以为参考地电压端GND，用于接收参考地电压gnd。
稳压电路10还包括低压差线性稳压器LDO和放电模块，放电模块包括第二比较器21、第二延时电路22以及多个第二开关电路23。
低压差线性稳压器LDO被配置为接收电压输入端VI的基准电压Vref，并输出第一电压v1。低压差线性稳压器LDO的结构例如可以与示例一中的相同，此处不再赘述。
请继续参考图9，第二比较器21被配置为接收第四电压端V4的第二阈值电压Vh和电压输出端VOT输出的第二电压v2，对第二阈值电压Vh和第二电压v2进行比较后，输出第二比较结果Vcn。
当然，本申请实施例对第二阈值电压Vh的取值不作限定。
第二比较器21的结构，可以与示例一中第一比较器11的结构相同，仅是第二比较器21的第一输入端用于接收第二阈值电压Vh，而第一比较器11的第一输入端用于接收第一阈值电压Vl。
第二比较器21用于检测第二电压v2的变化，将第二阈值电压Vh作为可接受范围内的最大参照电压，在第二电压v2大于第二阈值电压Vh的情况下，判定第二电压v2出现过冲，第二比较结果Vcn用于指示第二电压v2出现过冲。在第二电压v2小于第二阈值电压Vh的情况下，判定第二电压v2未出现过冲，第二比较结果Vcn用于指示第二电压v2未出现过冲。
示例的，第二比较器21为n型比较器，在第二电压v2出现过冲的情况下，第二比较结果Vcn为“1”。在第二电压v2未出现过冲的情况下，第二比较结果Vcn为0”。
当然，本申请实施例对第二比较器21的类型不作限定，对第二比较结果Vcn的类型也不作限定，在第二电压v2出现过冲的情况下，第二比较器21输出的第二比较结果Vcn可以控制第二开关电路23开启即可。
请继续参考图9，第二延时电路22被配置为接收第二比较结果Vcn，并输出多个第二控制信号Vc′<1:n>。
在一些实施例中，第二延时电路22的结构与示例一中第一延时电路12的结构相同，可以参考示例一中的相关描述。
图10为本申请实施例提供的一种第二延时电路22的结构示意图。
在另一些实施例中，如图10所示，第二延时电路22包括串联的多个第二延时模块221、多个与门、第二比较结果输入端VCN以及多个第二控制信号输出端(例如VC1′、VC2′、VC3′)。
第二延时电路22中第二延时模块221、第二比较结果输入端VCN以及多个第二控制信号输出端与图6B所示的第一延时电路12中的第一延时模块121、第一比较结果输入端VCP以及多个第一控制信号输入端可以对应相同。主要不同之处在于，将图6B中的或门换成图10中的与门。
与门被配置为接收第二延时模块221的输入端和输出端的信号，并向第二控制信号输出端输出与运算后的信号。
示例的，与门耦接于第二延时模块221与第二控制信号输出端之间。例如，与门包括第一输入端、第二输入端、以及输出端，与门的第一输入端与第二延时模块221的输入端耦接，与门的第二输入端与第二延时模块221的输出端耦接，与门的输出端与第二控制信号输出端耦接。
以图10为例，第一级与门的第一输入端与第一级第二延时模块221的输入端(也就是第一级第二控制信号输出端VC1′)耦接，第一级与门的第二输入端与第一级第二延时模块221的输出端耦接，第一级与门的输出端与第二级第二控制信号输出端VC2′耦接。第二级与门的第一输入端与 第二级第二延时模块221的输入端(也就是第二级第二控制信号输出端VC2′)耦接，第二级与门的第二输入端与第二级第二延时模块221的输出端耦接，第二级与门的输出端与第三级第二控制信号输出端VC3′耦接。
示例的，在电压输出端VOT输出的第二电压v2出现过冲的情况下，第二比较器21输出的第二比较结果Vcn为“1”，第二比较结果Vcn经第二延时模块221后依旧为延时后的“1”，经过与门运算后，输出的依旧为“1”，多个第二开关电路23在多级第二控制信号输出端输出的第二控制信号的控制下依次开启。而在电压输出端VOT输出的第二电压v2未出现过冲的情况下，第二比较结果Vcn为“0”。只要出现“0”，与门运算输出全为“0”，多个第二开关电路23同步关断。
本申请实施例中，通过在第二延时电路22中设置与门，当电压输出端VOT输出的第二电压v2被调节至正常范围后，第二比较器21输出的第二比较结果Vcn将控制所有第二开关电路23直接关闭，可改善由于后级第二开关电路23延时关闭而导致的第二电压v2过补偿的情况。
当然，图10中以每个第二延时模块221的输出端均耦接有与门为例进行示意，也可以是部分第二延时模块221的输出端耦接有与门、部分第二延时模块221的输出端没有耦接与门。
请继续参考图9，并联的多个第二开关电路23中，每个第二开关电路23被配置为接收第二控制信号Vc′，并调控第五电压端V5与电压输出端VOT之间的通断。
本示例中第二开关电路23与示例一中的第一开关电路13的设置位置和原理相同，可以参考示例一中的相关描述。
在一些实施例中，第二开关电路23包括第四晶体管M4，多个第二开关电路23为多个第四晶体管M4<1:n>。
多个第四晶体管M4<1:n>与第二延时电路22的对应关系，与多个第一晶体管M1<1:n>与第一延时电路12的对应关系可以相同。
示例的，第二比较器21为N型比较器，对应的第四晶体管M4为N型晶体管，在高电平信号的控制下开启，第五电压端V5为参考地电压端GND，在第二电压v2出现过冲时，第二开关电路23构成泄放通路，对第二电压v2进行泄放补偿，以使电压输出端VOT输出的第二电压v2稳定在阈值范围内。
本示例的方案，可以理解为将示例一中的第一晶体管M1从P型晶体管换为N型晶体管，将第二电压端V2由电源电压端VDD换为参考地电压端GND。
示例一中的稳压电路10可以对输出电压出现下冲时进行补偿。本示例中，稳压电路10可以对输出电压出现过冲时进行补偿。其他效果与示例一中相同，此处不再赘述。
请继续参考图9，在一些实施例中，稳压电路10还包括第二电流源电路24，第二电流源电路24耦接于第五电压端V5与多个第二开关电路23之间。
第二电流源电路24的结构和原理，可以与示例一中第一电流源电路14的结构和原理相同，此处不再赘述。
示例的，如图9所示，第二电流源电路24包括第五晶体管M5、第二电流源、多个第六晶体管M6<1:n>。
第五晶体管M5的控制极与多个第六晶体管M6<1:n>的控制极和第五晶体管M5的第二极耦接，第五晶体管M5的第一极与第二电压端V2耦接，第五晶体管M5的第二极与第二电流源耦接，第二电流源还与第六电压端V6耦接。
每个第六晶体管M6的第一极与第五电压端V5耦接，每个第六晶体管M6的第二极与一个第二开关电路23(例如第四晶体管M4的第一极)耦接。
在一些实施例中，第五电压端V5和第六电压端V6互为电源电压端VDD和参考地电压端GND。
例如，第六电压端V6为电源电压端VDD，第五电压端V5为参考地电压端GND。
请继续参考图9，在一些实施例中，稳压电路10还包括第二反向耦合电路25，第二反向耦合电路25耦接于第二延时电路22与第二电流源电路24之间。
第二反向耦合电路25的结构和原理可以与示例一中第一反向耦合电路15的结构和原理相同，此处不再赘述。
图11为本申请实施例提供的一种稳压电路10的结构示意图。
当负载电流由大变小，由于稳压电路10还未响应，电压输出端VOT输出的第二电压v2将随之发生突变，产生过冲电压。
当第二电压v2高于第四电压端V4输入的第二阈值电压Vh(过冲阈值电压)时，第二比较器21感应到输入正端电压高于输入负端电压，第二比较器21输出高电平的第二比较结果Vcn。并将高电平的第二比较结果Vcn(例如“1”)经过第一级第二延时模块221的输入端输出至第一级第四晶体管M4。该高电平控制第一级第四晶体管M4导通，与第四晶体管M4耦接的第六晶体管M6为电压输出端VOT提供到地的电流通路，形成第一泄放通路。电压输出端VOT多余的电流可以通过第一泄放通路得到泄放，从而补偿第二电压v2过冲(负载电流的减小)，电压输出端VOT的第二电压v2的过冲得到迅速恢复。若负载电流的变化幅度超过第六晶体管M6所能提供的最大电流，第二级第四晶体管M4在经过延时后开启，通过与第二级第四晶体管M4耦接的第六晶体管M6继续为电压输出端VOT提供到地的电流通路，形成第二泄放通路。第一泄放通路与第二泄放通路共同为电压输出端VOT泄放电流。
当电压输出端VOT的第二电压v2低于第二阈值电压Vh后，第二比较器21感应到输入正端电压低于输入负端电压，从而输出低电平(例如“0”)。该低电平同时控制第一级第四晶体管M4、第二级第四晶体管M4以及第三级第四晶体管M4关闭，第二泄放通路与第一泄放通路被同时切断，第三级第四晶体管M4所在的路径未开启，继续保持切断，避免电压输出端VOT的第二电压v2过度降低。从而保证第二电压v2在过冲阈值规定的范围之内。
在一些实施例中，示例一中第二电压端V2为参考地电压端GND(等同于本示例的第五电压端V5)，第三电压端V3为电源电压端VDD(等同于本示例的第六电压端V6)，第一晶体管M1、第二晶体管M2、第三晶体管M3为N型晶体管，第一比较器11为N型比较器时，稳压电路10也可以补偿过冲。
示例三
示例三提供的稳压电路10同时包括示例一中用于调整下冲的充电模块和用于调整过冲的放电模块。
图12为本申请实施例提供的一种稳压电路的拓扑示意图。
如图12所示，稳压电路10同时包括示例一中的充电模块和示例二中的放电模块，使得稳压电路10输出的第二电压v2在过冲阈值和下冲阈值规定的范围内。
本申请实施例提供的稳压电路10可以集成在同一芯片中，稳压电路10设置在基底(例如硅基底)上，作为本申请实施例提供的低压差线性稳压器芯片。本申请实施例提供的低压差线性稳压器芯片可以是裸芯片，也可以是封装后的芯片。
本申请实施例还提供一种芯片系统，芯片系统包括负载电路和本申请实施例提供的稳压电路10，稳压电路10的电压输出端VOT与负载电路耦接。或者芯片系统包括负载电路和本申请实施例提供的低压差线性稳压器芯片，低压差线性稳压器芯片中的电压输出端VOT与负载电路耦接。
芯片系统例如可以是微控制器(microcontroller unit，MCU)、射频(radio frequency，RF)收发机、高速数字电路(比如，芯片系统SoC)等。
本申请实施例还提供一种电子设备，该电子设备包括上文所提供的任一种稳压电路10或者低压差线性稳压器芯片或者芯片系统，稳压电路10用于为负载电路供电，稳压电路10可以设置在电子设备中的电路板上。
需要说明的是，上文中提供的稳压电路10的相关描述均可引援至该芯片系统和该电子设备中，本申请实施例在此不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种稳压电路，其特征在于，包括：
    电压输入端、电压输出端、第一电压端以及第二电压端；
    低压差线性稳压器，被配置为接收所述电压输入端的基准电压，并输出第一电压；
    所述电压输出端，被配置为接收所述第一电压，并输出第二电压；
    第一比较器，被配置为接收所述第一电压端的第一阈值电压和所述第二电压，并输出第一比较结果；
    第一延时电路，被配置为接收所述第一比较结果，并输出多个第一控制信号；
    并联的多个第一开关电路，每个所述第一开关电路被配置为接收所述第一控制信号，并调控所述第二电压端与所述电压输出端之间的通断。
  2. 根据权利要求1所述的稳压电路，其特征在于，所述稳压电路还包括第一电流源电路；
    所述第一电流源电路耦接于所述第二电压端与所述多个第一开关电路之间。
  3. 根据权利要求2所述的稳压电路，其特征在于，所述稳压电路还包括第一反向耦合电路；
    所述第一反向耦合电路耦接于所述第一延时电路与所述第一电流源电路之间。
  4. 根据权利要求1-3任一项所述的稳压电路，其特征在于，所述第一延时电路包括串联的多个第一延时模块、第一比较结果输入端以及多个第一控制信号输出端；每个所述第一延时模块的输入端和输出端均配置有所述第一控制信号输出端；
    所述第一延时电路被配置为由所述第一比较结果输入端接收所述第一比较结果，由所述第一控制信号输出端输出所述第一控制信号。
  5. 根据权利要求4所述的稳压电路，其特征在于，所述第一延时电路还包括多个或门；所述或门被配置为接收所述第一延时模块的输入端和输出端的信号，并向所述第一控制信号输出端输出或运算后的信号；
    和/或，
    所述第一延时电路还包括多个与门；所述与门被配置为接收所述第一延时模块的输入端和输出端的信号，并向所述第一控制信号输出端输出与运算后的信号。
  6. 根据权利要求1-5任一项所述的稳压电路，其特征在于，所述第一比较器包括级联的多级第一运算放大器。
  7. 根据权利要求6所述的稳压电路，其特征在于，所述第一比较器还包括与所述多级第一运算放大器的输出端耦接的多级第一反相器。
  8. 根据权利要求1-7任一项所述的稳压电路，其特征在于，所述第一开关电路包括第一晶体管；
    所述第一晶体管的控制极与所述第一延时电路耦接，所述第一晶体管的第一极与所述第二电压端耦接，所述第一晶体管的第二极与所述电压输出端耦接。
  9. 根据权利要求8所述的稳压电路，其特征在于，
    所述第一晶体管为P型晶体管，所述第二电压端为电源电压端；
    或者，
    所述第一晶体管为N型晶体管，所述第二电压端为参考地电压端。
  10. 根据权利要求2-9任一项所述的稳压电路，其特征在于，所述第一电流源电路包括电流镜。
  11. 根据权利要求2-10任一项所述的稳压电路，其特征在于，第一电流源电路包括第二晶体管、第一电流源、多个第三晶体管；
    所述第二晶体管的控制极与所述多个第三晶体管的控制极和所述第二晶体管的第二极耦接，所述第二晶体管的第一极与所述第二电压端耦接，所述第二晶体管的第二极与所述第一电流源耦接；
    所述第一电流源还与第三电压端耦接；
    每个所述第三晶体管的第一极与所述第二电压端耦接，每个所述第三晶体管的第二极与一个所述第一开关电路耦接。
  12. 根据权利要求11所述的稳压电路，其特征在于，所述第二电压端和所述第三电压端互为电源电压端和参考地电压端。
  13. 根据权利要求11或12所述的稳压电路，其特征在于，第一反向耦合电路包括第二反相器和第一电容；
    所述第二反相器和所述第一电容串联耦接于第一控制信号输出端与所述第三晶体管的控制极之间。
  14. 根据权利要求1-13任一项所述的稳压电路，其特征在于，所述稳压电路还包括第二比较器、第二延时电路、并联的多个第二开关电路、第四电压端以及第五电压端；
    所述第二比较器被配置为接收所述第四电压端的第二阈值电压和所述第二电压，并输出第二比较结果；
    第二延时电路，被配置为接收所述第二比较结果，并输出多个第二控制信号；
    每个所述第二开关电路被配置为接收所述第二控制信号，并调控所述第五电压端与所述电压输出端之间的通断。
  15. 根据权利要求14所述的稳压电路，其特征在于，所述稳压电路还包括第二电流源电路；
    所述第二电流源电路耦接于所述第五电压端与所述多个第二开关电路之间。
  16. 根据权利要求15所述的稳压电路，其特征在于，所述稳压电路还包括第二反向耦合电路；
    所述第二反向耦合电路耦接于所述第二延时电路与所述第二电流源电路之间。
  17. 一种低压差线性稳压器芯片，其特征在于，包括基底和权利要求1-16任一项所述的稳压电路，所述稳压电路设置在所述基底上。
  18. 一种芯片系统，其特征在于，包括权利要求1-16任一项所述的稳压电路或者权利要求17所述的低压差线性稳压器芯片以及负载电路；稳压电路的电压输出端与所述负载电路耦接。
  19. 一种电子设备，其特征在于，包括权利要求1-16任一项所述的稳压电路或者权利要求17所述的低压差线性稳压器芯片或者权利要求18所述的芯片系统和电路板，稳压电路设置在所述电路板上。
  20. 一种稳压电路的驱动方法，其特征在于，包括：
    电压输入端输入基准电压，低压差线性稳压器接收所述基准电压，并输出第一电压；
    所述电压输出端接收所述第一电压并输出第二电压；
    第一电压端输入第一阈值电压，第一比较器接收所述第一电压和所述第一阈值电压，并输出第一比较结果；
    第一延时电路接收所述第一比较结果，并输出多个第一控制信号；
    多个第一开关电路分别接收所述第一控制信号，并调控第二电压端与电压输出端之间的通断。
PCT/CN2024/088570 2023-04-25 2024-04-18 稳压电路、低压差线性稳压器芯片、芯片系统及电子设备 WO2024222560A1 (zh)

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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101231535A (zh) * 2007-01-25 2008-07-30 美国芯源系统股份有限公司 用于校正模拟低压差线性稳压器过冲和下冲的方法及装置
CN101986502A (zh) * 2009-07-28 2011-03-16 深圳富泰宏精密工业有限公司 手机电池充电电路
CN103606896A (zh) * 2013-11-13 2014-02-26 苏州天擎电子通讯有限公司 一种用于低压差线性稳压器的过流保护装置
CN105988495A (zh) * 2015-02-09 2016-10-05 钜泉光电科技(上海)股份有限公司 一种ldo过冲保护电路
CN209980116U (zh) * 2019-05-10 2020-01-21 深圳市汇春科技股份有限公司 低压差线性稳压器过冲消除电路、下冲消除电路和芯片
KR20210098324A (ko) * 2020-01-31 2021-08-10 한국과학기술원 단일 vco 기반 에지 레이싱 시간 양자화기를 사용하는 디지털 저전압 강하 전압 레귤레이터
CN115480611A (zh) * 2021-06-16 2022-12-16 上海艾为电子技术股份有限公司 一种电源电路、电源系统及电子设备
WO2022267026A1 (zh) * 2021-06-25 2022-12-29 华为技术有限公司 一种用于ldo的辅助电路、芯片系统及设备
CN115542991A (zh) * 2022-09-28 2022-12-30 北京奕斯伟计算技术股份有限公司 低压差线性稳压电路、驱动芯片及其驱动方法、电子设备
CN118192728A (zh) * 2024-02-08 2024-06-14 华为技术有限公司 稳压电路、低压差线性稳压器芯片、芯片系统及电子设备

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101231535A (zh) * 2007-01-25 2008-07-30 美国芯源系统股份有限公司 用于校正模拟低压差线性稳压器过冲和下冲的方法及装置
CN101986502A (zh) * 2009-07-28 2011-03-16 深圳富泰宏精密工业有限公司 手机电池充电电路
CN103606896A (zh) * 2013-11-13 2014-02-26 苏州天擎电子通讯有限公司 一种用于低压差线性稳压器的过流保护装置
CN105988495A (zh) * 2015-02-09 2016-10-05 钜泉光电科技(上海)股份有限公司 一种ldo过冲保护电路
CN209980116U (zh) * 2019-05-10 2020-01-21 深圳市汇春科技股份有限公司 低压差线性稳压器过冲消除电路、下冲消除电路和芯片
KR20210098324A (ko) * 2020-01-31 2021-08-10 한국과학기술원 단일 vco 기반 에지 레이싱 시간 양자화기를 사용하는 디지털 저전압 강하 전압 레귤레이터
CN115480611A (zh) * 2021-06-16 2022-12-16 上海艾为电子技术股份有限公司 一种电源电路、电源系统及电子设备
WO2022267026A1 (zh) * 2021-06-25 2022-12-29 华为技术有限公司 一种用于ldo的辅助电路、芯片系统及设备
CN115542991A (zh) * 2022-09-28 2022-12-30 北京奕斯伟计算技术股份有限公司 低压差线性稳压电路、驱动芯片及其驱动方法、电子设备
CN118192728A (zh) * 2024-02-08 2024-06-14 华为技术有限公司 稳压电路、低压差线性稳压器芯片、芯片系统及电子设备

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