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WO2024212770A1 - Batterie à contact arrière passivé combinée à haute densité de courant et son procédé de préparation - Google Patents

Batterie à contact arrière passivé combinée à haute densité de courant et son procédé de préparation Download PDF

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Publication number
WO2024212770A1
WO2024212770A1 PCT/CN2024/082386 CN2024082386W WO2024212770A1 WO 2024212770 A1 WO2024212770 A1 WO 2024212770A1 CN 2024082386 W CN2024082386 W CN 2024082386W WO 2024212770 A1 WO2024212770 A1 WO 2024212770A1
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layer
silicon
semiconductor
doping
doped region
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PCT/CN2024/082386
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English (en)
Chinese (zh)
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林楷睿
林锦山
张超华
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福建金石能源有限公司
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Publication of WO2024212770A1 publication Critical patent/WO2024212770A1/fr

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    • H01L31/0747—
    • H01L31/02167—
    • H01L31/02168—
    • H01L31/1804—
    • H01L31/1868—
    • H01L31/202—
    • H01L31/208—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present disclosure belongs to the technical field of back contact batteries, and in particular relates to a high current density combined passivation back contact battery and a preparation method thereof.
  • an amorphous silicon or microcrystalline silicon layer is generally deposited on the front of a back-contact heterojunction solar cell and an anti-reflection layer is superimposed to ensure the passivation effect while increasing the transmittance and improving the short-circuit current.
  • the amorphous silicon or microcrystalline silicon layer has a certain light absorption property, which will produce parasitic absorption, affecting the increase of the short-circuit current.
  • the amorphous silicon or microcrystalline silicon layer will have PID (potential induced degradation) or LID (light induced degradation) during long-term outdoor operation.
  • the deposition of amorphous silicon or microcrystalline silicon layer of the back-contact cell is generally deposited by plate-type PECVD, and the plate-type equipment has a high cost, which is not conducive to improving market competitiveness.
  • the applicant of the present disclosure disclosed a combined passivation back contact cell and its preparation method in the early research results CN115207137B, which includes an N-type doped silicon substrate with a light-receiving surface and a back surface, a first semiconductor layer and a second semiconductor layer arranged on the back surface, the second semiconductor layer includes an intrinsic silicon layer and a P-type doped silicon layer arranged in sequence in a direction perpendicular to the back surface and outward, and the first semiconductor layer includes a tunneling oxide layer and an N-type doped silicon crystal layer arranged in sequence in a direction perpendicular to the back surface and outward; an amorphous silicon or microcrystalline silicon layer is deposited on the light-receiving surface (i.e., the front surface) and an anti-reflection layer is superimposed.
  • the combined passivation back contact cell can significantly improve the fill factor FF, photoelectric conversion efficiency, and yield, etc., and the preparation method is relatively simple, can be industrialized, and is conducive to improving mass production efficiency, with obvious market advantages.
  • the purpose of the present invention is to overcome the problems of parasitic absorption and attenuation caused by the back polycrystalline and the amorphous silicon or microcrystalline silicon layer deposited on the front side as well as the defects of high deposition equipment cost in the prior art, and to provide a high current density jointly passivated back contact cell and a preparation method thereof, wherein the jointly passivated back contact cell can achieve good passivation effect without setting an amorphous silicon or microcrystalline silicon layer while ensuring a high current density (that is, taking into account the comprehensive effects of better short-circuit current Isc, open-circuit voltage Voc, fill factor FF, and cell conversion efficiency), while avoiding the above-mentioned parasitic absorption and attenuation problems caused by the back polycrystalline and amorphous silicon or microcrystalline silicon layer as well as the problem of high deposition equipment cost.
  • the present disclosure provides a high current density jointly passivated back contact cell, comprising a silicon substrate having a front side and a back side, a first semiconductor layer and a second semiconductor layer arranged on the back side, and a front passivation layer and an anti-reflection layer arranged on the front side, wherein the first semiconductor layer comprises a tunneling oxide layer and a first doped silicon crystal layer, and the second semiconductor layer comprises an intrinsic silicon layer and a second doped silicon layer; a first heavily doped region is provided on a side of the first doped silicon crystal layer away from the silicon substrate, a second lightly doped region is provided on the front side of the silicon substrate, the second lightly doped region is in contact with the front passivation layer, and a ratio of the surface doping index of the first heavily doped region to the second lightly doped region is 10-40:1, wherein the surface doping index is the ratio of the effective doping concentration of the corresponding doping layer to the thickness of the
  • the side of the first doped silicon crystal layer close to the silicon substrate is an original shallow doping region, and the ratio of the surface doping index of the original shallow doping region to the first heavily doped region and the second shallow doping region is 0.3-2:10-40:1.
  • the ratio of the surface doping index of the second doped silicon layer to that of the original shallowly doped region is 5-30:1.
  • the thickness of the first heavily doped region is 1/10-1/2 of the thickness of the first doped silicon crystal layer.
  • the ratio of the thickness of the second shallowly doped region to the intrinsic silicon layer and the tunneling oxide layer is 5-15:5-10:1.
  • the ratio of the thickness of the second shallowly doped region to the front passivation layer and the anti-reflection layer is 1:0.1-2:5-30.
  • the anti-reflection layer is a phosphorus-doped silicon layer.
  • a ratio of the surface doping index of the anti-reflection layer to that of the second shallowly doped region is 0.2-11:1.
  • the phosphorus-doped silicon layer is phosphorus-doped with at least one selected from silicon oxynitride, silicon nitride, silicon dioxide or silicon oxide.
  • the anti-reflection layer has two or more layers, and along the outward direction from the front side of the silicon substrate, the phosphorus doping concentration of each anti-reflection layer is 1 ⁇ 1018-1 ⁇ 1021cm-3, and the refractive index is 1.2-2.3, 1.4-2.3 can be selected, and the absolute value A of the difference in phosphorus doping concentration and the absolute value B of the difference in refractive index of adjacent anti-reflection layers satisfy a specific relationship: A/B>10.
  • one of the first doped silicon crystal layer and the second doped silicon layer is N-type and the other is P-type, and the doping elements of the second shallowly doped region and the first doped silicon crystal layer are the same.
  • the front side of the silicon substrate is a textured surface or a polished surface
  • the back side is a polished surface
  • the front passivation layer is an oxide layer.
  • the first semiconductor layer is spaced apart on the back side of the silicon substrate, and a second semiconductor opening region is formed at the spaced apart location for setting a portion of the second semiconductor layer; and a portion of the second semiconductor layer is also set in the outward direction of the first semiconductor layer, and a first semiconductor opening region is opened in the middle of the portion of the second semiconductor layer.
  • the width of the first semiconductor opening region Wb is 100-300 ⁇ m
  • the width of the second semiconductor opening region Wa is 300-700 ⁇ m.
  • the combined passivation back contact cell further comprises:
  • a conductive film layer is disposed in the outward direction of the first semiconductor layer and the second semiconductor layer; and an isolation groove is provided on the conductive film layer, and the isolation groove is located between the first semiconductor opening area and the second semiconductor opening area;
  • Metal electrodes are respectively arranged in the first semiconductor opening region and the second semiconductor opening region.
  • the present disclosure provides a method for preparing the combined passivation back contact cell according to the first aspect, comprising the following steps:
  • S1 providing a silicon substrate with a textured surface or a polished surface on the front side and a first semiconductor layer on the back side;
  • the deposition process of the anti-reflection layer in S4 includes: depositing multiple layers of anti-reflection layers in sequence and co-doping them, and the deposition conditions and co-doping conditions are such as to satisfy the required doping concentration, refractive index and thickness of each anti-reflection layer.
  • the preparation method further includes: in S4, before depositing the front passivation layer, pretreatment is performed to repair dangling bonds, and the pretreatment process includes: under plasma conditions, introducing hydrogen, ammonia, or a mixture of one or two of them and an inert gas.
  • the pretreatment conditions include: a pretreatment temperature of 300-500° C. and a pretreatment time of 0.5-1.5 h.
  • the process of providing a silicon substrate having a textured surface or a polished surface on the front side and a first semiconductor layer on the back side in S1 includes:
  • the process of forming a second semiconductor layer on the back side of the silicon substrate obtained in S2 in S3 includes:
  • the preparation method further comprises:
  • the present disclosure provides a front second shallow doping region and a back first heavily doped region with a specific surface doping index ratio and a specific thickness ratio in a joint passivation structure, and cooperates with a first semiconductor layer, a front passivation layer and an anti-reflection layer, so that the front layer structure and the back layer structure of the silicon substrate can cooperate to form a good and appropriate field passivation and chemical passivation effect, so that it is possible to ensure a high current density (that is, taking into account the comprehensive effect of a better short-circuit current Isc, an open-circuit voltage Voc, a fill factor FF, and a battery conversion efficiency) without providing an amorphous silicon or microcrystalline silicon layer, thereby avoiding the above-mentioned parasitic absorption and attenuation problems caused by the back polycrystalline and amorphous silicon or microcrystalline silicon layer and the high cost of the deposition equipment.
  • the ratio of the corresponding surface doping index is too large, the impurities will be too much due to the high doping concentration, affecting the passivation effect; if the ratio of the corresponding surface doping index is too small, the passivation will be less than expected due to the weakening of the field passivation effect, and the passivation level will also be reduced.
  • the ratio of the thickness of the second shallow doped region to the tunnel oxide layer is too large, the front impurity doping will dominate and the back passivation will be unsatisfactory, resulting in serious carrier recombination at the interface and serious damage to the opening voltage and short-circuit current. If it is too small, the potential barrier formed by the tunnel oxide layer will be too large and the carriers will not be able to tunnel out, affecting the conductive performance and further affecting the FF.
  • a specific second shallow doped area on the front side is used to replace the traditional amorphous silicon or microcrystalline layer deposited on the front side to produce a field passivation effect, which can reduce the parasitic absorption of the amorphous silicon or microcrystalline silicon film layer, and there is no amorphous silicon or microcrystalline silicon film layer on the front side, which reduces the probability of PID or LID and increases the stability of the component.
  • the second shallow doped area on the front side can be formed by diffusion, and only tubular equipment is needed to replace the equipment for plate-type deposition of amorphous silicon, reducing equipment investment.
  • the first heavily doped area of the first semiconductor can be formed by secondary diffusion, which further improves the conductivity of the film layer, which is conducive to improving the fill factor and conversion efficiency.
  • a multi-layer anti-reflection layer doped with phosphorus of different concentrations and different refractive indices that meets specific conditions is used on the front side, which is more conducive to enhancing the field passivation effect and improving the passivation level, while increasing the transmittance and being more conducive to improving the short-circuit current.
  • a front passivation layer is deposited after pre-treatment, so that defects at the interface of the second shallowly doped layer are repaired due to the intervention of pre-treatment hydrogen, thereby further improving the passivation level, reducing carrier recombination losses, and being more conducive to improving battery conversion efficiency.
  • FIG1 is a schematic cross-sectional view of a silicon wafer after double-sided polishing and cleaning in Example 1 of the present disclosure
  • FIG2 is a schematic cross-sectional view of a first semiconductor layer formed sequentially on the surface of a silicon wafer in Example 1 of the present disclosure
  • FIG3 is a schematic cross-sectional view of the embodiment 1 of the present disclosure after a mask layer is deposited on the back side of a silicon wafer;
  • FIG. 4 is a schematic cross-sectional view of forming a pyramid texture surface on the front side of a silicon wafer and removing a back side mask layer by texture cleaning in Embodiment 1 of the present disclosure;
  • FIG. 5 is a schematic cross-sectional view after forming a second lightly doped region on the front side and a first heavily doped region on the back side in Embodiment 1 of the present disclosure
  • FIG6 is a schematic cross-sectional view of a portion of the first semiconductor layer on the back side of the silicon wafer after removal of the first semiconductor layer in Embodiment 1 of the present disclosure
  • FIG7 is a schematic cross-sectional view of a second semiconductor layer deposited on the back side of a silicon wafer in Embodiment 1 of the present disclosure
  • FIG8 is a schematic cross-sectional view of the front surface of the silicon wafer after pre-treatment and sequential deposition of a front passivation layer and an anti-reflection layer in Example 1 of the present disclosure;
  • FIG. 9 is a schematic cross-sectional view of forming a first semiconductor opening region on the back side of a silicon wafer in Embodiment 1 of the present disclosure.
  • FIG10 is a schematic cross-sectional view of a conductive film layer deposited on the back side of a silicon wafer in Embodiment 1 of the present disclosure
  • FIG. 11 is a schematic cross-sectional view of forming an isolation trench between a first semiconductor opening region and a second semiconductor opening region on the back side of a silicon wafer in Embodiment 1 of the present disclosure
  • FIG. 12 is a schematic cross-sectional view of the embodiment 1 of the present disclosure after metal electrodes are formed in two semiconductor opening regions on the back side of the silicon wafer.
  • Reference Numerals Silicon wafer, 2. Tunneling oxide layer, 3. N-type doped polysilicon layer, 3.1. Original lightly doped region, 3.2. First heavily doped region, 3.3. Second lightly doped region, 4. Mask layer, 5. Intrinsic amorphous silicon layer, 6. Second doped silicon layer, 7.1. Front passivation layer, 7.2. First anti-reflection layer, 7.3. Second anti-reflection layer, 8. Conductive film layer, 9. Metal electrode.
  • first and second are only configured for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of “plurality” is two or more, unless otherwise clearly and specifically defined.
  • a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium.
  • a first feature being “above”, “above” or “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature.
  • a first feature being “below”, “below” or “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.
  • any values of the ranges disclosed in this article are not limited to the precise ranges or values, and these ranges or values should be understood to include values close to these ranges or values.
  • the endpoint values of each range, the endpoint values of each range and the individual point values, and the individual point values can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article.
  • the terms “optional” and “optional” all mean that they can be included or not (or can be included or not).
  • the direction away from the silicon substrate is referred to as outward, and the direction close to the silicon substrate is referred to as inward.
  • the present disclosure provides a high current density joint passivation back contact cell, comprising a silicon substrate having a front side and a back side, a first semiconductor layer and a second semiconductor layer arranged on the back side, and a front passivation layer and an anti-reflection layer arranged on the front side, wherein the first semiconductor layer comprises a tunneling oxide layer and a first doped silicon crystal layer, and the second semiconductor layer comprises an intrinsic silicon layer and a second doped silicon layer; a first heavily doped region is arranged on a side of the first doped silicon crystal layer away from the silicon substrate, a second lightly doped region is arranged on the front side of the silicon substrate, and the second lightly doped region and the front passivation layer are connected to each other.
  • the first heavily doped region and the second lightly doped region have a surface doping index ratio of 10-40:1, wherein the surface doping index is a ratio of an effective doping concentration of a corresponding doping layer to a thickness of the doping layer; and a ratio of a thickness of the second lightly doped region to a tunneling oxide layer is 2-10:1.
  • the ratio of the surface doping index of the first heavily doped region to the second lightly doped region is 10-30: 1. Under this optional solution, it is more conducive to obtaining a better comprehensive effect of Isc, Voc, FF and battery conversion efficiency.
  • the ratio of the thickness of the second shallowly doped region to the tunnel oxide layer is 4-10: 1. In this optional solution, a better comprehensive effect of Isc, Voc, FF and battery conversion efficiency is obtained.
  • the silicon substrate disclosed in the present invention may be a single crystal silicon wafer or a single cast silicon wafer, optionally a single crystal silicon wafer.
  • the side of the first doped silicon crystal layer close to the silicon substrate is an original lightly doped region
  • the ratio of the surface doping index of the original lightly doped region to the first heavily doped region and the second lightly doped region is 0.3-2:10-40:1, or optionally 0.3-1.5:10-30:1.
  • the surface doping index ratio of the original lightly doped region to the first heavily doped region and the second lightly doped region is appropriate, which can take into account the conductivity without destroying the passivation effect, and is more conducive to improving the comprehensive effects such as battery conversion efficiency.
  • the ratio of the surface doping index of the second doped silicon layer to the original shallow doped region is 5-30: 1, more optionally 10-30: 1.
  • the surface doping index ratio of the original shallow doped region to the second doped silicon layer is appropriate, which can ensure the passivation effect and conductive performance, and is more conducive to the improvement of Isc, Voc and FF as well as the battery conversion efficiency.
  • the thickness of the first heavily doped region is 1/10-1/2 of the thickness of the first doped silicon crystal layer, and more preferably 1/5-1/2.
  • the thickness ratio is appropriate, which can improve the comprehensive conductivity of the film layer and is more conducive to the improvement of Isc, FF and battery conversion efficiency.
  • the thickness ratio of the second shallowly doped region to the intrinsic silicon layer and the tunnel oxide layer is 5-15: 5-10: 1. Under this optional solution, the thickness ratio is appropriate, which can ensure the selectivity of carrier transmission and the stability of passivation, and is more conducive to the improvement of the overall comprehensive effect of Isc, Voc, FF and battery conversion efficiency.
  • the doping concentration and thickness of the original shallow doped region, the first heavily doped region, and the second shallow doped region, as well as the thickness of the tunneling oxide layer and the intrinsic silicon layer only need to satisfy the above-mentioned required proportional relationship.
  • Those skilled in the art can select within the conventional range of the prior art based on the above-mentioned proportional relationship.
  • the thickness of the tunneling oxide layer is 0.5-5nm
  • the thickness of the intrinsic silicon layer is 5-15nm
  • the thickness of the first doped silicon crystal layer is 50-300nm
  • the doping concentration of the original shallow doped region is 1 ⁇ 1019-1 ⁇ 1020cm-3
  • the doping concentration of the second shallow doped region is 1 ⁇ 1018-1 ⁇ 1019cm-3
  • the thickness of the second shallow doped region is 1-15nm.
  • the intrinsic silicon layer may be an intrinsic amorphous silicon layer or a microcrystalline silicon layer.
  • the first doped silicon crystal layer may be a doped polycrystalline silicon layer, and the second doped silicon layer may be a doped amorphous silicon layer or a microcrystalline silicon layer.
  • the ratio of the thickness of the second shallowly doped region to the front passivation layer and the anti-reflection layer is 1:0.1-2:5-30, and more preferably 1:0.2-1:5-20. It is understood that if the anti-reflection layer is multi-layered, the thickness of the anti-reflection layer here refers to the total thickness. Under this optional solution, the thickness ratio is appropriate, which can take into account both the passivation effect and the light transmission performance, and is more conducive to the improvement of the overall comprehensive effect of Isc, Voc, FF and battery conversion efficiency.
  • the anti-reflection layer is a phosphorus-doped silicon layer, which is more conducive to enhancing the field passivation effect and the optical effect of enhancing transmission such as the refractive index.
  • the ratio of the surface doping index of the anti-reflection layer to the second shallowly doped region is 0.2-11:1.
  • each anti-reflection layer satisfies this ratio.
  • the anti-reflection layer is doped so that the second shallowly doped region on the front side of the silicon substrate is superimposed with a phosphorus-doped silicon layer to form a negative fixed charge field with a suitably variable doping concentration, thereby enhancing the battery field passivation effect, and is more conducive to improving the overall passivation level, thereby improving Isc, Voc, FF and battery conversion efficiency.
  • the phosphorus-doped silicon layer is phosphorus-doped with at least one selected from silicon oxynitride, silicon nitride, silicon dioxide or silicon oxide, and more optionally phosphorus-doped silicon oxynitride.
  • the anti-reflection layer is two or more layers.
  • concentration, refractive index and thickness of each anti-reflection layer are the same or different, and can be different.
  • the phosphorus doping concentration of each anti-reflection layer is 1 ⁇ 1018-1 ⁇ 1021cm-3
  • the refractive index is 1.2-2.3, and optionally 1.4-2.3
  • the absolute value A of the difference in phosphorus doping concentration and the absolute value B of the difference in refractive index of adjacent anti-reflection layers satisfy a specific relationship: A/B>10.
  • the passivation effect can be taken into account while improving the transmission performance of photons in the film layer, which is more conducive to the improvement of the comprehensive effects of Isc, Voc, FF and battery conversion efficiency.
  • one of the first doped silicon crystal layer and the second doped silicon layer is N-type and the other is P-type, and the doping elements of the second shallowly doped region and the first doped silicon crystal layer are the same. It can be understood that when the silicon substrate is P-type, the first doped silicon crystal layer is P-type, the second doped silicon layer is N-type, the front side is the second shallowly doped region doped with boron, and the first heavily doped region of the first doped silicon crystal layer is P-type heavily doped.
  • the silicon substrate is N-type
  • the first doped silicon crystal layer is N-type
  • the second doped silicon layer is P-type
  • the front side is the second shallowly doped region doped with phosphorus
  • the first heavily doped region of the first doped silicon crystal layer is N-type heavily doped.
  • the front side of the silicon substrate is a textured surface or a polished surface
  • the back side is a polished surface
  • the front passivation layer is an oxide layer, such as a silicon dioxide layer.
  • the first semiconductor layer is spaced apart on the back side of the silicon substrate, and a second semiconductor opening region is formed at the spaced apart location for setting a portion of the second semiconductor layer; and a portion of the second semiconductor layer is also set in the outward direction of the first semiconductor layer, and a first semiconductor opening region is opened in the middle of the portion of the second semiconductor layer.
  • the width of the first semiconductor opening region Wb is 100-300 ⁇ m
  • the width of the second semiconductor opening region Wa is 300-700 ⁇ m.
  • the combined passivation back contact battery further includes: a conductive film layer, which is arranged in the outward direction of the first semiconductor layer and the second semiconductor layer; and an isolation groove is provided on the conductive film layer, and the isolation groove is located between the first semiconductor opening area and the second semiconductor opening area;
  • Metal electrodes are respectively arranged in the first semiconductor opening region and the second semiconductor opening region.
  • the isolation groove is configured to isolate two semiconductor layers to reduce short circuit or leakage. More optionally, the width Wg of the isolation groove is 50-200 ⁇ m.
  • the conductive film layer can be a transparent conductive film or a composite film layer composed of a transparent conductive film and a metal conductive film.
  • the transparent conductive film can be indium oxide doped with zinc, tin, tungsten, titanium or silicon, or zinc oxide doped with aluminum, boron or gallium.
  • the metal conductive film can be at least one of metal aluminum, metal copper, metal silver, nickel alloy and titanium alloy.
  • the conductive film layer is a composite film layer of tin-doped indium oxide, metal copper and nickel-copper alloy. More optionally, the square resistance of the conductive film layer is less than 0.2 ⁇ / ⁇ .
  • the present disclosure provides a method for preparing the combined passivation back contact cell according to the first aspect, comprising the following steps:
  • S1 providing a silicon substrate with a textured surface or a polished surface on the front side and a first semiconductor layer on the back side;
  • the doping described in S2 is doping by diffusing phosphorus oxychloride.
  • the doping process includes: first entering the first stage of pre-deposition, in which at least one of phosphorus oxychloride, nitrogen and oxygen is introduced to form a phosphorus element and a PSG layer through a chemical reaction.
  • the reaction temperature of the first stage is 750-850°C, and the reaction time is 5-180min; then entering the second stage of heating phosphorus diffusion, which is carried out in an oxygen atmosphere.
  • the PSG layer and the tunneling oxygen are formed.
  • the non-doped oxide layer is formed between the oxide layers, and the temperature of the second stage is 800-900° C. and the time is 10-300 min.
  • the phosphorus diffusion can be carried out in a high-temperature phosphorus diffusion furnace.
  • S4 further includes: doping the anti-reflection layer, for example, phosphorus diffusion doping.
  • the deposition process of the anti-reflection layer described in S4 includes: depositing multiple layers of anti-reflection layers in sequence and co-doping, and the deposition conditions and co-doping conditions are such that the required doping concentration, refractive index and thickness of each layer of the anti-reflection layer are satisfied.
  • the doping of the anti-reflection layer described in S4 is to introduce a gas such as phosphine during the deposition of the anti-reflection layer to perform co-reaction doping (or co-doping), and plasma doping is generally used.
  • the formation process of the anti-reflection layer includes: under plasma conditions, introducing a reaction gas including silane, nitrogen, ammonia and phosphine to perform in-situ doping film formation, adjusting the refractive index of the corresponding film layer by controlling the ratio of ammonia to silane, and controlling the doping amount of the corresponding film layer by adjusting the ratio of phosphine to silane. It is a prior art to adjust the ratio of the reaction gas to control each parameter, and those skilled in the art can select and adjust according to the required parameters, which will not be repeated here.
  • the preparation method further includes: in S4, before depositing the front passivation layer, a pre-treatment is performed to repair dangling bonds.
  • the pre-treatment process includes: under plasma conditions, introducing hydrogen, ammonia, or a mixture of one or two of them with an inert gas. That is, hydrogen, ammonia, a mixture of hydrogen and an inert gas, or a mixture of ammonia and an inert gas can be introduced.
  • hydrogen or ammonia gas molecules decompose H atoms or ions to repair dangling bonds on the silicon surface, which is beneficial to improve the passivation level, thereby more conducive to the improvement of the overall comprehensive effect of Isc, Voc, FF and battery conversion efficiency.
  • the present invention can enhance the passivation level, which is beneficial to improving the Voc of the battery. Since some dangling bonds are repaired, the front passivation layer (oxide layer) can be thinner, so that the thickness ratio of the second shallow doped region to the front passivation layer and the anti-reflection layer is 1:0.1-1:5-20.
  • the pretreatment conditions include: a pretreatment temperature of 300-500° C. and a pretreatment time of 0.5-1.5 h.
  • the process of providing a silicon substrate having a textured surface or a polished surface on the front side and a first semiconductor layer on the back side in S1 includes:
  • the mask layer disclosed in the present invention is configured to protect the first semiconductor layer from being corroded in the strong acid and alkali solution used in texturing.
  • the mask layer can be at least one of silicon nitride, silicon oxynitride, silicon carbide and organic protective ink.
  • the process of forming a second semiconductor layer on the back side of the silicon substrate obtained in S2 in S3 includes:
  • the preparation method further comprises:
  • a high current density combined passivation back contact battery is prepared by the following method:
  • S101 depositing a first semiconductor layer on the back side of the silicon wafer 1, wherein the first semiconductor layer is a tunneling oxide layer 2 and an N-type doped polysilicon layer 3, wherein the tunneling oxide layer 2 has a thickness of 1 nm, the N-type doped polysilicon layer 3 has a thickness of 220 nm, and the doping concentration is 1 ⁇ 1020 cm-3;
  • the mask layer is silicon nitride, the purpose of which is to protect the first semiconductor layer from being corroded by the strong acid or alkali solution;
  • the silicon wafer 1 obtained in the above S102 is textured so that a textured surface with an anti-reflection effect is formed on the front side of the silicon wafer 1, and the mask layer on the back side (first semiconductor layer) is removed to expose the first semiconductor layer.
  • phosphorus diffusion doping is performed on both sides of the silicon wafer 1, so that a second shallow doping region 3.3 is formed on the front side of the silicon wafer 1, and a part of the N-type doped polysilicon layer 3 on the back side of the silicon wafer 1 is heavily doped for a second time to form a first heavily doped region 3.2, and the remaining part is the original shallow doping region 3.1.
  • the phosphorus diffusion doping process is a doping process including: first entering the first stage of pre-deposition, in which phosphorus oxychloride, nitrogen and oxygen are introduced to form a phosphorus element and a PSG layer through chemical reaction, and the reaction temperature of the first stage is 750°C and the reaction time is 15 minutes; then proceeding Enter the second stage of phosphorus diffusion at elevated temperature.
  • the second stage is carried out in an oxygen atmosphere. While the phosphorus diffusion is promoted by the elevated temperature, a non-doped oxide layer is formed between the PSG layer and the tunneling oxide layer.
  • the temperature of the second stage is 900°C and the time is 35 minutes.
  • the phosphorus diffusion doping process makes the thickness of the second shallow doping region 3.3 10nm and the concentration of phosphorus doping 1 ⁇ 1019cm-3; the doping concentration of the N-type doped polysilicon layer 3 is increased from 1 ⁇ 1020cm-3 of the original shallow doping region 3.1 to 1 ⁇ 1021cm-3 of the first heavily doped region 3.2, and the depth of the first heavily doped region 3.2 is 1/4 of the thickness of the original N-type doped polysilicon layer 3.
  • the ratio of the surface doping index of the original shallow doping region 3.1, the first heavily doped region 3.2 and the second shallow doping region 3.3 is 0.6:18:1, wherein the surface doping index is the ratio of the effective doping concentration of the corresponding doping layer to the thickness of the doping layer.
  • a second semiconductor layer is deposited in the second semiconductor opening region, wherein the second semiconductor layer comprises an intrinsic amorphous silicon layer 5 and a second doped silicon layer 6, wherein the second doped silicon layer 6 is an amorphous silicon P layer.
  • the thickness of the second doped silicon layer 6 is 12 nm, and the ratio of the surface doping index of the second doped silicon layer 6 to the original shallow doped region 3.1 is 12.7:1.
  • the ratio of the thickness of the second shallow doped region 3.3 to the intrinsic amorphous silicon layer 5 and the tunneling oxide layer 2 is 10:8:1.
  • the front side is pre-treated and a front passivation layer 7.1 (oxide layer) and two anti-reflection layers are deposited, and the anti-reflection layers are co-doped with phosphorus diffusion, namely a first anti-reflection layer 7.2 and a second anti-reflection layer 7.3 with different thicknesses.
  • the pre-treatment is to introduce a mixture of hydrogen and inert gas argon under plasma conditions, and the pre-treatment time is 0.5 h.
  • the formation process of the anti-reflection layer includes: under plasma conditions, introducing reaction gases including silane, nitrogen, ammonia and phosphine for in-situ doping and film formation, adjusting the refractive index of the film layer by controlling the ratio of ammonia to silane, and controlling the doping amount of the film layer by adjusting the ratio of phosphine to silane, so that the anti-reflection layer is finally formed into two layers of phosphorus-doped silicon nitride oxide layers with different concentrations and different refractive indices, specifically, the phosphorus-doped concentrations from the outside to the inside of the front side are 1 ⁇ 1021cm-3 and 1 ⁇ 1020cm-3 respectively, and the refractive indices from the outside to the inside are 1.46 and 2.0 respectively; the thickness ratio of the second shallow doping region 3.3 to the front passivation layer 7.1 and the total thickness of the two anti-reflection layers is 1:0.1:24.
  • the second semiconductor layer on the back side is removed to expose the first semiconductor layer, thereby forming a first semiconductor opening region Wb with a width of 200 ⁇ m.
  • a conductive film layer 8 is deposited on the back of the battery.
  • the conductive film layer 8 is a composite film layer of tin-doped indium oxide, metallic copper, and nickel-copper alloy, and has a square resistance of 0.1 ⁇ / ⁇ .
  • a gap isolation groove with a width of Wg is formed between the first semiconductor opening region and the second semiconductor opening region.
  • the width of Wg is 150 ⁇ m, mainly for isolating the two semiconductor layers to reduce the generation of short circuit or leakage.
  • gate lines are printed on the back of the battery, and metal electrodes 9 are formed at the first semiconductor opening region and the second semiconductor opening region of the silicon wafer 1 , respectively.
  • Example 1 The method of Example 1 is referred to, except that in S4, the front surface is not pre-treated, but the front passivation layer (oxide layer) and two anti-reflection layers are directly deposited.
  • Example 1 The method of Example 1 is referred to, except that in S4, only one first anti-reflection layer is deposited on the front side, and no second anti-reflection layer is deposited.
  • Example 1 The method of Example 1 is referred to, except that in S2, the doping concentration of the first heavily doped region is adjusted so that the ratio of the surface doping index of the first heavily doped region to that of the second lightly doped region is 16:1, and the conditions for controlling the phosphorus diffusion doping are correspondingly to increase the diffusion gas pressure by 5% and extend the diffusion time by 8%. Under the same diffusion conditions, the diffusion rate on polysilicon is 1.5 times that on bulk silicon (silicon substrate).
  • Example 1 The method of Example 1 is referred to, except that in S2, the doping concentration of the first heavily doped region is adjusted so that the ratio of the surface doping index of the first heavily doped region to that of the second lightly doped region is 35:1, and the conditions for controlling phosphorus diffusion doping are correspondingly to reduce the diffusion gas pressure by 20% and the diffusion temperature by 10%.
  • Example 1 The method of Example 1 is referred to, except that in S101, the thickness of the tunnel oxide layer is adjusted so that the ratio of the thickness of the second shallow doped region to the tunnel oxide layer is 2.2:1.
  • Example 1 The method of Example 1 is followed, except that in S101, the original doping concentration of the N-type doped polysilicon layer is adjusted so that the ratio of the surface doping index of the original lightly doped region and the first heavily doped region is 0.1:1, and the phosphorus diffusion is adjusted accordingly to obtain the first heavily doped region and the second lightly doped region as in Example 1.
  • Example 1 The method of Example 1 is referred to, except that in S101, the thickness of the original lightly doped region in the N-type doped polysilicon layer is adjusted so that the thickness of the first heavily doped region is 1/6 of the thickness of the N-type doped polysilicon layer, and the thickness of the first heavily doped region remains unchanged.
  • Example 1 The method of Example 1 is referred to, except that in S302 , the doping concentration of the second doped silicon layer is adjusted so that the ratio of the surface doping index of the second doped silicon layer to that of the original shallowly doped region is 7.5:1.
  • Example 1 The method of Example 1 is referred to, except that in S4, the total thickness of the two anti-reflection layers is adjusted (the ratio of the thickness of the first anti-reflection layer 7.2 to the second anti-reflection layer 7.3 is 1:2) so that the ratio of the thickness of the second shallowly doped region to the total thickness of the anti-reflection layer is 1:30.
  • Example 1 The method of Example 1 is referred to, except that in S2, no second shallowly doped region is set on the front side, and the N-type doped polysilicon layer on the back side is not heavily doped for the second time to form the first heavily doped region. Instead, a conventional amorphous silicon passivation layer and a silicon nitride anti-reflection layer are used on the front side.
  • Example 1 The method of Example 1 is referred to, except that in S2, phosphorus diffusion doping is performed on the silicon wafer to control the formation of a second shallowly doped region only on the front side of the silicon wafer, and the N-type doped polysilicon layer on the back side of the silicon wafer is not heavily doped for the second time to form a first heavily doped region.
  • Example 1 The method of Example 1 is referred to, except that in S2, the doping concentration of the first heavily doped region is adjusted so that the ratio of the surface doping index of the first heavily doped region to that of the second lightly doped region is 45:1, and the second lightly doped region remains basically unchanged. Accordingly, the conditions for controlling the phosphorus diffusion doping are to increase the diffusion concentration of phosphorus oxychloride by 25% and the diffusion temperature by 20-30%, so that the phosphorus doping amount in the first heavily doped region is much greater than that in the second lightly doped region.
  • Example 1 The method of Example 1 is referred to, except that in S2, the doping concentration of the first heavily doped region is adjusted so that the ratio of the surface doping index of the first heavily doped region to that of the second lightly doped region is 7:1, and the conditions for controlling phosphorus diffusion doping are correspondingly to lower the diffusion temperature and shorten the diffusion time, so that the doping concentration of the first heavily doped region is reduced.
  • Example 1 The method of Example 1 is referred to, except that in S101 the thickness of the tunnel oxide layer 2 is adjusted so that the ratio of the thickness of the second shallow doped region to the thickness of the tunnel oxide layer is 13:1.
  • Examples 1 and 2 it can be seen from Examples 1 and 2 that the use of an additional pre-treatment solution can be more conducive to obtaining a better passivation effect, thereby improving Voc and battery conversion efficiency. It can be seen from Examples 1 and 3, and Examples 10-11 that the use of the anti-reflection layer solution under the optional specific structural parameters of the present disclosure can be more conducive to reducing the reflectivity of the front side and improving the comprehensive transmittance of photons in the film layer, thereby obtaining a high current density and improving Isc, Voc, FF and battery conversion efficiency.
  • the high current density jointly passivated back contact cell disclosed in the present invention can make the front layer structure and the back layer structure of the silicon substrate cooperate to form a good and appropriate field passivation and chemical passivation effect by arranging a second lightly doped region on the front side and a first heavily doped region on the back side with a specific surface doping index ratio and a specific thickness ratio in the joint passivation structure, in conjunction with the first semiconductor layer, the front passivation layer and the anti-reflection layer.

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Abstract

La présente divulgation appartient au domaine technique des batteries à contact arrière et se rapporte, en particulier, à une batterie à contact arrière passivé combinée à haute densité de courant et à son procédé de préparation. La batterie à contact arrière passivé combinée à haute densité de courant comprend : un substrat de silicium, qui comporte une face avant et une face arrière ; une première couche semi-conductrice et une seconde couche semi-conductrice, qui sont disposées sur la face arrière ; et une couche de passivation avant et une couche antireflet, qui sont disposées sur la face avant, la première couche semi-conductrice comprenant une couche d'oxyde à effet tunnel et une première couche de cristaux de silicium dopé, et la seconde couche semi-conductrice comprenant une couche de silicium intrinsèque et une seconde couche de silicium dopé. Le côté de la première couche de cristaux de silicium dopé qui est éloigné du substrat de silicium est pourvu d'une première région fortement dopée et la face avant du substrat de silicium est pourvue d'une seconde région légèrement dopée, qui est en contact avec la couche de passivation avant ; et le rapport d'un indice de dopage de face de la première région fortement dopée à celle de la seconde région légèrement dopée est 10-40:1 et le rapport de l'épaisseur de la seconde région légèrement dopée à celle de la couche d'oxyde à effet tunnel est 2-10:1. La présente divulgation peut assurer une densité de courant élevée, sans fournir de couche de silicium amorphe ou de couche de silicium microcristallin.
PCT/CN2024/082386 2023-04-10 2024-03-19 Batterie à contact arrière passivé combinée à haute densité de courant et son procédé de préparation WO2024212770A1 (fr)

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