WO2024209821A1

WO2024209821A1 - Light detection device and electronic apparatus

Info

Publication number: WO2024209821A1
Application number: PCT/JP2024/006372
Authority: WO
Inventors: 二朗井上
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2023-04-04
Filing date: 2024-02-21
Publication date: 2024-10-10
Also published as: JP2024147979A

Abstract

The present invention further improves the reliability of a light detection device and an electronic apparatus. This light detection device is provided with: a semiconductor layer having a first surface and a second surface that are positioned on mutually opposite sides in the thickness direction; a multilayer wiring layer provided on the first surface side of the semiconductor layer; a warpage suppression film provided on the opposite side of the multilayer wiring layer from the semiconductor layer side; and a dug-in part overlapping the warpage suppression film in a plan view and extending from the second surface side of the semiconductor layer to the multilayer wiring layer. The warpage suppression film has an opening in an overlapping region overlapping the dug-in part in the plan view.

Description

Photodetection device and electronic device

This technology (the technology disclosed herein) relates to photodetection devices and electronic devices, and in particular to technology that is effective when applied to photodetection devices and electronic devices that have a warp suppression layer.

In photodetection devices such as solid-state imaging devices and distance measuring devices, a stacked type is known in which semiconductor layers in which elements are formed are stacked in multiple stages. This stacked type photodetection device is capable of transferring signals at high speed. Patent Document 1 discloses a solid-state imaging device with a two-stage stacked structure in which two semiconductor layers are stacked. Patent Document 1 also discloses a technology in which a warpage suppression film (warpage correction layer) is provided to suppress warpage of a semiconductor substrate including a semiconductor layer and a multilayer wiring layer.

JP 2012-204810 A

In a stacked-type photodetector, a multi-layer wiring layer is provided on one side of a semiconductor layer, and a warpage suppression film is provided on the side of the multi-layer wiring layer opposite the semiconductor layer. The multi-layer wiring layer provided on one side of the semiconductor layer and an external electrode pad provided on the side opposite the semiconductor layer are electrically connected through a recessed portion provided in the semiconductor layer.

In this type of configuration, stress is concentrated locally around the recessed portion, which can cause deformation in the portion of the multilayer wiring layer that overlaps the recessed portion of the semiconductor layer in a planar view. This deformation of the multilayer wiring layer can cause warping or peeling in the wiring and internal electrode pads of the multilayer wiring layer, reducing reliability, and therefore leaving room for improvement.

The purpose of this technology is to provide technology that can further improve the reliability of photodetection devices and electronic devices.

(1) A photodetector according to an aspect of the present disclosure,
a semiconductor layer having a first surface and a second surface positioned opposite to each other in a thickness direction;
a multilayer wiring layer provided on the first surface side of the semiconductor layer;
a warpage suppression film provided on a side of the multilayer wiring layer opposite to the semiconductor layer;
a recessed portion that overlaps the warp suppression film in a plan view and extends from the second surface side of the semiconductor layer to the multilayer wiring layer;
It is equipped with:
The warp suppression film has an opening in an overlapping region that overlaps with the recessed portion in a plan view.

(2) A photodetector according to another aspect of the present technology,
a first semiconductor layer having a first surface and a second surface opposite to each other and including a photoelectric conversion unit configured to perform photoelectric conversion on light incident from the second surface side;
a first multilayer wiring layer provided on the first surface side of the first semiconductor layer;
a second semiconductor layer having a third surface and a fourth surface opposite to each other and including a transistor;
a second multilayer wiring layer provided on the third surface side of the second semiconductor layer so as to overlap the first multilayer wiring layer;
a warpage suppression film provided between the first multilayer wiring layer and the second multilayer wiring layer;
a recessed portion that overlaps the warp suppression film in a plan view and extends from the fourth surface side of the second semiconductor layer to the second multilayer wiring layer;
It is equipped with:
The warp suppression film has an opening in an overlapping region that overlaps with the recessed portion in a plan view.

(3) An electronic device according to another aspect of the present technology includes:
The photodetector;
an optical lens that forms an image of image light from a subject on an imaging surface of the detection device;
a signal processing circuit for processing a signal output from the photodetector;
It is equipped with:

1 is a chip layout diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. 1 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. 1 is an equivalent circuit diagram showing a configuration example of a pixel and a pixel circuit according to a first embodiment of the present technology. 2 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along the a1-a1 cutting line in FIG. 1. FIG. 5 is a development view of FIG. FIG. 6 is an enlarged development view of a part of FIG. 5 . 1 is a plan view showing a schematic planar pattern in an overlapping region of a warpage suppressing film; 11 is a longitudinal sectional view showing a schematic diagram of deformation in an overlapping region where a bonding interface between a first laminate and a second laminate overlaps a recessed portion in a conventional solid-state imaging device. FIG. 4 is a longitudinal sectional view showing a schematic diagram of deformation in an overlapping region where a bonding interface between a first stack and a second stack overlaps with a recessed portion in the solid-state imaging device of the first embodiment; FIG. FIG. 1 is a plan view illustrating a modified example 1-1 of the first embodiment of the present technology. FIG. 11 is a plan view illustrating a modified example 1-2 of the first embodiment of the present technology. FIG. 11 is a longitudinal sectional view illustrating a modified example 1-3 of the first embodiment of the present technology. FIG. 11 is a longitudinal sectional view illustrating a modified example 1-4 of the first embodiment of the present technology. 11 is a chip layout diagram showing a configuration example of a solid-state imaging device according to a second embodiment of the present technology. FIG. 15 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along the a14-a14 cutting line in FIG. 14. FIG. 13 is a diagram showing a configuration example of an electronic device according to a third embodiment of the present technology.

Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings.
In the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined by taking into consideration the following description.

Of course, there are parts in which the dimensional relationships and ratios differ between the drawings. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also exist.

Furthermore, the following embodiments are merely examples of devices and methods for embodying the technical ideas of the present technology, and are not intended to limit the configuration to those described below. In other words, the technical ideas of the present technology can be modified in various ways within the technical scope described in the claims.

Furthermore, the definitions of up and down and other directions in the following explanation are merely for the convenience of explanation and do not limit the technical ideas of this technology. For example, if an object is rotated 90 degrees and observed, up and down are converted into left and right and read, and of course, if it is rotated 180 degrees and observed, up and down are read inverted.

In the following embodiment, of the three mutually orthogonal directions in space, a first direction and a second direction that are mutually orthogonal in the same plane are defined as the X direction and the Y direction, respectively, and a third direction that is orthogonal to each of the first and second directions is defined as the Z direction. In the following embodiment, the thickness direction of the semiconductor layers 30 and 70 described later will be described as the Z direction.

First Embodiment
In the first embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated complementary metal oxide semiconductor (CMOS) image sensor as a photodetector will be described.
In addition, in this first embodiment, a warpage suppressing film (warpage adjusting film) provided between the first stack (first semiconductor substrate) and the second stack (second semiconductor substrate) will be described.

<Overall configuration of solid-state imaging device>
First, the overall configuration of the solid-state imaging device 1A will be described.
As shown in Fig. 1, the solid-state imaging device 1A according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plane. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be regarded as the solid-state imaging device 1A. As shown in Fig. 16, this solid-state imaging device 1A (101) takes in image light (incident light 106) from a subject via an optical lens 102, converts the amount of incident light 106 formed on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

As shown in FIG. 1, the semiconductor chip 2 on which the solid-state imaging device 1A is mounted has a square sensor pixel array section 2A provided in the center in a two-dimensional plane including mutually orthogonal X and Y directions, and a peripheral section 2B provided outside the sensor pixel array section 2A so as to surround the sensor pixel array section 2A. In the manufacturing process, the semiconductor chip 2 is formed by dicing a semiconductor wafer including first and second semiconductor layers 30, 70 described below into chip formation regions. Therefore, the configuration of the solid-state imaging device 1A described below is generally the same in the wafer state before the semiconductor wafer is diced. In other words, this technology can be applied in the state of a semiconductor chip and in the state of a semiconductor wafer.

The sensor pixel array section 2A is a light receiving surface that receives light focused by, for example, an optical lens (optical system) 102 shown in FIG. 16. In the sensor pixel array section 2A, a plurality of sensor pixels (pixels) 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the sensor pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are mutually orthogonal on the two-dimensional plane.

As shown in FIG. 1, a plurality of external electrode pads 94 are arranged on the peripheral portion 2B. As shown in FIG. 4, the plurality of external electrode pads 94 are provided on the side of the semiconductor chip 2 opposite the sensor pixel array portion 2A. As shown in FIG. 1, each of the plurality of external electrode pads 94 is arranged, for example, along each of the four sides of the semiconductor chip 2 in a two-dimensional plane. Each of the plurality of external electrode pads 94 functions as an input/output terminal that electrically connects the semiconductor chip 2 to an external device.

<Logic circuit>
The semiconductor chip 2 includes a logic circuit 13 shown in Fig. 2. As shown in Fig. 2, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, an n-channel conductivity type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a p-channel conductivity type MOSFET.

The vertical drive circuit 4 shown in FIG. 2 is composed of, for example, a shift register. The vertical drive circuit 4 sequentially selects the desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the sensor pixels 3, and drives each sensor pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each sensor pixel 3 in the sensor pixel array section 2A vertically row by row, and supplies pixel signals from the sensor pixels 3 based on signal charges generated by the photoelectric conversion section (photoelectric conversion element) of each sensor pixel 3 according to the amount of light received to the column signal processing circuit 5 via the vertical signal line 11.

The column signal processing circuit 5 shown in FIG. 2 is arranged, for example, for each column of sensor pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of sensor pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-to-Digital) conversion to remove pixel-specific fixed pattern noise.

The horizontal drive circuit 6 shown in FIG. 2 is composed of, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn, and causing each of the column signal processing circuits 5 to output a pixel signal that has been subjected to signal processing to the horizontal signal line 12.

The output circuit 7 shown in FIG. 2 processes and outputs pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12. For example, the signal processing may include buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

The control circuit 8 shown in FIG. 2 generates clock signals and control signals that serve as the basis for the operation of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

<Circuit configuration of sensor pixel>
3, each of the sensor pixels 3 includes a photoelectric conversion region 32 and a pixel circuit (readout circuit) 15. The photoelectric conversion region 32 includes a photoelectric conversion unit 34, a transfer transistor TR as a pixel transistor, and a floating diffusion region FD as a charge holding unit. The pixel circuit 15 is electrically connected to the floating diffusion region FD of the photoelectric conversion region 32.

In the first embodiment, as an example, a circuit configuration is used in which one pixel circuit 15 is assigned to one sensor pixel 3, but the present invention is not limited to this first embodiment. For example, a circuit configuration may be used in which one pixel circuit 15 is shared by multiple sensor pixels 3. Specifically, a circuit configuration may be used in which one pixel circuit 15 is shared by one sensor pixel group (photoelectric conversion group) in which four sensor pixels 3 are arranged in a 2×2 arrangement, two in each of the X and Y directions, as one unit. Also, a circuit configuration may be used in which one pixel circuit 15 is shared by one sensor pixel group (photoelectric conversion group) in which two sensor pixels 3 are arranged as one unit. Also, a circuit configuration may be used in which one pixel circuit 15 is shared by one sensor pixel group (photoelectric conversion group) in which four or more sensor pixels 3 are arranged as one unit.

The photoelectric conversion unit 34 shown in FIG. 3 is composed of, for example, a pn junction type photodiode (PD) and generates a signal charge according to the amount of light received. The cathode side of the photoelectric conversion unit 34 is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (for example, ground).

The transfer transistor TR shown in FIG. 3 transfers the signal charge photoelectrically converted by the photoelectric conversion unit 34 to the floating diffusion region FD. The source region of the transfer transistor RT is electrically connected to the cathode side of the photoelectric conversion unit 34, and the drain region of the transfer transistor TR is electrically connected to the floating diffusion region FD. The gate electrode of the transfer transistor TR is electrically connected to the transfer transistor drive line of the pixel drive line 10 shown in FIG. 2.

The floating diffusion region FD shown in FIG. 3 temporarily holds (accumulates) the signal charge transferred from the photoelectric conversion unit 24 via the transfer transistor TR.

The photoelectric conversion region 32, which includes the photoelectric conversion unit 34, the transfer transistor TR, and the floating diffusion region FD, is mounted for each sensor pixel 3 on the first semiconductor layer 30 shown in Figures 4 and 5.

The pixel circuit 15 shown in FIG. 3 reads out the signal charge held in the floating diffusion region FD and outputs a pixel signal based on the read-out signal charge. The pixel circuit 15 includes, but is not limited to, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST as pixel transistors Q. Each of these pixel transistors (AMP, SEL, RST) and the transfer transistor TR described above is configured as a field effect transistor, for example, a MOSFET having a gate insulating film made of a silicon oxide (SiO ₂ ) film, a gate electrode, and a pair of main electrode regions functioning as a source region and a drain region. In addition, these transistors may be MISFETs (Metal Insulator Semiconductor FETs) whose gate insulating film is made of a silicon nitride (Si ₃ N ₄ ) film or a laminated film such as a silicon nitride film and a silicon oxide film.

The amplifier transistor AMP shown in FIG. 3 has a source region electrically connected to the drain region of the select transistor SEL, and a drain region electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. The gate electrode of the amplifier transistor AMP is electrically connected to the floating diffusion region FD and the source region of the reset transistor RST.

The selection transistor SEL shown in FIG. 3 has a source electrically connected to the vertical signal line 11 (VSL) and a drain region electrically connected to the source region of the amplification transistor AMP. The gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line of the pixel drive line 10 shown in FIG. 2.

The reset transistor RST shown in FIG. 3 has a source region electrically connected to the floating diffusion region FD and the gate electrode of the amplifier transistor AMP, and a drain region electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line of the pixel drive line 10 shown in FIG. 2.

When the transfer transistor TRG shown in FIG. 3 is turned on, the transfer transistor TR transfers the signal charge generated in the photoelectric conversion unit 24 to the floating diffusion region FD.

When the reset transistor RST shown in FIG. 3 is turned on, it resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 15.

The amplification transistor AMP shown in FIG. 3 generates a pixel signal whose voltage corresponds to the level of the signal charge held in the floating diffusion region FD. The amplification transistor AMP constitutes a source-follower type amplifier, and outputs a pixel signal whose voltage corresponds to the level of the signal charge generated in the photoelectric conversion unit 24. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion region FD, and outputs a voltage corresponding to that potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

Now, referring to FIG. 3, during operation of the solid-state imaging device 1A according to the first embodiment, the signal charge generated in the photoelectric conversion unit 34 of the sensor pixel 3 is held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the sensor pixel 3. The signal charge held in the floating diffusion region FD is read out by the pixel circuit 15 and applied to the gate electrode of the amplification transistor AMP of the pixel circuit 15. A horizontal line selection control signal is provided to the gate electrode of the selection transistor SEL of the pixel circuit 15 from the vertical shift register. Then, by setting the selection control signal to a high (H) level, the selection transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD amplified by the amplification transistor AMP flows in the vertical signal line 11. Also, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 15 to a high (H) level, the reset transistor RST becomes conductive, and the signal charge accumulated in the floating diffusion region FD is reset.

<Other pixel circuits>
The selection transistor SEL may be omitted if necessary. In the case where the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL).

A switching transistor may also be provided between the reset transistor RST and the gate electrode of the floating diffusion region FD and the amplifier transistor AMP. The switching transistor controls charge retention by the floating diffusion region FD and adjusts the voltage multiplication factor according to the potential amplified by the amplifier transistor AMP.

The switching transistor is also used to switch the conversion efficiency. In general, the pixel signal is small when shooting in a dark place. Based on Q=CV, when performing charge-voltage conversion, if the FD capacitance C (floating diffusion capacitance C) of the charge holding section (floating diffusion region FD) is large, the voltage V when converted to voltage by the amplification transistor AMP will be small. On the other hand, in a bright place, the pixel signal is large, so if the FD capacitance C of the charge holding section is not large, the charge holding section cannot receive the charge of the photoelectric conversion section 24 (photodiode PD). Furthermore, the FD capacitance C of the charge holding section needs to be large so that the voltage V when converted to voltage by the amplification transistor AMP does not become too large (in other words, to become small). In light of this, when the switching transistor is turned on, the gate capacitance of the switching transistor increases, so the overall FD capacitance C becomes large. On the other hand, when the switching transistor is turned off, the overall FD capacitance C becomes small. In this way, by switching the switching transistor on/off, the FD capacitance C can be made variable and the conversion efficiency can be switched.

<<Specific configuration of solid-state imaging device>>
Next, a specific configuration of the solid-state imaging device 1A will be described with reference to FIGS.
As shown in Fig. 4 and Fig. 5, the solid-state imaging device 1A (semiconductor chip 2) includes a first stack (first semiconductor substrate) 20 and a second stack (second semiconductor substrate) 60. The first stack 20 and the second stack 60 are bonded with their bonding surfaces 20a, 60a facing each other. The first stack 20 is equipped with a sensor pixel array section 2A, a control circuit 8, a pixel circuit 15, and the like. The second stack 60 is equipped with a logic circuit 13 including a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and the like.

<First laminate>
As shown in Figures 4 and 5, the first stack 20 includes a first semiconductor layer 30 having a first surface S1 and a second surface S2 located opposite each other in the thickness direction (Z direction), a first multilayer wiring layer 40 provided on the first surface S1 side of the first semiconductor layer 30, and a light-collecting layer 50 provided on the second surface S2 side of the first semiconductor layer 30.
The first laminate 20 also includes a warp suppression film 46 and a bonding layer 47 laminated in sequence from the first multilayer wiring layer 40 side on the side of the first multilayer wiring layer 40 opposite the first semiconductor layer 30 side.
Here, the first surface S1 of the first semiconductor layer 30 may be referred to as the main surface or element formation surface, and the second surface S2 may be referred to as the back surface. As will be described in detail later, the solid-state imaging device 1A according to the first embodiment photoelectrically converts incident light incident from the second surface S2 side of the first semiconductor layer 30 in a photoelectric conversion unit 34 (photodiode PD) provided in a photoelectric conversion region 32 of the first semiconductor layer 30. Therefore, in this first embodiment, the second surface S2 of the first semiconductor layer 30 may be referred to as the light incident surface.

<Second laminate>
The second stack 60 comprises a second semiconductor layer 70 having a third surface S3 and a fourth surface S4 located opposite each other in the thickness direction (Z direction), and a second multilayer wiring layer 80 provided on the third surface S3 side of the second semiconductor layer 70.
The second laminate 60 also includes a recessed portion 91 extending from the third surface S3 side of the second semiconductor layer 70 to the second multilayer wiring layer 80, an isolation insulating film 92 provided along the inner wall of the recessed portion 91, and a contact electrode 93 provided along the inner wall of the recessed portion 91 via the isolation insulating film 92 and electrically connected to the second multilayer wiring layer 80.
The second laminate 60 also includes an external electrode pad 94 provided on the fourth surface S4 side of the second semiconductor layer 70 and electrically connected to the contact electrode 93, and a solder resist film 95 provided in the recessed portion 91 via the contact electrode 93.
The second laminate 60 also includes a warp suppression film 86 and a bonding layer 87 laminated in sequence from the second multilayer wiring layer 80 side on the side of the second multilayer wiring layer 80 opposite the second semiconductor layer 70 side.
Here, the third surface S3 of the second semiconductor layer 70 may be called the main surface or element formation surface, and the fourth surface S4 may be called the back surface.

<Light-collecting layer>
4 and 5, the light collecting layer 50 is provided on the second surface S2 side of the first semiconductor layer 30. The light collecting layer 50 has a layered structure in which, for example, but not limited to, a planarizing film 51, an optical filter 53, and an on-chip lens 54 are layered in this order from the second surface S2 side of the first semiconductor layer 30.

The planarization film 51 is provided on the second surface S2 side of the semiconductor layer 30 so as to cover the second surface S2 of the semiconductor layer 30, and planarizes the second surface S2 side of the semiconductor layer 30.

The optical filter 53 and the microlens 54 are provided for each sensor pixel 3. The optical filter 53 separates the color of the incident light that is incident from the light incident surface side (second surface S2 side) of the semiconductor chip 2. The microlens 54 collects the irradiated light and allows the collected light to efficiently enter the sensor pixel 3 (photoelectric conversion region 32).

<First Semiconductor Layer>
As shown in Figures 4 and 5, the first semiconductor layer 30 is provided on the third surface S3 side of the second semiconductor layer 70 via a first multi-layer wiring layer 40 and a second multi-layer wiring layer 80. The first semiconductor layer 30 is made of, for example, a p-type single crystal silicon substrate. In the first semiconductor layer 30, a photoelectric conversion region 32 is provided for each sensor pixel 3 in a region overlapping with the sensor pixel array section 2A in a planar view. Although not shown, the photoelectric conversion region 32 is partitioned by a separation region provided in the first semiconductor layer 30. Note that the number of sensor pixels 3 is not limited to that shown in Figures 4 and 5.

The photoelectric conversion region 32, although not shown, has, for example, a p-type well region and an n-type semiconductor region (photoelectric conversion section) embedded inside this well region. The photoelectric conversion element PD shown in FIG. 3 is configured in the photoelectric conversion region 32 including the well region and photoelectric conversion section of the first semiconductor layer 30. In addition, the photoelectric conversion region 32 is provided with, but is not limited to, a floating diffusion region (charge holding section) FD made of, for example, an n-type semiconductor region, and a transfer transistor TR.

As shown in Figures 4 and 5, a plurality of transistors Q1 are provided on the first surface S1 of the first semiconductor layer 30. The transistors Q1 are provided in the semiconductor layer 30 directly below the peripheral portion 2B in a plan view. The transistors Q1 are, for example, transistors that constitute the control circuit 8 shown in Figure 2. For example, a MOS transistor (Metal Oxide Semiconductor Field Effect Transistor) is used as the transistor Q1. Figures 4 and 5 show four transistors Q1 as an example representing the plurality of transistors.

<First multi-layer wiring layer>
4 and 5, the first multilayer wiring layer 40 is laminated on the first surface S1 side of the first semiconductor layer 30. The first multilayer wiring layer 40 has a multilayer wiring structure in which wiring layers 42 are laminated in multiple stages via an interlayer insulating film 41. Although not limited thereto, for example, a three-layer wiring structure in which the wiring layers 42 are laminated in three stages is illustrated in FIGS.

The interlayer insulating film 41 is made of, for example, a silicon oxide film. The wiring layer 42 is made of, for example, a copper (Cu) film or a Cu alloy film mainly composed of Cu, or an aluminum (Al) film or an Al alloy film mainly composed of Al.

<Second Semiconductor Layer>
4 and 5, the second semiconductor layer 70 is provided on the first surface S1 side of the first semiconductor layer 30 via a second multilayer wiring layer 80 and a first multilayer wiring layer 40. The second semiconductor layer 70 is made of, for example, a p-type single crystal silicon substrate.

As shown in Figures 4 and 5, a plurality of transistors Q2 are provided on the third surface S3 of the semiconductor layer 70. The transistors Q2 are, for example, pixel transistors constituting the pixel circuit (readout circuit) 15 shown in Figure 3, or transistors constituting the logic circuit 13 shown in Figure 2. For example, a MOS transistor is used as the transistor Q2. Seven transistors Q2 are shown in Figures 4 and 5 to represent the plurality of transistors.

<Second Multilayer Wiring Layer>
4 and 5, the second multilayer wiring layer 80 is laminated on the third surface S3 side of the second semiconductor layer 70. The second multilayer wiring layer 80 has a multilayer wiring structure in which wiring layers 82 are laminated in multiple stages via an interlayer insulating film 81. Although not limited thereto, for example, a three-layer wiring structure in which the wiring layers 82 are laminated in three stages is illustrated in FIG.

As shown in Figures 4 and 5, the second multilayer wiring layer 80 has an internal electrode pad 83. This internal electrode pad 83 is provided in the first wiring layer 82, counting from the second semiconductor layer 70 side of the second multilayer wiring layer 80.

The interlayer insulating film 81 is made of, for example, a silicon oxide film. The wiring layer 82 is made of, for example, a copper (Cu) film or a Cu alloy film mainly composed of Cu, or an aluminum (Al) film or an Al alloy film mainly composed of Al.

<Dug-in portion, isolation insulating film>
4 and 5, the dug portion 91 is provided at a position overlapping with the internal electrode pad 83 of the second multilayer wiring layer 80 in a plan view. The dug portion 91 extends from the third surface S3 side of the second semiconductor layer 70 across the second multilayer wiring layer 80, and reaches the internal electrode pad 83. The dug portion 91 can be formed by selectively etching the second semiconductor layer 70 and the second multilayer wiring layer 80 using well-known photolithography and anisotropic dry etching techniques.
As shown in FIG. 1, a plurality of recessed portions 91 are provided in the peripheral portion 2B, for example, but not limited to this.

As shown in Figures 4 and 5, the isolation insulating film 92 is provided along the side surface of the inner wall of the recessed portion 91, and is also provided on the fourth surface S4 side of the second semiconductor layer 70. In other words, the isolation insulating film 92 is provided across the side surface of the inner wall of the recessed portion 91 and the fourth surface S4 of the second semiconductor layer 70. The isolation insulating film 92 is composed of, for example, a silicon oxide film.

<Contact electrodes, external electrode pads>
4 and 5, the contact electrode 93 is provided along the inner wall of the dug portion 91 via the isolation insulating film 92, and is provided along the internal electrode pad 83 located at the bottom of the dug portion 91. The contact electrode 93 is electrically and mechanically connected to the internal electrode pad 83. The contact electrode 93 is electrically insulated and separated from the second semiconductor layer 70 via the isolation insulating film 92.

4 and 5, the external electrode pad 94 is provided on the fourth surface S4 side of the second semiconductor layer 70 via an isolation insulating film 92. The external electrode pad 94 is integrally formed with the contact electrode 93 and is electrically connected to the contact electrode 93. That is, the external electrode pad 94 is electrically connected to the internal electrode pad 83 of the second multilayer wiring layer 80 through the recessed portion 91. The recessed portion 91 is a through hole for electrically connecting the internal electrode pad 83 on the third surface S3 side of the second semiconductor layer 70 and the external electrode pad 94 on the fourth surface S4 side of the second semiconductor layer 70, and penetrates the second semiconductor layer 70 along the thickness direction (Z direction) of the second semiconductor layer 70. The external electrode pad 94 is electrically insulated and separated from the second semiconductor layer 70 via the isolation insulating film 92.

The contact electrode 93 and the external electrode pad 94 can be formed, for example, by forming a conductive film on the fourth surface S4 side of the second semiconductor layer 70 and inside the recessed portion 91 with a thickness that conforms to the inner wall of the recessed portion 91, and then patterning this conductive film using well-known photolithography and anisotropic dry etching techniques. The conductive film can be, for example, a laminate film of a titanium (Ti) film as a barrier film and a copper (Cu) film as a seed film.

As shown in FIG. 1, multiple external electrode pads 94 are provided, for example but not limited to, on the peripheral portion 2B of the semiconductor chip 2.

<Solder resist>
4 and 5 , the solder resist film 95 is provided inside the dug portion 91 so as to cover the contact electrode 93, and is also provided so as to cover the fourth surface S4 of the second semiconductor layer 70. In other words, the solder resist film 95 is provided across the inside of the dug portion 91 and the fourth surface S4 of the second semiconductor layer 70.

The solder resist film 95 is provided mainly for the purpose of protecting the contact electrodes 93 and the wiring (not shown) provided on the fourth surface S4 side of the second semiconductor layer 70. The solder resist film 95 is provided with an opening 95a that exposes the external electrode pad 94.

Connecting members such as solder bumps and bonding wires are connected to the external electrode pads 94 through the openings 95a in the solder resist film 95.

<Bonding layer>
5, the bonding layer 47 on the first laminate 20 side is provided on the bonding surface of the first multilayer wiring layer 40 opposite the first semiconductor layer 30 side so as to cover the warpage suppression film 46. The bonding layer 46 is provided across the sensor pixel array portion 2A and the peripheral portion 2B of the semiconductor chip 2, and is provided over a wide range so as to cover the entire area of the first multilayer wiring layer 40 in a plan view.

As shown in FIG. 5, the bonding layer 87 on the second laminate 20 side is provided on the bonding surface side of the second multilayer wiring layer 80 opposite the second semiconductor layer 70 side so as to cover the warpage suppression film 86. The bonding layer 87 is provided across the sensor pixel array portion 2A and the peripheral portion 2B of the semiconductor chip 2, and is provided over a wide area so as to cover the entire area of the second multilayer wiring layer 80 in a plan view.

The surface of the bonding layer 47 functions as the bonding surface 20a of the first laminate 20. Meanwhile, the bonding layer 87 functions as the bonding surface 60a of the second laminate 60. The bonding layer 47 of the first laminate 20 and the bonding layer 87 of the second laminate 60 are bonded together. By bonding the bonding layer 47 of the first laminate 20 and the bonding layer 87 of the second laminate 60 together, the first laminate 20 and the second laminate 60 are bonded together in line in their respective thickness directions (Z direction).

<Plasma bonding method>
The bonding layer 47 of the first stack 20 and the bonding layer 87 of the second stack 60 can be bonded together by, for example, a plasma bonding method.

In the plasma bonding method, silanol groups are formed by irradiating a silicon oxide layer serving as a bonding layer with plasma. The surfaces on which the silanol groups have been formed are then placed face to face, and the laminates are pressed together and bonded by van der Waals force. After that, to further increase the adhesion at the bonding interface, a heat treatment of, for example, 400°C/60 min is applied, causing a dehydration condensation reaction between the silanol groups. By controlling the bonding layer of the laminates in this way at the molecular level, it becomes possible to bond the laminates together. The bonding between the bonding layer 47 of the first laminate 20 and the bonding layer 87 of the second laminate 60 is performed in the form of a wafer.

<Warpage suppression film>
5, the warp suppression film 46 is provided on the side of the first multilayer wiring layer 40 opposite to the first semiconductor layer 30, and is covered with a bonding layer 47. The warp suppression film 46 is provided across the sensor pixel array portion 2A and the peripheral portion 2B of the semiconductor chip 2, and is provided over a wide range so as to cover the entire area of the first multilayer wiring layer 40 in a plan view.

The warpage suppression film 46 is for suppressing warpage of the first stack 20 in which the first semiconductor layer 30 and the first multilayer wiring layer 40, which have different thermal expansion coefficients, are stacked, and is made of a layer having an internal stress opposite to the warpage of the first stack 20. As the warpage suppression film 46, for example, a material that can be formed by a plasma CVD method, such as SiN, SiO2, SiOC, SiC, SiCN, FSG, FTEOS, or a material that can be formed by a coating method, such as an induction material or SOG, can be used. In particular, the film formed by the plasma CVD method can control the internal stress by changing conditions such as the pressure in the chamber of the CVD device and the RF power. Therefore, it is preferable to use a material film formed by the plasma CVD method as the warpage suppression film 46. In this first embodiment, for example, a silicon nitride (SiN) film is used as the warpage suppression film 46.
5, the warp suppression film 86 is provided on the side of the second multilayer wiring layer 80 opposite to the second semiconductor layer 70, and is covered with a bonding layer 87. The warp suppression film 86 is provided across the pixel array portion 2A and the peripheral portion 2B of the semiconductor chip 2, and is provided over a wide range so as to cover the entire area of the second multilayer wiring layer 80 in a plan view.

The warpage suppression film 86 is intended to suppress warpage of the second laminate 60, which is a laminate of the second semiconductor layer 70 and the second multilayer wiring layer 80, which have different thermal expansion coefficients, and is made of a layer that has an internal stress opposite to the warpage of the second laminate 60. The warpage suppression film 46 can be configured in the same way as the warpage suppression film 46 that suppresses warpage of the first laminate 20 described above. In this first embodiment, for example, a silicon nitride (SiN) film is used as the warpage suppression film 86.

As shown in FIG. 5 , each of the warp suppression films 86 and 46 is provided between the second multilayer wiring layer 80 and the first multilayer wiring layer 40 .
That is, the solid-state imaging device 1A of the first embodiment comprises a second semiconductor layer 70, a second multilayer wiring layer 80 provided on the third surface S3 side of the second semiconductor layer 70, a warp suppression film 86 provided on the side of the second multilayer wiring layer 80 opposite the second semiconductor layer 70 side, and a recessed portion 91 that overlaps the warp suppression film 86 in a planar view and extends from the fourth surface S4 side of the second semiconductor layer 70 to the second multilayer wiring layer.

<Overlapping area of warpage suppression film>
6 and 7, the warpage suppression film 86 has openings _86a1 in an overlapping region 86a that overlaps with the recessed portion 91 in a plan view. The openings _86a1 are, for example, scattered, but are not limited to this. The overlapping region 86a of the warpage suppression film 86 has a lattice-like planar pattern including the openings _86a1 .
₆ , the opening 86a1 penetrates, for example, the warp suppression film 86. The planar shape of the opening _86a1 is, for example, rectangular, as shown in FIG.

6, like the warp suppression film 86 described above, the warp suppression film 46 also has openings _46a1 in an overlapping region 46a that overlaps with the recessed portion 91 in a plan view. Like the openings _86a1 of the warp suppression film 86 described above, the openings 46a1 are also, for example, scattered. The overlapping region 46a of the warp suppression film 46 also has a lattice-like planar pattern including the openings _46a1 . Like the openings _86a1 described above, the openings _46a1 of the warp suppression film 46 also penetrate the warp suppression film 46, for example, and the planar shape of the openings _46a1 is, for example, rectangular _.

<<Main Effects of the First Embodiment>>
Next, main effects of the first embodiment will be described with reference to FIGS.

FIG. 8 is a vertical cross-sectional view showing a schematic diagram of deformation in an overlapping region where the bonding interface R1 between the first laminate 20 and the second laminate 60 overlaps with the recessed portion 91 in a conventional solid-state imaging device.

FIG. 9 is a vertical cross-sectional view showing a schematic diagram of deformation in the overlapping region where the bonding interface between the first laminate 20 and the second laminate 60 overlaps with the recessed portion 91 in the solid-state imaging device 1A of this first embodiment.

As shown in FIG. 8, in a conventional solid-state imaging device, the overlapping regions 86a, 46a of the warp suppression films 86, 46 that overlap the recessed portion 91 of the second semiconductor layer 70 in a planar view are in a solid film state. That is, the entire recessed portion 91 is covered with the warp suppression films 86, 46 in a planar view. For this reason, stress caused by the warp suppression films 86, 46 is locally concentrated around the recessed portion 91, and deformation (warp amount A) may occur in the portion of the second multilayer wiring layer 80 that overlaps the recessed portion 91 of the second semiconductor layer 70 in a planar view. This deformation of the second multilayer wiring layer 80 causes warping or peeling in the wiring of the second multilayer wiring layer 80 and the internal electrode pads 83, which reduces reliability.

In contrast, as shown in Figure 9, in the solid-state imaging device 1A of the first embodiment, the warp suppression films 86, 46 have openings 86a1, 46a1 in overlapping regions 86a, 46a that overlap the recessed portion 91 of the second semiconductor layer 70 in a planar view. This makes it possible to mitigate the phenomenon in which stress caused by the warp suppression films 86, 46 is locally concentrated around the recessed portion 91, and to suppress deformation (warpage amount A) in the portion of the second multilayer wiring layer 80 that overlaps the recessed portion 91 of the second semiconductor layer 70 in a planar view.

This makes it possible to suppress warping and peeling of the wiring of the multilayer wiring layer 80 and the internal electrode pads 83 caused by local deformation of the second multilayer wiring layer 80.

Therefore, the solid-state imaging device 1A according to the first embodiment can achieve even greater reliability.

<Modification of the First Embodiment>
<Modification 1-1>
In the above-described first embodiment, as shown in FIG. 7, the openings _86a.sub.1 , _46a.sub.1 of the warp suppression films 86, 46 have a rectangular planar shape. However, the present technology is not limited to the rectangular shape.
For example, as shown in Fig. 10, the openings 86a1, _46a1 of the warp suppression films ₈₆ , 46 may be formed to have a circular planar shape, with the same effects as those of the first embodiment being obtained in this case as well.

<Modification 1-2>
In the above-described first embodiment, as shown in FIG. 7 , the openings 86a1, _46a1 are dotted in the overlapping regions 86a, 46a of the warp suppression films 86, 46. However, the present technology is not limited to the configuration in which the _openings _86a1 , _46a1 are dotted in the overlapping regions 86a, 46a of the warp suppression films 86, 46.
11, the openings 86a ₁ and 46a ₁ may be provided in the overlapping regions 86a and 46a of the warp suppression films 86 and 46. In this case as well, the same effects as those of the first embodiment can be obtained.

<Modification 1-3>
In the above-described first embodiment, as shown in FIG. 4 , a recessed portion 91 is provided in the second semiconductor layer 70 that overlaps with the peripheral portion 2B of the semiconductor chip 2 in a planar view, and openings _86a1 , 46a1 are provided in overlapping regions 86a, 46a of the warp suppression films 86, ₄₆ that overlap with this recessed portion 91. However, the present technology is not limited to the recessed portion 91 of the above-described first embodiment.

12, for example, a recessed portion 91 may be provided in the second semiconductor layer 70 that overlaps with the sensor pixel array portion 2A of the semiconductor chip 2 in a plan view, and openings 86a1, 46a1 may be provided in overlapping regions 86a, 46a of the warp suppression films ₈₆ , ₄₆ that overlap with this recessed portion 91. In this case as well, the same effects as those of the first embodiment described above can be obtained.

In addition, deformation (warping amount A) in the portion of the second multilayer wiring layer 80 that overlaps with the recessed portion 91 directly below the sensor pixel array portion 2A in a plan view can be suppressed, thereby suppressing warping of the internal electrode pad 83. This makes it possible to suppress the phenomenon in which light reflected by the internal electrode pad 83 is condensed due to the warping of the internal electrode pad 83 and appears as a projected image, thereby achieving even higher image quality.

<Modification 1-4>
In the above-described first embodiment, as shown in Fig. 6, the warp suppression films 86, 46 are provided on both the first laminate 20 and the second laminate 60, but the present technology can also be applied to a case where a warp suppression film is provided on at least one of the first laminate 20 and the second laminate 60. Fig. 13 illustrates a case where the warp suppression film 86 is provided on the second laminate 60 of the first laminate 20 and the second laminate 60. An opening 86a is provided in an overlapping region 86a of the warp suppression film 86 on the second laminate 60 side.

Second Embodiment
As shown in Figures 14 and 15, the solid-state imaging device 1B of the second embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1A of the first embodiment described above, with the configurations of the external electrode pads and the recessed portions being different.

That is, as shown in FIG. 5, in the first embodiment described above, a recessed portion 91 is provided in the second laminate 60 so as to overlap with the internal electrode pad 83 of the second multilayer wiring layer 80 in a plan view, and openings _86a1 , _46a1 are provided in overlapping regions 86a, 46a of the warp suppression films 86, 46 that overlap with this recessed portion 91.

In contrast, as shown in FIG. 15 , in the second embodiment, a recessed portion 56 is provided in the first laminate 20 so as to overlap with the internal electrode pad 44 of the first multilayer wiring layer 40 in a plan view, and openings 46 b ₁ , 86 b ₁ are provided in the overlapping regions 46 b , 86 b of the warp suppression films 46 , 86 that overlap with this recessed portion 56.

As shown in FIG. 15, the internal electrode pads 44 are provided, for example, in the third wiring layer 42 counting from the first semiconductor layer 30 side of the first multilayer wiring layer 40. The internal electrode pads 44 function as input/output terminals that electrically connect the semiconductor chip 2 to an external device. Then, connecting members such as solder bumps and bonding wires are connected to the internal electrode pads 44.

The recessed portion 56 extends from the second surface S2 of the first semiconductor layer 30 toward the first multilayer wiring layer 40, and reaches the internal electrode pad 44 of the first multilayer wiring layer 40. That is, the recessed portion 56 penetrates the first semiconductor layer 30 across the first surface S1 and the second surface S2, and reaches the internal electrode pad 44 of the first multilayer wiring layer 40.

The overlapping regions 46b, 86b of the warp suppressing films 46, 86 have, for example, a lattice-like planar pattern including openings 46b ₁ , 86b ₁ , similar to the overlapping regions 46a, 86b of the above-described first embodiment.

The solid-state imaging device 1B according to the second embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above.

Third Embodiment
<Applications to electronic devices>
The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

FIG. 16 is a diagram showing the schematic configuration of an electronic device (e.g., a camera) according to a third embodiment of the present technology.

As shown in FIG. 16, electronic device 100 includes solid-state imaging device 101, optical lens 102, shutter device 103, drive circuit 104, and signal processing circuit 105. This electronic device 100 shows an embodiment in which solid-state imaging device 1A according to the first embodiment of the present technology is used as solid-state imaging device 101 in an electronic device (e.g., a camera).

The optical lens 102 focuses image light (incident light 106) from the subject on the imaging surface of the solid-state imaging device 101. This causes signal charge to accumulate in the solid-state imaging device 101 for a certain period of time. The shutter device 103 controls the light irradiation period and light blocking period for the solid-state imaging device 101. The drive circuit 104 supplies a drive signal that controls the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The drive signal (timing signal) supplied from the drive circuit 104 transfers charge in the solid-state imaging device 101. The signal processing circuit 105 performs various signal processing on the signal (pixel signal (image signal)) output from the solid-state imaging device 101. The video signal that has undergone signal processing is stored in a storage medium such as a memory, or output to a monitor.

This configuration further improves the reliability of the solid-state imaging device 101, and therefore the reliability of the electronic device 100 of the third embodiment can also be further improved.

The electronic device 100 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the solid-state imaging device may be applied to an imaging device such as a camera module for mobile devices such as mobile phones and tablet terminals.

Furthermore, this technology can be applied to all light detection devices, including not only the solid-state imaging devices that serve as image sensors described above, but also distance measurement sensors known as ToF (Time of Flight) sensors that measure distance. Distance measurement sensors emit light toward an object, detect the light that is reflected back from the surface of the object, and calculate the distance to the object based on the flight time from when the light is emitted to when the reflected light is received. The pixel transistors described above can also be used in these distance measurement sensors.

The present technology may be configured as follows.
(1)
a semiconductor layer having a first surface and a second surface positioned opposite to each other in a thickness direction;
a multilayer wiring layer provided on the first surface side of the semiconductor layer;
a warpage suppression film provided on a side of the multilayer wiring layer opposite to the semiconductor layer;
a recessed portion that overlaps the warp suppression film in a plan view and extends from the second surface side of the semiconductor layer to the multilayer wiring layer;
Equipped with
the warp suppression film has an opening in an overlapping region that overlaps with the recessed portion in a plan view.
(2)
The light detection device according to (1) above, wherein the openings are scattered.
(3)
The light-detecting device according to (1) or (2) above, wherein the overlapping region of the warp suppression film has a lattice-like planar pattern including the openings.
(4)
a contact electrode provided in the recess and connected to a wiring layer of the multilayer wiring layer;
The photodetector according to any one of (1) to (3) above, further comprising an external electrode pad provided on the second surface side of the semiconductor layer and connected to the contact electrode.
(5)
the multilayer wiring layer has an internal electrode pad between the warp suppression film and the recessed portion,
The photodetector according to claim 4, wherein the contact electrode is connected to the internal electrode pad.
(6)
the contact electrode is provided along an inner wall of the recessed portion,
The photodetector according to claim 4, wherein a solder resist film is provided in the recess so as to cover the contact electrode.
(7)
The photodetector according to any one of (1) to (6), wherein the warpage suppression film suppresses warpage of the semiconductor layer and the wiring layer.
(8)
a first semiconductor layer having a first surface and a second surface opposite to each other and including a photoelectric conversion portion configured to photoelectrically convert light incident from the second surface side;
a first multilayer wiring layer provided on the first surface side of the first semiconductor layer;
a second semiconductor layer having a third surface and a fourth surface opposite to each other and including a transistor;
a second multilayer wiring layer provided on the third surface side of the second semiconductor layer so as to overlap the first multilayer wiring layer;
a warpage suppression film provided between the first multilayer wiring layer and the second multilayer wiring layer;
a recessed portion that overlaps the warp suppression film in a plan view and extends from the fourth surface side of the second semiconductor layer to the second multilayer wiring layer;
Equipped with
the warp suppression film has an opening in an overlapping region that overlaps with the recessed portion in a plan view.
(9)
The light detection device according to (8) above, wherein the openings are scattered.
(10)
The light-detecting device according to (8) or (9) above, wherein the overlapping region of the warp suppression film has a lattice-like planar pattern including the openings.
(11)
a contact electrode provided in the recess and connected to a wiring layer of the multilayer wiring layer;
The photodetector according to claim 8, further comprising an external electrode pad provided on the second surface side of the semiconductor layer and connected to the contact electrode.
(12)
the second multilayer wiring layer has an internal electrode pad between the warp suppression film and the recessed portion,
The photodetector according to (11) above, wherein the contact electrode is connected to the internal electrode pad.
(13)
the contact electrode is provided along an inner wall of the recessed portion,
The photodetector according to (11) above, wherein a solder resist film is provided in the recessed portion so as to cover the contact electrode.
(14)
The photodetector according to any one of (8) to (12) above, wherein the warpage suppression film suppresses warpage of the semiconductor layer and the wiring layer.
(15)
A photodetector;
an optical lens that forms an image of image light from a subject on an imaging surface of the light detection device;
a signal processing circuit for processing a signal output from the photodetector;
Equipped with
The light detection device includes:
a semiconductor layer having a first surface and a second surface positioned opposite to each other in a thickness direction;
a multilayer wiring layer provided on the first surface side of the semiconductor layer;
a warpage suppression film provided on a side of the multilayer wiring layer opposite to the semiconductor layer;
a recessed portion that overlaps the warp suppression film in a plan view and extends from the second surface side of the semiconductor layer to the multilayer wiring layer;
Equipped with
The warp suppression film has an opening in an overlapping region that overlaps with the recessed portion in a plan view.

The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve the same effect as the intended purpose of the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective features disclosed.

1A Solid-state imaging device 2 Semiconductor chip 2A Sensor pixel array section 2B Peripheral section 3 Sensor pixel 4 Vertical drive circuit 5 Column signal processing circuit 6 Horizontal drive circuit 7 Output circuit 8 Control circuit 10 Pixel drive line 11 Vertical signal line 12 Horizontal signal line 13 Logic circuit 15 Pixel circuit 20 First stacked body 30 First semiconductor layer 32 Photoelectric conversion region 34 Photoelectric conversion section 40 First multilayer wiring layer 41 Interlayer insulating film 42 Wiring layer 44 Internal electrode pad 46 Warp suppression film 46a, 46b Overlapping region 46a ₁ , 46b ₁ Opening 47 Bonding layer 50 Light collecting layer 51 Planarization film 53 Optical filter 54 On-chip lens 56 Carved section 60 Second stacked body 70 Second semiconductor layer 80 Second multilayer wiring layer 81 Interlayer insulating film 82 Wiring layer 83 Internal electrode pad 86 Warp suppressing film 86a, 86b Overlapping region _86a1 , _86b1 Opening 87 Bonding layer 91 Engraved portion 92 Isolation insulating film 93 Contact electrode 94 External electrode pad 95 Solder resist film 100 Electronic device 101 Solid-state imaging device 102 Optical system (optical lens)
103: shutter device 104: drive circuit 105: signal processing circuit S1: first surface S2: second surface S3: third surface S4: fourth surface Q1, Q2: transistor

Claims

a semiconductor layer having a first surface and a second surface positioned opposite to each other in a thickness direction;
a multilayer wiring layer provided on the first surface side of the semiconductor layer;
a warpage suppression film provided on a side of the multilayer wiring layer opposite to the semiconductor layer;
a recessed portion that overlaps the warp suppression film in a plan view and extends from the second surface side of the semiconductor layer to the multilayer wiring layer;
Equipped with
the warp suppression film has an opening in an overlapping region that overlaps with the recessed portion in a plan view.
The optical detection device of claim 1, wherein the openings are scattered.
The photodetector according to claim 1, wherein the overlapping region of the warpage suppression film is a lattice-like planar pattern including the openings.
a contact electrode provided in the recess and connected to a wiring layer of the multilayer wiring layer;
2. The photodetector according to claim 1, further comprising an external electrode pad provided on the second surface side of the semiconductor layer and connected to the contact electrode.
the multilayer wiring layer has an internal electrode pad between the warp suppression film and the recessed portion,
The photodetector according to claim 4 , wherein the contact electrode is connected to the internal electrode pad.
the contact electrode is provided along an inner wall of the recessed portion,
5. The light-detecting device according to claim 4, wherein a solder resist film is provided in the recess so as to cover the contact electrode.
The photodetector according to claim 1, wherein the warpage suppression film suppresses warpage of the semiconductor layer and the wiring layer.
a first semiconductor layer having a first surface and a second surface opposite to each other and including a photoelectric conversion portion configured to photoelectrically convert light incident from the second surface side;
a first multilayer wiring layer provided on the first surface side of the first semiconductor layer;
a second semiconductor layer having a third surface and a fourth surface opposite to each other and including a transistor;
a second multilayer wiring layer provided on the third surface side of the second semiconductor layer so as to overlap the first multilayer wiring layer;
a warpage suppression film provided between the first multilayer wiring layer and the second multilayer wiring layer;
a recessed portion that overlaps the warp suppression film in a plan view and extends from the fourth surface side of the second semiconductor layer to the second multilayer wiring layer;
Equipped with
the warp suppression film has an opening in an overlapping region that overlaps with the recessed portion in a plan view.
The optical detection device of claim 8, wherein the openings are scattered.
The photodetector according to claim 8, wherein the overlapping region of the warpage suppression film is a lattice-like planar pattern including the openings.
a contact electrode provided in the recess and connected to a wiring layer of the multilayer wiring layer;
9. The photodetector according to claim 8, further comprising an external electrode pad provided on the second surface side of the semiconductor layer and connected to the contact electrode.
the second multilayer wiring layer has an internal electrode pad between the warp suppression film and the recessed portion,
The photodetector according to claim 11 , wherein the contact electrode is connected to the internal electrode pad.
the contact electrode is provided along an inner wall of the recessed portion,
12. The light-detecting device according to claim 11, wherein a solder resist film is provided in the recess so as to cover the contact electrode.
The photodetector according to claim 8, wherein the warpage suppression film suppresses warpage of the semiconductor layer and the wiring layer.
A photodetector;
an optical lens that forms an image of image light from a subject on an imaging surface of the light detection device;
a signal processing circuit for processing a signal output from the photodetector;
Equipped with
The light detection device includes:
a semiconductor layer having a first surface and a second surface positioned opposite to each other in a thickness direction;
a multilayer wiring layer provided on the first surface side of the semiconductor layer;
a warpage suppression film provided on a side of the multilayer wiring layer opposite to the semiconductor layer;
a recessed portion that overlaps the warp suppression film in a plan view and extends from the second surface side of the semiconductor layer to the multilayer wiring layer;
Equipped with
the warp suppression film has an opening in an overlapping region that overlaps with the recessed portion in a plan view.