WO2024205573A1

WO2024205573A1 - Anti-jam adaptive notch filter for pulse radar signals

Info

Publication number: WO2024205573A1
Application number: PCT/US2023/016512
Authority: WO
Inventors: Steven W. Cox; Richard J. Lavery; JR. Peter Ladubec
Original assignee: Bae Systems Information And Electronic Systems Integration Inc.
Priority date: 2023-03-28
Filing date: 2023-03-28
Publication date: 2024-10-03

Abstract

Techniques are provided for adaptive anti-jam filtering in radio frequency (RF) based systems. In one example, an adaptive filter includes a filtering device coupled between an input port and an output port, and including at least one infinite impulse response (IIR) filter, the filtering device configured to receive an input signal via the input port and to provide a filtered output signal at the output port, and an analysis module coupled between the input port and the filtering device, the analysis module being configured to receive the input signal via the input port, to determine a set of filter coefficients for the at least one IIR filter based on detecting at least one interfering signal in the input signal, and to provide the a set of filter coefficients to the filtering device to update a configuration of the at least one IIR filter using the a set of filter coefficients.

Description

ANTI- JAM ADAPTIVE NOTCH FILTER FOR PULSE RADAR SIGNALS

FIELD OF DISCLOSURE

[0001] The present disclosure relates to detection and suppression of interfering signals in a radio frequency (RF) environment, and more particularly to a notch fdtering system for detecting and suppressing such interfering signals.

BACKGROUND

[0002] An RF -based system can be adversely affected by the RF environment in which it operates. For example, self-interference, RF jamming, RF cyber-attacks, or the presence of other interfering signals, whether intentional or un-intentional, can degrade system performance.

SUMMARY

[0003] Aspects and examples are directed to an adaptive notch fdter for excising certain frequencies corresponding to interfering signals in an RF system.

[0004] According to one example, an adaptive filter comprising a filtering device coupled between an input port and an output port, and including at least one infinite impulse response (HR) filter, the filtering device being configured to receive a pulsed input signal via the input port and to provide a filtered output signal at the output port; and an analysis module coupled between the input port and the filtering device and configured to receive the pulsed input signal via the input port. The analysis module includes a fast Fourier transform (FFT) module configured to perform an FFT on the input signal and to provide FFT output data representative of frequency content of the input signal, a memory configured to store the FFT output data, at least one processor coupled to the memory, and at least one processor-readable medium storing program instructions executable by the at least one processor to control the adaptive filter to analyze the FFT output data to detect at least one interfering signal in the pulsed input signal, determine an estimated frequency of the at least one interfering signal, and determine a set of fdter coefficients for the at least one IIR filter based on the estimated frequency of the at least one interfering signal using a look-up table, wherein the analysis module is configured to provide the a set of filter coefficients to the filtering device to dynamically update a configuration of the at least one IIR filter using the a set of filter coefficients.

[0005] Another example is directed to a computer program product including one or more non- transitory machine-readable mediums encoded with instructions that when executed by one or more processors cause a process to be carried out for filtering an input signal to suppress one or more interfering signals. The process comprises applying a fast Fourier transform (FFT) to the input signal to produce FFT output data that includes a plurality of frequency bins, detecting one or more magnitude peaks in the FFT output data corresponding to the one or more interfering signals, applying a frequency bin interpolation process to the FFT output data to determine estimated frequencies of the one or more interfering signals, based on the estimated frequencies, determining a plurality of filter coefficients, and configuring a filtering device using the plurality of filter coefficients, wherein configuring the filtering device includes adjusting a center notch frequency and a bandwidth of at least one infinite impulse response (HR) filter in the filtering device.

[0006] According to another example, a radio frequency (RF) Identification Friend or Foe (IFF) system comprises an input port configured to receive an IFF input signal, the IFF input signal including at least one of an IFF transponder waveform or an IFF interrogator waveform, an output port, and an adaptive filter coupled between the input port and the output port and configured to provide a filtered signal at the output port. The adaptive filter includes a plurality of infinite impulse response (IIR) filters coupled in series between the input port and the output port and configured to filter the IFF input signal to produce the filtered signal at the output port, and an analysis module configured to determine a set of corresponding filter coefficients for each of the plurality of HR filters based on detecting one or more interfering signals in the IFF input signal, and to provide the set of corresponding filter coefficients to the plurality of HR filters to update a center notch frequency and a bandwidth of the plurality of HR filters using the set of corresponding filter coefficients. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the figures,

[0008] FIG. l is a block diagram of an RF system including an anti-jam filter in accordance with aspects of the present disclosure;

[0009] FIG. 2 is a block diagram of one example of an adaptive anti-jam filter in accordance with aspects of the present disclosure;

[0010] FIG. 3 is a more detailed block diagram of an example of the adaptive anti -jam filter of FIG. 2, in accordance with aspects of the present disclosure;

[0011] FIG 4 is a block diagram one of example of an input module to an adaptive anti -jam filter in accordance with aspects of the present disclosure;

[0012] FIG. 5 is a block diagram of one example of a windowed fast Fourier transform (FFT) module in accordance with aspects of the present disclosure;

[0013] FIG. 6 is a block diagram of one example of an exponential averaging bin filter in accordance with aspects of the present disclosure;

[0014] FIG. 7 is a block diagram of another example of an adaptive anti -jam filter in accordance with aspects of the present disclosure;

[0015] FIG. 8 is a flow chart for one example of a bin interpolation process in accordance with aspects of the present disclosure;

[0016] FIG. 9 is a graph illustrating an example of FFT output data to which the process of FIG.

8 may be applied in accordance with aspects of the present disclosure; and

[0017] FIG. 10 is a flow diagram for one example of a filtering process in accordance with aspects of the present disclosure.

[0018] Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent in light of this disclosure.

DETAILED DESCRIPTION

[0019] Techniques are provided herein for detecting and suppressing interfering signals (sometimes referred to as RF jamming signals or interferers) in an RF environment. As noted above, the presence of interfering signals can degrade system performance. Accordingly, many applications, both military and commercial, have stringent requirements for anti-jam performance. There is therefore a need to provide frequency excision (anti-jam) capability that can be used in a variety of different applications.

[0020] To this end, and in accordance with various aspects and embodiments disclosed herein, an RF anti -jam adaptive fdter is described. Examples of the filter disclosed herein may be particularly well suited to systems in which the RF signals of interest are pulsed signals, and the pulsed nature of the signals may not be suitable for other interference mitigation techniques. In addition, the filter may provide relatively high performance interferer suppression with relatively low firmware/software implementation cost and relatively low latency in the processing path, compared to other approaches. As discussed further below, certain embodiments employ a dualpath approach in which the system input signal (e.g., an RF signal waveform) is processed through a low-latency infinite impulse response (HR) filter path, while an analysis path runs in parallel and is used to determine the HR filter coefficients in real time. This provides low-latency reception of the signal of interest, allowing the filter to be compatible with, and used in systems employing, a wide range of different RF signal waveforms, including pulse position modulation waveforms, differential phase modulated waveforms, minimum shift keying (MSK) waveforms, and others. Further, by dynamically altering the coefficients, the center (notch) frequency and/or the bandwidth of each HR filter can be adjusted in real time, thus allowing the filter to adapt to changing interferers and conditions.

[0021] The disclosed RF anti-jam adaptive filter can be used, for instance, with receiver systems in a wide variety of applications including, for example, radar systems and communication systems that can be deployed on aircraft (manned and unmanned), guided munitions and projectiles, spacebased systems (e.g., satellite-based platforms), electronic warfare systems, and other communication systems including cellular telephones and smartphones, although other applications will be apparent. In some embodiments, the filter is used in an Identification Friend or Foe (IFF) system, and the input RF signal waveforms include those defined for IFF transponders and interrogators.

[0022] Various known frequency excision techniques, such as those involving processing in the frequency domain (e.g., FFT bin notching), require conversion back to the time domain. Not only is this costly from a resource perspective, but also incurs a significant amount of latency, rendering such approaches unsuitable for applications with fast turn-around time requirements (such as IFF systems employing SIF modes of operation, for example). Other frequency excision techniques involve the use of an Adaptive Line Enhancer (ALE). However, this approach includes a costly additional estimation of a delay parameter and is not suited for dynamically changing tonal interferers. In contrast, as discussed further below, embodiments of the adaptive anti -jam fdter disclosed herein adapt to changing tonal interferers to provide suppression of the interferers without significant detriment to the signal of interest, thereby providing high performance for IFF pulsed CW and Mode 5 MSK decoding. In many communications systems, the carrier signal is constant for a long duration, and therefore interference approaches using ALE or FFT bin notching may be suitably applied, whereas in systems using pulsed RF signals, the pulsed nature of the signals can make interference mitigation more complex and may not be well suited to such approaches. Examples of the adaptive filter disclosed herein advantageously provide an effective interference mitigation technique that can be applied to pulsed RF signals, thereby offering a solution for systems employing pulsed RF signals.

[0023] Further, in many adaptive interference cancellation implementations, such as those employing Least Mean Squares (LMS) type adaptive filters, errors in the interference estimate can corrupt the processing path. In contrast, because of the parallel path design of embodiments of the adaptive filter disclosed herein, the processing path runs independently of the analysis path. As discussed further below, in examples, the analysis path controls the center frequency of narrowband notch filters implemented in in the processing path whose transfer functions are stable and deterministic. If a notch is incorrectly assigned in the processing path, the effect to the signal of interest is minimal since the notch bandwidth is very narrow compared with the signal bandwidth. When the notch is correctly assigned, the tonal interferer is suppressed by an amount between 30dB and 40dB in some examples.

[0024] It will be appreciated that the techniques and adaptive filter implementations described herein may provide improved signal processing and/or improved performance in the presence of multiple strong interfering signals that could otherwise disrupt system communications. Numerous embodiments and applications will be apparent in light of this disclosure.

System Architecture

[0025] FIG. 1 is a block diagram of an RF system 100, configured in accordance with certain aspects of the present disclosure. In examples, the RF system 100 is a combined transponder (XP) and interrogator (IR) IFF system that transmits and receives RF signals. Accordingly, in such examples, the RF system 100 includes a transponder input/output (I/O) module 102 coupled to one or more antennas 104, and an interrogator I/O module 106 also coupled to one or more antennas 108. Signals received via the transponder I/O module 102 and the interrogator module 106 (and their associated antennas 104, 108) are passed to an RF front end 110, and from the RF front-end 110 to a filtering and down-conversion module 112. The RF front end 110 may include filters, amplifiers, frequency converters, and/or other functional components as needed for a particular application. The filtering and down-conversion module 112 performs various filtering operations on the signals received from the RF front-end 110, and down-converts the signals to baseband for processing at the baseband processing module 114. The filtering and down-conversion module 112 includes one or more adaptive anti-jam filter(s) 200, examples and implementations of which are discussed in more detail below. For example, in a combined transponder and interrogator IFF system 100, the filtering and down-conversion module 112 may include two adaptive anti-jam filters 200, one for each channel. In other examples, the system 100 may include only an interrogator or only a transponder, in which case, only one anti -jam filter 200 may be included. In other examples, the system 110 may be configured for one or more applications other than IFF, and one or more adaptive anti -jam filters 200 can be included as needed for any particular application or implementation. Various components and features of the filtering and downconversion module 112 may be implemented in hardware, firmware, software, or a combination thereof, as discussed further below. In some examples, at least portions of the filtering and downconversion module 112 and the baseband processing module 114 may be implemented on the same chip, which may include one or more embedded processors for executing software implementations of one or more features.

[0026] FIG. 2 is a high-level block diagram showing an architecture for an example of the adaptive anti -jam filter 200 according to certain aspects. In the example shown in FIG. 2, one input signal path is shown for purposes of illustration and explanation; however, in other examples, components and signal paths discussed herein may be duplicated for additional inputs as needed for any given application and/or implementation. As discussed above, in examples, the adaptive anti-jam filter 200 includes an analysis path/module 202 that is operated in parallel with a processing path/module 204. An input block 206 produces an input signal 212, which in certain examples is a complex signal, that is divided into the analysis path 202 and the processing path 204, as shown in FIG. 2. The input signal 212 may represent a signal of interest along with one or more interferers. In the analysis path 202, a threat analysis block 208 monitors the passband of the signal of interest looking for malicious signals (interferers) that might impede system performance. In the processing path 204, an adaptive low-latency fdtering device 210 fdters the input signal 212 to remove or suppress interferers and allow the signal of interest to pass through to the output 214. As used herein, to suppress the interferers means to reduce an amplitude of the interfering signals to below a threshold such that the interfering signals do not obscure or degrade the signal of interest to a degree that substantially affects operation of the RF system 100. When one or more interfering signals are identified by the threat analysis block 208 for excision, coefficients for the filtering device 210 are calculated (indicated at block 216) and programmed, such that the filtering device 210 is tuned (adapted) to the current identified interfering signals. As new interfering signals are detected, the filter coefficients are updated, such that the filtering device 210 dynamically adjusts to changing tonal interferers, as discussed above. Embodiments of the filtering device 210 can be implemented entirely in firmware, for example, as a field programmable gate array (FPGA) device. Components of the analysis path 202 can be implemented in a combination of firmware and software that is executed on an embedded processor included on the same chip as the FPGA in which the filtering device 210 is implemented.

[0027] Referring to FIG. 3, there is illustrated a more detailed block diagram of an example of an implementation of the adaptive anti-jam filter 200 according to certain embodiments. As discussed above, the filter 200 includes the analysis path 202 that operates on the input signal 212 in parallel with the processing path 204. The components of the analysis path 202 and the processing path 204 are discussed in detail below.

[0028] In examples, the filtering device 210 in the processing path 204 is implemented using a plurality of HR notch filters with very low latency, for example, less than 100 nanoseconds (ns) in some implementations, thus making it suitable for SIF-mode IFF and other applications with very stringent turn-around time requirements. According to certain examples, the filtering device 210 is implemented using six sequential second order HR real notch filters with three 12-bit fixed point coefficients per filter. In some examples, using no more than six notch filters in the filtering device 210 keeps the latency through the filtering device 210 to levels low enough to support applications with very low latency requirements, as discussed above. However, it will be appreciated that more or fewer than six HR filters can be used, more or fewer than three coefficients can be calculated for each filter, and that each coefficient can be described by more or fewer than 12 bits. The HR notch filters are arranged in a series configuration capable of excising up to six frequencies (each notch filter being tuned to remove a corresponding interferer), with programmable bandwidth on each notch.

[0029] As discussed above, in certain examples, the RF system 100 is a combined IFF transponder and interrogator system. Accordingly, in some examples, the input signal 212 is an IFF transponder and/or an IFF interrogator signal. FIG. 4 illustrates an example of the input block 206 that produces the input signal 212. In the illustrated example, the input block 206 includes a transponder receive path and an interrogator receive path, and the input signal 212 may thus correspond at any given time to one or more signals received via either or both paths. Accordingly, it will be appreciated that examples of the input block 206 may correspond to components implemented within various modules of the RF system 100, including the transponder (VO) module 102 and its associated antenna(s) 104, the interrogator VO module 106 and its associated antenna(s) 108, the RF front end 110, and the fdtering and down-conversion module 112 In the illustrated example, the interrogator receive path includes an interrogator analog-to-digital converter (ADC) 402 that converts an interrogator receive signal to a digital baseband signal. The transponder receive path similarly includes a transponder ADC 404 that digitizes a transponder receive signal.

[0030] In various examples, in order to meet timing requirements for the signals traversing the adaptive anti -jam filter 200, the logic and circuitry of the various components of the filter 200 are configured to operate with a clock rate above the sample rate of the digital input signals 212. In examples, the clock rate is configured at four times the sample rate. Thus, for a sample rate of 80 megahertz (MHz), also referred to as a sample rate of 80 mega-samples per second (Msps), the clock rate would be 320 MHz. However, it will be appreciated that a wide variety of other values may be selected. In examples, the transponder receive path operates at a higher sample rate than does the interrogator receive path. For example, the interrogator receive path may operate at 80 Msps, whereas the transponder receive path may operate at 160 Msps. Accordingly, as shown in FIG. 4, in such examples, the transponder receive path includes a 2X finite impulse response (FIR) decimating filter 406 than reduces the sample rate for the signal 212 to 80 Msps, matching that of the interrogator receive path. For purposes of explanation and clarity, various examples and implementations discussed below will assume a sample rate for the input signal 212 of 80 Msps, however, it will be appreciated that embodiments of the anti-jam adaptive filter 200 are not limited in this regard, and the features, techniques and aspects disclosed herein are applicable to input signals with other sample rates. In examples, the interrogator ADC 402 and the transponder ADC 404 are implemented in a data converter that may be part of the fdtering and down -conversion module 112. The decimating fdter 406 in the transponder receive path may be implemented in firmware, optionally in the same FPGA as the filtering device 210.

[0031] Referring again to FIG. 3, as discussed above, in example, the input signal 212 is a complex baseband signal. The filtering device 210 in the processing path 204 may be operated at a complex intermediate frequency (IF) signal that is generated by up-conversion of the input signal 212. In examples, up-conversion is accomplished using a multiplierless Fs/4 complex up- conversion process at 302. In such examples, the IF generated by the up-converter 302 is one quarter of the input signal sample rate (Fs/4). Thus, for an input signal 212 having an 80 MHz sample rate, for example, the complex IF signal input to the filtering device 210 is centered at 20 MHz. After filtering (through the filtering device 210), the complex IF signal is down-converted back to baseband (to produce the output signal 214) with an Fs/4 down-conversion process at 304. Examples of the up-converter 302 and down-converter 304 may be implemented in firmware, operationally in the same FPGA as the filtering device 210. In examples, the total latency through the processing path 204 is less than 120 ns, making this implementation suitable for all modes of operation of the RF system 100, including those with the tightest turn-around time requirements.

[0032] The analysis path 202 runs in parallel with the processing path 204 and is used to determine the IIR filter coefficients in real time. In examples, a windowed Fast Fourier Transform (FFT) 306 implemented in firmware provides the raw data used for spectral analysis. Each FFT bin is averaged using an exponential averaging function at 308 to reduce the transient effects on the spectral data when a pulsed input signal 212 is present. Examples of the exponential averaging bin filter device 308 are implemented in firmware. The averaged bin data is stored in a dual port memory (e.g., a random access memory (RAM)) 310 which is read by a real time embedded processor 312. The dual port RAM 310 may be implemented in firmware. A software-based process identifies the peaks of possible interfering signals (at 314), as discussed further below. In examples, to increase the speed at which the filtering device 210 is updated, the software process employs a look up table (LUT) 316 to translate the desired notch frequency value and bandwidth for each HR filter in the filtering device 210 to three coefficients which are written to the firmware, as discussed above. Accordingly, the embedded processor 312 may include a programmable logic (PL) dual port RAM read interface 318 to read the bin data (corresponding to the desired notch frequencies) from the dual port RAM 310, and a PL register write interface 320 that writes the calculated fdter coefficients to the filtering device 210.

[0033] As a result of the FFT-based implementation of the analysis path 202, the frequency bin resolution is determined by the sample rate and FFT size. The size and therefore resolution may depend on the particular application for which the system is configured. In order to obtain a higher resolution on the ability to program the notch frequency values, embodiments use a process to estimate the location of the interfering signal with fractional bin resolution based on the relative strength of adjacent bin values. This process allows for increased performance by more accurately aligning the programmed notch filters in the filtering device 210 with the true frequencies of the interferers. Examples of this process are discussed in more detail below.

[0034] As discussed above, in examples, the input signal 212 is a complex baseband signal. Accordingly, in some such examples, the analysis path 202 includes an up-converter 322 to convert the input signal 212 to an IF signal. In some examples, the analysis path may operate on a complex IF signal, and therefore the up-converter 322 may up-convert the input signal to a complex IF signal. However, there may be advantages in terms of processing speed and/or computational resources to have the analysis path 202 operate on a real IF signal, rather than a complex IF signal. Accordingly, in some examples, the up-converter 322 converts the input signal 212 in the analysis path to a real IF signal. Thus, the up-converter 322 may implement a multiplierless Fs/4 real up- conversion process. Thus, for the input signal 212 having a sample rate of 80 MHz, as discussed above, the up-converter 322 generates a real IF signal centered at 20 MHz. The up-converter 322 may implemented in firmware. In certain examples, the firmware components of the analysis path 202 are implemented in the same FPGA as the filtering device 210, and the processor 312 is embedded with the FPGA.

[0035] Turning now to FIG. 5, there is illustrated a block diagram of one example of an implementation of the windowed FFT block 306 as may be used in the analysis path 202. The “data in” 502 (input data) is the real IF input signal generated by the up-converter 322 (for example, output at 508 in FIG. 5A). An FFT core 504 operates on the input data 502. In examples, the FFT core 504 is configured for a burst mode of operation with a block size of N=2048 samples. The As discussed above, in examples, the input data 502 is read into the FFT core 504 at a sample rate of 80 MHz, and the windowed FT block 306 runs at a clock rate of 320 MHz. Enable logic 506 turns ON and OFF the FFT core 504 and feeds the output from the FFT core 504 into a window 508 to produce windowed data. The windowed data is mixed with the input data 502 via a multiplier 510, as shown in FIG. 5. Windowing lessens the effects of the burst nature of some input signals corresponding to the input data 502, and may allow the FFT block 306 to provide improved performance relative to implementations without the window 508. In examples, the window 508 is a Hanning window; however in other examples, other windowing functions can be used. In further examples, overlapping transforms using additional FFTs can be used (with or instead of windowing) to improve edge effects, if desired for a particular implementation or application. In the illustrated example, the output from the FFT core 504 is provided to a saturation block 512. The saturation function at block 512 monitors the output of the FFT core 504 for overflow conditions, and reduces the size of the output vector, if necessary, to prevent overflow. That is, when necessary, the saturation block 512 saturates the output vector from the FFT core 504 at the maximum permissible positive or negative value. The output vector from the FFT core 504 is a complex vector; however, as noted above, the analysis path operates on a real IF signal. Accordingly, only the real component of the output from the FFT core 504 is used, and therefore, the magnitude block 514 removes the imaginary (e.g., phase) component of the vector, such that the FFT output data 516 is real (e.g., magnitude) only. The FFT output data 516 is representative of the frequency content of the input signal 212.

[0036] For an N = 2048 point FFT, for example, a sample rate of 80 MHz as discussed above establishes a frequency bin resolution of 80 MHz divided by 2048 bins, resulting in 39.0625 kHz per bin. Of the 2048 output bins in this examples, the first 1024 output bins represent frequencies from DC (0 Hz) to 40 MHz and the second 1024 output bins are duplicates of the first half because they represent the negative frequencies from -40 MHz to DC. In certain examples, it may be desirable to filter out passband interference that falls within +/- 10 MHz of the center carrier frequency of the signal of interest. Thus, for examples in which the input signal is centered at 20 MHz, as discussed above, the 512 output bins from 10 MHz to 30 MHz may be processed by the embedded processor 312 to calculate the filter coefficients for the filtering device 210. Accordingly, in examples, the output 516 from the windowed FFT block 306 that is passed to the next stage of processing may include only the output bins of interest (e.g., the 512 output bins in the example discussed above).

[0037] In examples, before writing the FFT magnitude data represented by the output 516 to the dual-port RAM 310, an exponential, the output 516 from the windowed FFT block 306 is provided to an exponential averaging bin filter 308 that uses an averaging function to reduce transient effects on the spectral data and “smooth” the response. Referring to FIG. 6 there is illustrated one example of an implementation of the exponential averaging bin filter 308. In examples, the exponential averaging bin filter 308 includes a summation component 602 and a pair of multipliers 604, 606. The output 516 from the windowed FFT block 306 is input to a first multiplier 604, where it is mixed with a parameter, a. In examples, the parameter, a, is written to the exponential averaging bin filter 308 by a processor 712 (see FIG. 7). The parameter, a, determines the degree to which new bin values contribute to the filtered output 608 that is written to the dual-port RAM 310. The output of the first multiplier 604 is input to the summation component 602. The filtered output 608 of the summation component 602 is fed back into the second multiplier 606, where it is mixed with a value equal to (1-a), as shown in FIG. 6. The output of the second multiplier 606 is input to the summation component 602, where it is summed with the output of the first multiplier 604 to produce the filtered output 608.

[0038] Referring to FIG. 7, there is illustrated a block diagram of another example of an implementation of the anti -jam filter 200 showing various components discussed above. In the example of FIG. 7, the anti-jam filter device 700 represents components of the anti-jam filter 200 implemented in firmware, including the filtering device 210, the windowed FFT block 306, the exponential averaging bin filter 308, and the up-conversion and down-conversion components 302, 304, and 322 discussed above. As shown, in this example, the embedded processor 312 in the analysis path 202 receives FFT data for the IFF transponder (XP) path, represented by block 702, and for the IFF interrogator (IR) path, represented by block 704. Thus, in this example, the dualport RAM 310 (FIG. 3) corresponds to blocks 702 and 704, and the output FFT data 608 that is written to the dual-port RAM 310 includes XP data and IR data, as shown. The embedded processor 312 calculates filter coefficients for filtering device 210 for both the transponder and interrogator paths, which are written, via the PL register write interface 320 (FIG. 3), to registers 706 and 708, respectively. As discussed above, the processor 712 provides the parameter, a, used by the exponential averaging bin filter 308 for both the transponder (indicated at block 714) and interrogator (indicated at block 716) paths. In some examples, if the parameter, a, is not being used in a given calculation, the processor 712 can provide a “bypass” parameter instead, as indicated at block 718. The embedded processor 312 and the processor 712 can access a shared memory 710 that includes various system configuration and status data as may be needed for operation of the anti-jam filter 200.

[0039] The embedded processor 312 and the processor 712 can be any suitable processor, and may be implemented as any number of processor cores. The processor 312 may include multithreaded cores in that it may include more than one hardware thread context (or “logical processor”) per core. In some examples, the processor 712 may be implemented as one or more cores of the processor 312. In other examples, the processor 712 may be an additional processor. The processor(s) 312, 712 may be implemented as a complex instruction set computer (CISC) or a reduced instruction set computer (RISC) processor. In some examples, the processor 312 and/or processor 712 may be configured as an x86 instruction set compatible processor. The processor 312 may be configured to execute an Operating System (OS) which may comprise any suitable operating system, such as Google Android (Google Inc., Mountain View, CA), Microsoft Windows (Microsoft Corp., Redmond, WA), Apple OS X (Apple Inc., Cupertino, CA), Linux, or a real-time operating system (RTOS).

[0040] The shared memory 710 can be implemented using any suitable type of digital storage including, for example, flash memory and/or random access memory (RAM). In some examples, the memory 710 may include various layers of memory hierarchy and/or memory caches as are known to those of skill in the art. The memory 710 may be implemented as a volatile memory device such as, but not limited to, a RAM, dynamic RAM (DRAM), or static RAM (SRAM) device.

[0041] Referring again to FIG. 3, the embedded processor 312 in the analysis path 202 accesses the fdtered output FFT data 608 from the dual -port RAM 310 (optionally implemented using blocks 702 and 704 discussed above) via the PL dual-port RAM read interface 318. The embedded processor 312 may include, or be coupled to, at least one computer readable medium that stores program instructions that, when executed by the embedded processor, implement processes to determine the desired IIR fdter coefficients for the filtering device 210 based on the FFT data 608. As discussed above with reference to FIG. 2, in some examples, the analysis path includes the threat analysis block 208 that identifies the location of an interfering signal in order to determine the filter coefficients needed to remove that interfering signal. In examples, an FFT is used to identify the frequency content of the input signal 212, as discussed above. The more precise the estimate of the frequency content of the input signal 212, the more accurate the adaptive anti -j m filter 200 will be in generating filter coefficients to remove interfering signals in the input signal 212. Conventionally, when using an FFT, added precision generally means using a larger FFT block size (higher point number). However, increasing the FFT block size significantly increases the processing resources needed to implement the FFT. For example, calculating an N = 4096 point FFT may require significantly more computing resources than calculating an N = 2048 point FFT. In addition, using a larger FFT block size increases the processing time, and thus the latency in the analysis path, which may be undesirable or even unacceptable for some applications. As discussed above, in some examples, calculation of the filter coefficients is implemented using a look-up table (LUT) 316 to reduce latency in the analysis path 202. However, the accuracy in removing interferers is limited by the resolution of the LUT 316. Normally, the FFT block size used in windowed FFT block 306 would directly determine the resolution of the LUT 316. However, in certain examples, the embedded processor 312 implements a peak detection and bin interpolation process 314 that allows the bin resolution of the FFT data to be increased without the added complexity and processing resources associated with increasing the FFT block size.

[0042] Referring to FIG. 8, there is illustrated a flow diagram of one example of the peak detection and bin interpolation process 314 according to certain aspects. The process 314 operates on the filtered output FFT data 608, which in some examples, includes the 512 output bins of interest discussed above. Accordingly, the following example refers to using 512 FFT output bins; however, it will be appreciated that other values may be used and that the principles and approach discussed below for the process 314 may be applied to any number of FFT output bins.

[0043] Starting with the original FFT bin resolution (determined based on the N point FFT used in block 306), at 802, the 512 FFT bin magnitude values of interest are analyzed to determine the peak magnitude bin as a nominal reference, f mag, for a particular interferer. In some examples, all local maxima are identified in the 512 FFT bins, and the six largest peaks (for a six HR filter implementation) are found among all the local maxima. A value, f_mag, is determined for each identified interferer. Items 804-810 can then be applied for each identified interferer.

[0044] At 804, the bin magnitudes on the left and right of the nominal reference bin, f_mag, are extracted from the original FFT magnitude buffer to produce data points f magleft and f magright. [0045] At 806, the nominal reference value, f_mag, is translated onto a new frequency bin vector representing the same span of frequencies, but with M times the resolution of the original 512 FFT bin values, thus producing Mx512 new frequency bin values. In one example, M=4, such that 2048 new frequency bin values are produced. The new initial higher resolution index value of the reference value, f_mag, is M times (e.g., 4 times) the original f_mag index value.

[0046] At 808, the values f magleft and f magright are normalized by f mag to determine the strength of the adjacent magnitude bins relative to the strength of f mag. If the magnitude, f_magleft, is greater than the magnitude, f_magright, a number of frequency indexes is subtracted from the newly translated f_mag index value. In some examples, the number of frequency indexes subtracted is zero, one, or two frequency indexes. If the magnitude, f_magleft, is less than the magnitude, f magright, the same number of frequency indexes (e.g., zero, one, or two) are added to the newly translated f_mag index value.

[0047] At 810, the normalized f magleft and f magright are then compared with threshold values to determine whether the final coefficient result from the LUT 316 should be unchanged (add/ subtract zero frequency indexes), or shifted in frequency by ±1 or ±2 frequency indexes. In some examples, these threshold are fixed threshold values. In some examples, the threshold values are determined based on the mean signal power close to the carrier center frequency. In examples in which each original FFT output bin corresponds to four higher-resolution bins (M=4, as discussed above), adjusting the frequency for the normalized f_mag, f_magleft, and/or f_magright values by up to ±2 frequency indexes allows for moving (“tuning”) the frequency corresponding to the detected interferer within the corresponding original frequency bin in which the peak was detected.

[0048] The output produced at 812 is the final value of the frequency index for each interferer. This output 812 is an interpolated frequency index that can be used as the input to a 2048 LUT 316 (rather than only a 512 LUT based on the original FFT bin resolution) for determining more accurate corresponding filter coefficients for each identified interferer.

[0049] FIG. 9 is a graph illustrating an example of FFT output data 608 including a detected peak 902. In this example, the detected peak 902 is located at bin 205 in the original 512 bin FFT output. Applying the process discussed above with reference to FIG. 8, after translation onto a 4X higher resolution bn scale, the frequency bin corresponding to the peak 902 becomes bin 820 (4 x 205). Based on the relative amplitude between the original peak 902 at bin 205 and the next highest adjacent bin at 204, an adjustment can be made (at 810) to down-shift the peak frequency bin from 820 to 818 because the data indicates that, on the higher resolution scale, the true location of the interfering tone at closer to bin 81 than to bin 820 (as may be seen referring to FIG 8, the true peak likely falls between bins 204 and 205, rather than at bin 205). The same process 314 can be applied to other detected peaks, such as peak 904 in the example shown in FIG. 9, for example.

[0050] Referring again to FIG. 3, the frequency bins identified for each detected peak (interferer) in the input signal 212 (corresponding to the output 812) are input to the coefficient look-up table 316 to determine the corresponding filter coefficients. The coefficients are written to the filtering device 210 via the PL register write interface 320 (and filter coefficient registers 706, 708, as shown in FIG. 7). Thus, the filtering device 210 is tuned, in terms of center notch frequency and/or bandwidth of one or more of the HR filters, based on the determined filter coefficients, to filter out the current identified interfering signals.

[0051] Thus, aspects and embodiments provide an RF anti -jam adaptive filter that can provide high performance interferer suppression with low firmware/software implementation cost and very low latency in the processing path. As such, examples of the anti -jam adaptive filter disclosed herein may be suitable for a wide range of applications, including those with stringent latency requirements. Certain embodiments may provide an effective solution for interference mitigation is systems using pulsed RF signals, which may not be suitable for other interference mitigation approaches. In addition, embodiments of the filter provide the ability to identify and suppress very narrow spectral line interferers (through the use of the IIR notch filters) without significantly negatively impacting the signal of interest. Furthermore, the bandwidth and central frequency of each notch filter can be dynamically adjusted, thereby providing the ability to respond to dynamically changing tonal interferers, as described above.

[0052] As discussed above, various components of examples of the anti -jam filter 200, and the RF system 100 in which it is used, may be combined or integrated in a system-on-a-chip (SoC) architecture. In some examples, the components may be hardware components, firmware components, software components or any suitable combination of hardware, firmware or software. Accordingly, and as discussed above, various examples may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (for example, transistors, resistors, capacitors, inductors, and so forth), integrated circuits, ASICs, programmable logic devices, digital signal processors, FPGAs, logic gates, registers, semiconductor devices, chips, microchips, chipsets, and so forth. Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an embodiment is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power level, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints.

[0053] Some examples may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not intended as synonyms for each other. For example, some embodiments may be described using the terms “connected” and/or “coupled” to indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still cooperate or interact with each other.

[0054] In some examples, at least one non-transitory computer readable storage medium has instructions encoded thereon that, when executed by one or more processors (such as the processors 312 and/or 712 discussed above), cause one or more of the methodologies and/or processes disclosed herein to be implemented. The instructions can be encoded using a suitable programming language, such as C, C++, object oriented C, Java, JavaScript, Visual Basic .NET, Beginner’s All-Purpose Symbolic Instruction Code (BASIC), or alternatively, using custom or proprietary instruction sets. The instructions can be provided in the form of one or more computer software applications and/or applets that are tangibly embodied on a memory device, and that can be executed by a computer having any suitable architecture. The computer software applications disclosed herein may include any number of different modules, sub-modules, or other components of distinct functionality, and can provide information to, or receive information from, still other components. Other componentry and functionality not reflected in the illustrations will be apparent in light of this disclosure, and it will be appreciated that other embodiments are not limited to any particular hardware or software configuration.

[0055] The aforementioned non-transitory computer readable medium may be any suitable medium for storing digital information, such as a hard drive, a server, a flash memory, and/or random-access memory (RAM), or a combination of memories. In various examples, as discussed above, at least some components and/or modules disclosed herein can be implemented with hardware, including gate level logic such as a field-programmable gate array (FPGA), or alternatively, a purpose-built semiconductor such as an application-specific integrated circuit (ASIC). It will be apparent that any suitable combination of hardware, software, and firmware can be used, and that other embodiments are not limited to any particular system architecture.

[0056] Unless specifically stated otherwise, it may be appreciated that terms such as “processing,” “computing,” “calculating,” “determining,” or the like refer to the action and/or process of a computer or computing system, or similar electronic computing device, that manipulates and/or transforms data represented as physical quantities (for example, electronic) within the registers and/or memory units of the computer system into other data similarly represented as physical entities within the registers, memory units, or other such information storage transmission or displays of the computer system. The examples are not limited in this context.

[0057] The terms “circuit” or “circuitry,” as used in any embodiment herein, are functional and may comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry such as computer processors comprising one or more individual instruction processing cores, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. The circuitry may include a processor and/or controller configured to execute one or more instructions to perform one or more operations described herein. The instructions may be embodied as, for example, an application, software, firmware, etc. configured to cause the circuitry to perform any of the aforementioned operations. Software may be embodied as a software package, code, instructions, instruction sets and/or data recorded on a computer-readable storage device. Software may be embodied or implemented to include any number of processes, and processes, in turn, may be embodied or implemented to include any number of threads, etc., in a hierarchical fashion. Firmware may be embodied as code, instructions or instruction sets and/or data that are hard-coded (e.g., nonvolatile) in memory devices. The circuitry may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), desktop computers, laptop computers, tablet computers, servers, smartphones, etc. Other examples may be implemented as software executed by a programmable control device. In such cases, the terms “circuit” or “circuitry” are intended to include a combination of software and hardware such as a programmable control device or a processor capable of executing the software. Methodology

[0058] FIG. 10 is a flowchart illustrating a methodology 1000 for anti-jam filtering in accordance with aspects of the present disclosure. As can be seen, example process 1000 includes a number of phases and sub-processes, the sequence of which may vary from one embodiment to another. However, when considered in aggregate, these phases and sub-processes form a process for enhancing anti -jam performance in RF environments, in accordance with certain of the embodiments disclosed herein, for example as illustrated in FIGS. 1-9 and described above. However other system architectures can be used in other embodiments, as will be apparent in light of this disclosure. To this end, the correlation of the various functions shown in FIG. 10 to the specific components illustrated in the figures, is not intended to imply any structural and/or use limitations. Numerous variations and alternative configurations will be apparent in light of this disclosure.

[0059] In one example, the process 1000 commences at 1002 with reception of the input signal 212 discussed above.

[0060] At 1004, the signal 212 is up-converted to an intermediate frequency, as discussed above. [0061] In the processing path, the up-converted input signal is filtered (at 1014) through a filtering device to remove interfering signals that have been detected within the input signal 212. As discussed above, in examples, the filtering device includes a bank of one or more HR filters that are tuned to specific interferer frequencies using a set of filter coefficients per HR filter.

[0062] In the analysis path, at 1006, an FFT process is applied to produce FFT output data, as discussed above. In examples, applying the FFT process at 1006 can include implementing and operating the windowed FFT 306 and exponential averaging bin filter 308 discussed above.

[0063] At 1008, a peak detection and bin interpolation process, such as the process 314 discussed above with reference to FIG. 7, for example, is applied to the FFT output data obtained at 1008. As discussed above, using a bin interpolation process, such as the process 314, allows the system to achieve higher frequency resolution for detected interferers without increasing the FFT block size, which is advantageous in terms of processing resources and processing time.

[0064] At 1010, filter coefficients are obtained, and at 1012, the newly determined filter coefficients are used to update/tune the IIR filters that operate on the up-converted input signal at 1014. In examples, obtaining the filter coefficients at 1010 includes determining the filter coefficients using a look-up table (e g., LUT 316) based on the higher resolution FFT data obtained from the peak detection and bin interpolation process applied at 1008.

[0065] In the processing path, at 1016, the signal filtered at 1014 is down-converted back to baseband.

[0066] The process 1000 ends at 1018 with provision of the filtered output signal 214.

Further Examples

[0067] The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

[0068] Example 1 is an adaptive filter comprising a filtering device coupled between an input port and an output port, and including at least one infinite impulse response (HR) filter, the filtering device being configured to receive an input signal via the input port and to provide a filtered output signal at the output port, and an analysis module coupled between the input port and the filtering device, the analysis module being configured to receive the input signal via the input port, to determine a set of filter coefficients for the at least one HR filter based on detecting at least one interfering signal in the input signal, and to provide the a set of filter coefficients to the filtering device to update a configuration of the at least one IIR filter using the set of filter coefficients.

[0069] Example 2 includes the adaptive filter of Example 1, wherein the analysis module comprises a fast Fourier transform (FFT) module configured to perform an FFT on the input signal and to provide FFT output data representative of frequency content of the input signal.

[0070] Example 3 includes the adaptive filter of Example 2, wherein the analysis module further comprises a memory configured to store the FFT output data, at least one processor coupled to the memory, and at least one processor-readable medium storing program instructions executable by the at least one processor to control the adaptive filter to analyze the FFT output data to detect the at least one interfering signal, determine an estimated frequency of the at least one interfering signal, and determine the set of filter coefficients based on the estimated frequency of the at least one interfering signal using a look-up table.

[0071] Example 4 includes the adaptive filter of Example 3, wherein the at least one processor- readable medium further stores program instructions executable by the at least one processor to control the adaptive filter to apply a frequency bin interpolation process to the FFT output data to determine the estimated frequency of the at least one interfering signal. [0072] Example 5 includes the adaptive filter of any one of Examples 2-4, wherein the FFT module is a windowed FFT module configured to implement a Hanning windowing function.

[0073] Example 6 includes the adaptive filter of any one of Examples 1-5, further comprising an up-converter coupled to the input port and configured to up-convert the input signal received at the input port to an intermediate frequency (IF) to provide a complex IF input signal and optionally a real IF input signal corresponding to the input signal. The up-converter is configured to provide the provide the complex IF input signal to the filtering device, and to provide either the real or complex IF input signal to the analysis module.

[0074] Example 7 includes the adaptive filter of Example 6, further comprising a down-converter coupled to the filtering device and configured to down-convert the filtered output signal in frequency to baseband.

[0075] Example 8 includes the adaptive filter of any one of Examples 1-7, wherein the at least one HR filter includes six HR filters, and wherein the set of filter coefficients includes three filter coefficients per HR filter.

[0076] Example 9 provides a radio frequency (RF) system comprising the adaptive filter of any one of Examples 1-8.

[0077] Example 10 provides a computer program product including one or more non-transitory machine-readable mediums encoded with instructions that when executed by one or more processors cause a process to be carried out for filtering an input signal to suppress one or more interfering signals. The process comprises applying a fast Fourier transform (FFT) to the input signal to produce FFT output data that includes a plurality of frequency bins, detecting one or more magnitude peaks in the FFT output data corresponding to the one or more interfering signals, applying a frequency bin interpolation process to the FFT output data to determine estimated frequencies of the one or more interfering signals, based on the estimated frequencies, determining a plurality of filter coefficients, and configuring a filtering device using the one or more filter coefficients, wherein configuring the filtering device includes adjusting a center notch frequency and a bandwidth of at least one infinite impulse response (HR) filter in the filtering device.

[0078] Example 11 includes the computer program product of Example 10, wherein the process further comprises up-converting the input signal in frequency to provide a complex IF component of the input signal and optionally a real intermediate frequency (IF) component of the input signal, and down-converting the filtered output signal in frequency to baseband. [0079] Example 12 includes the computer program of Example 11 , wherein applying the FFT to the input signal includes applying the FFT to either the real IF component of the input signal or the complex IF component of the input signal.

[0080] Example 13 includes the computer program product of any one of Examples 10-12, wherein the input signal corresponds to a radio frequency (RF) signal waveform including at least one of an Identification Friend or Foe (IFF) transponder waveform or an IFF interrogator waveform.

[0081] Example 14 includes the computer program product of any one of Examples 10-13, wherein applying the frequency bin interpolation process includes determining nominal frequencies of the one or more magnitude peaks based on a first frequency resolution of the FFT, translating the nominal frequencies to frequency index vector having a second frequency resolution higher than the first frequency resolution to produce translated frequency values, determining frequency index offset values based on relative magnitudes between the one or more magnitude peaks and magnitude values of frequencies adjacent to the nominal frequencies, and determining the estimated frequencies of the one or more interfering signals based on the translated frequency values and the frequency index offset values.

[0082] Example 15 includes the computer program product of any one of Examples 10-14, wherein applying the FFT to the input signal includes applying an N-point windowed FFT.

[0083] Example 16 includes the computer program product of any one of Examples 10-15, wherein configuring the filtering device includes tuning one or more infinite impulse response (HR) filters using the one or more filter coefficients.

[0084] Example 17 provides a radio frequency (RF) system comprising the computer program product of any one of Examples 10-16.

[0085] Example 18 provides a radio frequency (RF) Identification Friend or Foe (IFF) system comprising an input port configured to receive an IFF input signal, the IFF input signal including at least one of an IFF transponder waveform or an IFF interrogator waveform, an output port, and an adaptive filter coupled between the input port and the output port and configured to provide a filtered signal at the output port, the adaptive filter including a plurality of infinite impulse response (HR) filters coupled in series between the input port and the output port and configured to filter the IFF input signal to produce the filtered signal at the output port, and an analysis module configured to determine a set of corresponding filter coefficients for each of the plurality of HR filters based on detecting one or more interfering signals in the IFF input signal, and to provide the set of corresponding filter coefficients to the plurality of IIR filters to update a center notch frequency and a bandwidth of the plurality of IIR filters using the set of corresponding filter coefficients.

[0086] Example 19 includes the RF IFF system of Example 18, wherein the analysis module comprises a field programmable gate array (FPGA) configured to apply a fast Fourier transform (FFT) to the IFF input signal to produce FFT output data representative of frequency content of the IFF input signal.

[0087] Example 20 includes the RF IFF system of Example 19, wherein the analysis module further comprises a memory configured to store the FFT output data;, at least one processor coupled to the memory, and at least one computer readable medium storing program instructions executable by the at least one processor to control the analysis module to analyze the FFT output data to detect the one or more interfering signals, determine estimated frequencies of the one or more interfering signals, and determine the set of corresponding filter coefficients based on the estimated frequencies of the one or more interfering signals using a look-up table.

[0088] Example 21 includes the RF IFF system of Example 20, wherein at least one computer readable medium further stores program instructions executable by the at least one processor to control the analysis module to apply a frequency bin interpolation process to the FFT output data to determine the estimated frequencies of the one or more interfering signals.

[0089] Example 22 includes the RF IFF system of Example 21, wherein applying the frequency bin interpolation process includes determining nominal frequencies of one or more magnitude peaks in the FFT output data based on a first frequency resolution of the FFT, the one or more magnitude peaks corresponding to the one or more interfering signals, translating the nominal frequencies to frequency index vector having a second frequency resolution higher than the first frequency resolution to produce translated frequency values, determining frequency index offset values based on relative magnitudes between the one or more magnitude peaks and magnitude values of frequencies adjacent to the nominal frequencies, and determining the estimated frequencies of the one or more interfering signals based on the translated frequency values and the frequency index offset values.

[0090] Example 23 includes the RF IFF system of any one of Examples 18-22, wherein the FPGA further includes an up-converter coupled to the input port and configured to up-convert the IFF input signal received at the input port to an intermediate frequency (IF) to provide a complex IF input signal and optionally a real IF input signal and, the up-converter being configured to provide the complex IF input signal to the plurality of IIR filters and to provide either the real IF input signal or the complex IF signal to the analysis module, and a down-converter coupled between the plurality of HR filters and the output port and configured to down-convert the filtered output signal in frequency to baseband.

[0091] Example 24 provides an adaptive filter comprising a filtering device coupled between an input port and an output port, and including at least two infinite impulse response (HR) filters connected in series between the input port and the output port, the filtering device being configured to receive a pulsed input signal via the input port and to provide a filtered output signal at the output port; and an analysis module coupled between the input port and the filtering device, the analysis module being configured to receive the pulsed input signal via the input port, to determine filter coefficients based on detecting at least one interfering signal in the pulsed input signal, the filter coefficients including a respective set of filter coefficients for each of the at least two HR filters, and to provide the filter coefficients to the filtering device to dynamically update a configuration of the at least two IIR filters using the filter coefficients.

[0092] Example 25 provides an adaptive filter comprising a filtering device coupled between an input port and an output port, and including at least one infinite impulse response (HR) filter, the filtering device being configured to receive a pulsed input signal via the input port and to provide a filtered output signal at the output port, and an analysis module coupled between the input port and the filtering device and configured to receive the pulsed input signal via the input port. The analysis module includes a fast Fourier transform (FFT) module configured to perform an FFT on the input signal and to provide FFT output data representative of frequency content of the input signal, a memory configured to store the FFT output data, at least one processor coupled to the memory, and at least one processor-readable medium. The at least one processor-readable medium stores program instructions executable by the at least one processor to control the adaptive filter to analyze the FFT output data to detect at least one interfering signal in the pulsed input signal, determine an estimated frequency of the at least one interfering signal, and determine a set of filter coefficients for the at least one HR filter based on the estimated frequency of the at least one interfering signal using a look-up table, wherein the analysis module is configured to provide the set of filter coefficients to the filtering device to dynamically update a configuration of the at least one IIR filter using the set of filter coefficients.

[0093] Example 26 includes the adaptive filter of Example 25, wherein the set of filter coefficients includes three filter coefficients per HR filter, and wherein to update the configuration of the at least one HR filter includes updating a center notch frequency and a bandwidth of the at least one HR filter based on the set of filter coefficients.

[0094] Example 27 includes the adaptive filter of one of Examples 25 and 26, wherein the at least one HR filter includes a plurality of HR filters coupled in series between the input port and the output port, and wherein the set of filter coefficients includes a respective set of filter coefficients for each HR filter of the plurality of HR filters.

[0095] Example 28 includes the adaptive filter of Example 27, wherein the plurality of HR filter includes six IIR filters, and wherein the respective set of filter coefficients for each HR filter includes three respective filter coefficients for each HR filter.

[0096] Example 29 includes the adaptive filter of any one of Examples 25-28, wherein the at least one processor-readable medium further stores program instructions executable by the at least one processor to control the adaptive filter to apply a frequency bin interpolation process to the FFT output data to determine the estimated frequency of the at least one interfering signal.

[0097] Example 30 includes the adaptive filter of any one of Examples 25-29, further comprising an up-converter coupled to the input port and configured to up-convert the input signal received at the input port to an intermediate frequency (IF) to provide a complex IF input signal, and optionally a real IF input signal, corresponding to the input signal, the up-converter being configured to provide the complex IF input signal to the filtering device and to provide either the real IF input signal or the complex IF input signal to the analysis module.

[0098] Example 31 includes the adaptive filter of Example 30, further comprising a downconverter coupled to the filtering device and configured to down-convert the filtered output signal in frequency to baseband.

[0099] Example 32 includes the adaptive filter of any one of Examples 25-31, wherein the FFT module is a windowed FFT module configured to implement a windowing function.

[0100] Example 33 provides a radio frequency (RF) system comprising the adaptive filter of any one of Examples 25-32. [0101] Example 34 provides a computer program product including one or more non-transitory machine-readable mediums encoded with instructions that when executed by one or more processors cause a process to be carried out for fdtering an input signal to suppress one or more interfering signals. The process comprises up-converting the input signal in frequency to provide a complex IF input signal and optionally a real intermediate frequency (IF) input signal, applying a fast Fourier transform (FFT) to either the complex IF input signal or the real IF input signal to produce FFT output data that includes a plurality of frequency bins, detecting one or more magnitude peaks in the FFT output data corresponding to the one or more interfering signals, applying a frequency bin interpolation process to the FFT output data to determine estimated frequencies of the one or more interfering signals, based on the estimated frequencies, determining a set of fdter coefficients, configuring a filtering device using the set of filter coefficients, and filtering the complex IF input signal using the filtering device to suppress the one or more interfering signals and produce a filtered output signal.

[0102] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents. Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be appreciated in light of this disclosure. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner and may generally include any set of one or more elements as variously disclosed or otherwise demonstrated herein.

[0103] Numerous specific details have been set forth herein to provide a thorough understanding of the embodiments. It will be understood, however, that other embodiments may be practiced without these specific details, or otherwise with a different set of details. It will be further appreciated that the specific structural and functional details disclosed herein are representative of example embodiments and are not necessarily intended to limit the scope of the present disclosure. Tn addition, although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described herein. Rather, the specific features and acts described herein are disclosed as example forms of implementing the claims.

Claims

CLAIMS What is claimed is:

1. An adaptive filter comprising: a filtering device coupled between an input port and an output port, and including at least one infinite impulse response (IIR) filter, the filtering device being configured to receive a pulsed input signal via the input port and to provide a filtered output signal at the output port; and an analysis module coupled between the input port and the filtering device and configured to receive the pulsed input signal via the input port, the analysis module including a fast Fourier transform (FFT) module configured to perform an FFT on the pulsed input signal and to provide FFT output data representative of frequency content of the pulsed input signal, a memory configured to store the FFT output data, at least one processor coupled to the memory, and at least one processor-readable medium storing program instructions executable by the at least one processor to control the adaptive filter to analyze the FFT output data to detect at least one interfering signal in the pulsed input signal, determine an estimated frequency of the at least one interfering signal, and determine a set of filter coefficients for the at least one IIR filter based on the estimated frequency of the at least one interfering signal using a look-up table; wherein the analysis module is configured to provide the set of filter coefficients to the filtering device to dynamically update a configuration of the at least one IIR filter using the set of filter coefficients.

2. The adaptive filter of claim 1, wherein the set of filter coefficients includes three filter coefficients per IIR filter, and wherein to update the configuration of the at least one IIR filter includes updating a center notch frequency and a bandwidth of the at least one IIR filter based on the set of filter coefficients.

3. The adaptive filter of claim 1 , wherein the at least one ITR filter includes a plurality of TTR filters coupled in series between the input port and the output port, and wherein the set of filter coefficients includes a respective set of filter coefficients for each IIR filter of the plurality of IIR filters.

4. The adaptive filter of claim 3, wherein the plurality of IIR filter includes six IIR filters, and wherein the respective set of filter coefficients for each IIR filter includes three respective filter coefficients for each IIR filter.

5. The adaptive filter of claim 1, wherein the at least one processor-readable medium further stores program instructions executable by the at least one processor to control the adaptive filter to apply a frequency bin interpolation process to the FFT output data to determine the estimated frequency of the at least one interfering signal.

6. The adaptive filter of claim 1, further comprising: an up-converter coupled to the input port and configured to up-convert the pulsed input signal received at the input port to an intermediate frequency (IF) to provide a real IF input signal and a complex IF input signal corresponding to the input signal, the up-converter being configured to provide the real IF input signal to the analysis module and to provide the complex IF input signal to the filtering device.

7. The adaptive filter of claim 6, further comprising a down-converter coupled to the filtering device and configured to down-convert the filtered output signal in frequency to baseband.

8. The adaptive filter of claim I, wherein the FFT module is a windowed FFT module configured to implement a windowing function.

9. A radio frequency (RF) system comprising the adaptive filter of claim 1.

10. A computer program product including one or more non-transitory machine-readable mediums encoded with instructions that when executed by one or more processors cause a process to be carried out for filtering an input signal to suppress one or more interfering signals, the process comprising: applying a fast Fourier transform (FFT) to the input signal to produce FFT output data that includes a plurality of frequency bins; detecting one or more magnitude peaks in the FFT output data corresponding to the one or more interfering signals; applying a frequency bin interpolation process to the FFT output data to determine estimated frequencies of the one or more interfering signals; based on the estimated frequencies, determining a plurality of filter coefficients; and configuring a filtering device using the plurality of filter coefficients, wherein configuring the filtering device includes adjusting a center notch frequency and a bandwidth of at least one infinite impulse response (IIR) filter in the filtering device.

11. The computer program product of claim 10, wherein the input signal corresponds to a radio frequency (RF) signal waveform including at least one of an Identification Friend or Foe (IFF) transponder waveform or an IFF interrogator waveform.

12. The computer program product of claim 10, wherein applying the frequency bin interpolation process includes: determining nominal frequencies of the one or more magnitude peaks based on a first frequency resolution of the FFT; translating the nominal frequencies to frequency index vector having a second frequency resolution higher than the first frequency resolution to produce translated frequency values; determining frequency index offset values based on relative magnitudes between the one or more magnitude peaks and magnitude values of frequencies adj acent to the nominal frequencies; and determining the estimated frequencies of the one or more interfering signals based on the translated frequency values and the frequency index offset values.

13. The computer program product of claim 10, wherein applying the FFT to the input signal includes applying an N-point windowed FFT.

14. The computer program product of claim 13, wherein the process further comprises applying an exponential averaging bin filter to the FFT output data.

15. A radio frequency (RF) system comprising the computer program product of claim 10.

16. A radio frequency (RF) Identification Friend or Foe (IFF) system comprising: an input port configured to receive an IFF input signal, the IFF input signal including at least one of an IFF transponder waveform or an IFF interrogator waveform; an output port; and an adaptive filter coupled between the input port and the output port and configured to provide a filtered signal at the output port, the adaptive filter including a plurality of infinite impulse response (HR) filters coupled in series between the input port and the output port and configured to filter the IFF input signal to produce the filtered signal at the output port, and an analysis module configured to determine a set of corresponding filter coefficients for each of the plurality of HR filters based on detecting one or more interfering signals in the IFF input signal, and to provide the set of corresponding filter coefficients to the plurality of HR filters to update a center notch frequency and a bandwidth of the plurality of HR filters using the set of corresponding filter coefficients.

17. The RF IFF system of claim 16, wherein the analysis module comprises a field programmable gate array (FPGA) configured to apply a fast Fourier transform (FFT) to the IFF input signal to produce FFT output data representative of frequency content of the IFF input signal.

18. The RF IFF system of claim 17, wherein the analysis module further comprises: a memory configured to store the FFT output data; at least one processor coupled to the memory; and at least one computer readable medium storing program instructions executable by the at least one processor to control the analysis module to analyze the FFT output data to detect the one or more interfering signals, determine estimated frequencies of the one or more interfering signals, and determine the set of corresponding fdter coefficients based on the estimated frequencies of the one or more interfering signals using a look-up table.

19. The RF IFF system of claim 18, wherein at least one computer readable medium further stores program instructions executable by the at least one processor to control the analysis module to apply a frequency bin interpolation process to the FFT output data to determine the estimated frequencies of the one or more interfering signals.

20. The RF IFF system of claim 19, wherein applying the frequency bin interpolation process includes: determining nominal frequencies of one or more magnitude peaks in the FFT output data based on a first frequency resolution of the FFT, the one or more magnitude peaks corresponding to the one or more interfering signals; translating the nominal frequencies to frequency index vector having a second frequency resolution higher than the first frequency resolution to produce translated frequency values; determining frequency index offset values based on relative magnitudes between the one or more magnitude peaks and magnitude values of frequencies adj acent to the nominal frequencies; and determining the estimated frequencies of the one or more interfering signals based on the translated frequency values and the frequency index offset values.

21. The RF IFF system of claim 16, wherein the FPGA further includes: an up-converter coupled to the input port and configured to up-convert the IFF input signal received at the input port to an intermediate frequency (IF) to provide a real IF input signal and a complex IF input signal, the up-converter being configured to provide the real IF input signal to the analysis module and to provide the complex IF input signal to the plurality of HR filters; and a down-converter coupled between the plurality of HR filters and the output port and configured to down-convert the filtered output signal in frequency to baseband.