WO2024202987A1 - Semiconductor device - Google Patents

Abstract

This semiconductor device comprises: an IGBT region and a diode region that are formed in a semiconductor layer; and a plurality of gate wires that are formed on a first main surface of the semiconductor layer, wherein one of the IGBT region and the diode region is a reference region and the other is a different region that differs from the reference region, in a predetermined region among active regions that include the IGBT region and the diode region, the reference region facing the different region in a first direction that is perpendicular to an extension direction of a gate trench in a plan view, and, in a predetermined region among the active regions the reference region further facing the different region in a second direction that is parallel to the extension direction of the gate trench in a plan view with a first gate wire that is included in the plurality of gate wires interposed therebetween.

Description

Semiconductor Device Related Applications

This application corresponds to Patent Application No. 2023-059174 filed with the Japan Patent Office on March 31, 2023, the entire disclosure of which is incorporated herein by reference.

This disclosure relates to a semiconductor device including an IGBT region and a diode region.

Patent Document 1 discloses an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) as an example of a semiconductor device. The RC-IGBT includes an IGBT region and a diode region fabricated in a common semiconductor layer. The IGBT region includes an IGBT. The diode region includes a diode.

International Publication No. 2019/230851

One embodiment of the present disclosure provides a semiconductor device that can suppress localized increases in heat generation in an RC-IGBT.

An embodiment of the present disclosure provides a semiconductor device including a semiconductor layer having a first main surface and a second main surface on the opposite side thereof, an IGBT region formed in the semiconductor layer, the IGBT region having a gate trench formed therein, a diode region formed in the semiconductor layer, and a plurality of gate wirings formed on the first main surface. In a predetermined region of an active region including the IGBT region and the diode region, one of the IGBT region and the diode region is a reference region, and the other is a heterogeneous region different from the reference region. The reference region faces the heterogeneous region in a first direction perpendicular to the extension direction of the gate trench in a plan view. In a predetermined region of the active region, the reference region further faces the heterogeneous region in a second direction parallel to the extension direction of the gate trench in a plan view, sandwiching a first gate wiring included in the plurality of gate wirings.

According to one embodiment of the present disclosure, a semiconductor device can be provided that can suppress an increase in localized heat generation in an RC-IGBT.

FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view showing a schematic structure of a first main surface of the semiconductor device. FIG. 3 is a bottom view showing a schematic structure of the second main surface of the semiconductor device. FIG. 4 is an enlarged view of a portion enclosed by a dashed line IV in FIG. FIG. 5A is an enlarged view of a portion surrounded by a dashed line VA in FIG. FIG. 5B is an enlarged view of the portion surrounded by the dashed dotted line VB in FIG. 5A. FIG. 6 is an enlarged view of a portion surrounded by a dashed line VI in FIG. FIG. 7 is an enlarged view of a portion surrounded by a dashed line VII in FIG. FIG. 8 is an enlarged view of the portion surrounded by the dashed line VIII in FIG. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. FIG. 10 is a cross-sectional view taken along line X-X of FIG. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. FIG. 12 is a schematic plan view of a semiconductor package including the semiconductor device. FIG. 13 is a cross-sectional view showing the mounting structure of the semiconductor package of FIG. FIG. 14 is a bottom view for explaining a semiconductor device according to a modified example in which the configuration of the collector region and the cathode region is changed. FIG. 15 is a cross-sectional view of a semiconductor device according to a modification of FIG. 14, and corresponds to FIG. FIG. 16 is a schematic plan view of a semiconductor device according to a second embodiment of the present disclosure. FIG. 17 is a plan view showing a schematic structure of the first main surface of the semiconductor device. FIG. 18 is a schematic plan view of a semiconductor device according to a third embodiment of the present disclosure. FIG. 19 is a plan view showing a schematic structure of the first main surface of the semiconductor device. FIG. 20 is a schematic plan view of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 21 is a plan view showing a schematic structure of the first main surface of the semiconductor device. FIG. 22 is a schematic cross-sectional view of a semiconductor package including the semiconductor device.

FIG. 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment of the present disclosure. FIG. 2 is a plan view showing a schematic structure of a first main surface 3 of the semiconductor device 1. FIG. 3 is a bottom view showing a schematic structure of a second main surface 4 of the semiconductor device 1. FIG. 4 is an enlarged view of a portion surrounded by dashed line IV in FIG. 1. FIG. 5A is an enlarged view of a portion surrounded by dashed line VA in FIG. 1. FIG. 5B is an enlarged view of a portion surrounded by dashed line VB in FIG. 5A.

The semiconductor device 1 is an electronic component having an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) that has an IGBT and a diode integrated together.

Referring to Figures 1 to 3, the semiconductor device 1 includes a semiconductor layer 2 having a rectangular parallelepiped shape. The semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D that connect the first main surface 3 and the second main surface 4.

The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view (hereinafter simply referred to as "plan view") seen from their normal direction Z. The side surface 5A and the side surface 5C extend along the first direction X and face a second direction Y that intersects with the first direction X. The side surface 5B and the side surface 5D extend along the second direction Y and face the first direction X. Specifically, the second direction Y is orthogonal (perpendicular) to the first direction X. The second direction Y includes one side Y1 and the other side Y2. The one side Y1 coincides with the upper side of the paper in FIG. 1. The other side Y2 coincides with the lower side of the paper in FIG. 1.

The semiconductor layer 2 includes an active region 6 and an outer region 7. The active region 6 is a region in which an RC-IGBT is formed. The active region 6 is set in the center of the semiconductor layer 2, spaced from the side surfaces 5A to 5D toward the inner region in a plan view. The active region 6 may be set in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view. The thickness of the semiconductor layer 2 may be 50 μm or more and 200 μm or less.

The outer region 7 is the region outside the active region 6. The outer region 7 extends in a band shape along the periphery of the active region 6 in a planar view. Specifically, the outer region 7 is endless (square ring shape) surrounding the active region 6 in a planar view.

The active region 6 includes an IGBT region 8 and a diode region 9. In Figures 2 and 3, the IGBT region 8 is shown by hatching for clarity. The IGBT region 8 is the region in which the IGBT is formed. The diode region 9 is the region in which the diode is formed.

The active region 6 specifically includes an RC-IGBT array (region array) 12. A plurality of RC-IGBT arrays 12 (six in this embodiment) are formed at intervals in the second direction Y. The RC-IGBT array 12 has a first end on one side (side surface 5B side) and a second end on the other side (side surface 5D side). The RC-IGBT array 12 has a loop array that repeatedly includes IGBT regions 8, diode regions 9, IGBT regions 8, diode regions 9, etc., that are arranged in a line along the first direction X from the first end to the second end. In the RC-IGBT array 12, a plurality of IGBT regions 8 and a plurality of diode regions 9 are alternately arranged along the first direction X.

In the active region 6, a plurality of IGBT regions 8 are distributed and arranged. The IGBT regions 8 are formed at intervals along the first direction X and the second direction Y. The IGBT regions 8 are arranged in a staggered pattern in a plan view. Specifically, each of the IGBT regions 8 is formed in a rectangular shape extending along the second direction Y. In this embodiment, the IGBT regions 8 have the same width WG (see FIG. 4).

In addition, a plurality of diode regions 9 are distributed and arranged in the active region 6. Specifically, the plurality of diode regions 9 are each formed so as to be adjacent to an IGBT region 8 in the first direction X. The plurality of diode regions 9 are formed at intervals along the first direction X and the second direction Y. The plurality of diode regions 9 are arranged in a staggered manner in a plan view. Specifically, the diode regions 9 are each formed in a rectangular shape extending along the second direction Y. In this embodiment, the plurality of diode regions 9 have the same width WD. In this embodiment, the plurality of IGBT regions 8 and the plurality of diode regions 9 are each arranged in a staggered manner throughout the active region 6.

In this embodiment, the length of each diode region 9 is shorter than the length of each IGBT region 8. Therefore, the planar area of each diode region 9 is smaller than the planar area of each IGBT region 8. In a planar view, the area ratio of the diode region 9 to the active region 6 is 25% or more and 45% or less. In other words, in a planar view, the area ratio of the IGBT region 8 to the active region 6 is 55% or more and 75% or less.

The multiple (e.g., six) RC-IGBT arrays 12 include, in order from one side Y1 in the second direction Y, a first array 12A, a second array 12B, a third array 12C, a fourth array 12D, a fifth array 12E, and a sixth array 12F. The column widths (widths in the second direction Y) of the first array 12A and the sixth array 12F are the same. The column widths (widths in the second direction Y) of the second array 12B and the fifth array 12E are the same. The column widths (widths in the second direction Y) of the third array 12C and the fourth array 12D are the same.

The first array 12A, the third array 12C, and the fifth array 12E are arranged in the same array pattern. The second array 12B, the fourth array 12D, and the sixth array 12F are arranged in the same array pattern. The second array 12B, the fourth array 12D, and the sixth array 12F are offset from the first array 12A, the third array 12C, and the fifth array 12E in the first direction X of the IGBT regions 8 and the diode regions 9.

In this embodiment, the first ends of the first array 12A, the third array 12C, and the fifth array 12E in the first direction X are formed by the IGBT region 8. The first ends of the first array 12A, the third array 12C, and the fifth array 12E may be formed by the diode region 9. In this embodiment, the second ends of the first array 12A, the third array 12C, and the fifth array 12E in the first direction X are formed by the IGBT region 8. The second ends of the first array 12A, the third array 12C, and the fifth array 12E may be formed by the diode region 9.

In this embodiment, the first ends of the second array 12B, the fourth array 12D, and the sixth array 12F in the first direction X are formed by the IGBT region 8. The first ends of the second array 12B, the fourth array 12D, and the sixth array 12F may be formed by the diode region 9. In this embodiment, the second ends of the second array 12B, the fourth array 12D, and the sixth array 12F in the first direction X are formed by the diode region 9. The second ends of the second array 12B, the fourth array 12D, and the sixth array 12F in the first direction X may be formed by the IGBT region 8.

Referring to FIG. 4, the width WG of each IGBT region 8 may be 10 μm or more and 1000 μm or less. The width WG may be 100 μm or more. It is preferable that the width WG is 200 μm or more.

The width WD of each diode region 9 may be less than or equal to the width WG of each IGBT region 8. The width WD is the width of the diode region 9 in the first direction X. It is preferable that the width WD of each diode region 9 is less than the width WG of each IGBT region 8.

Referring to Figures 1 and 2, the active area 6 further includes a sensor area 11 in which a temperature sensor is formed. The sensor area 11 is formed in a region between two RC-IGBT arrays 12 adjacent to each other in the second direction Y. In this embodiment, the sensor area 11 is formed in the center of the active area 6.

The semiconductor device 1 further includes an emitter terminal electrode 13 (see the dashed line in FIG. 1). The emitter terminal electrode 13 is formed on the first main surface 3 of the semiconductor layer 2 in the active region 6. The emitter terminal electrode 13 transmits an emitter signal to the active region 6 (IGBT region 8). The emitter signal may be a reference potential or a ground potential.

Referring to FIG. 1, the semiconductor device 1 further includes a plurality of terminal electrodes 14, 15, 16, 17, and 18 (five in this embodiment) formed on the first main surface 3 of the semiconductor layer 2 in the outer region 7. The multiple terminal electrodes 14 to 18 are arranged at intervals along the side surface 5D. The multiple terminal electrodes 14 to 18 are formed in a quadrangular shape in a plan view.

In this embodiment, the multiple terminal electrodes 14 to 18 include a gate terminal electrode 14, a first sense terminal electrode 15, a second sense terminal electrode 16, a current detection terminal electrode 17, and an open terminal electrode 18. The gate terminal electrode 14 transmits a gate signal to the active region 6 (IGBT region 8). The first sense terminal electrode 15 and the second sense terminal electrode 16 transmit a control signal for controlling the sensor region 11 (temperature sensor). The current detection terminal electrode 17 is an electrode for detecting a current flowing through the active region 6 and extracting it to the outside. The open terminal electrode 18 is in an electrically floating state. The gate terminal electrode 14, the first sense terminal electrode 15, the second sense terminal electrode 16, the current detection terminal electrode 17, and the open terminal electrode 18 may be arranged in any manner. In the example of FIG. 1, the open terminal electrode 18, the current detection terminal electrode 17, the gate terminal electrode 14, the first sense terminal electrode 15, and the second sense terminal electrode 16 are arranged in this order from the side surface 5A to the side surface 5C.

The semiconductor device 1 further includes a gate wiring 19 electrically connected to the gate terminal electrode 14. The gate wiring 19 is also called a gate finger. The gate wiring 19 extends from the outer region 7 toward the active region 6. The gate wiring 19 transmits a gate signal applied to the gate terminal electrode 14 to the active region 6 (IGBT region 8). Specifically, the gate wiring 19 includes a first region 19a located in the outer region 7 and a second region 19b located in the active region 6. The first region 19a is electrically connected to the gate terminal electrode 14. In this embodiment, the first region 19a is selectively routed in a region on the side surface 5D side in the outer region 7.

A plurality of second regions 19b (five in this embodiment) are formed in the active region 6. The second regions 19b are formed at intervals along the second direction Y. The second regions 19b are each formed in a region between two adjacent RC-IGBT arrays 12. The second regions 19b each extend from the region on the side face 5D side to the region on the side face 5B side in the outer region 7. The second regions 19b are connected to the first region 19a in the outer region 7. The second regions 19b transmit gate signals to one or both of the two adjacent RC-IGBT arrays 12.

The gate signal applied to the gate terminal electrode 14 is transmitted to the second region 19b via the first region 19a. This causes the gate signal to be transmitted to the active region 6 (IGBT region 8) via the second region 19b.

The first sense wiring 20 is electrically connected to the first sense terminal electrode 15. The first sense wiring 20 extends from the outer region 7 toward the sensor region 11. The first sense wiring 20 transmits a control signal for the temperature sensor. Specifically, the first sense wiring 20 includes a first region 20a located in the outer region 7 and a second region 20b located in the active region 6. The first region 20a is electrically connected to the first sense terminal electrode 15. The second region 20b is electrically connected to the temperature sensor in the sensor region 11. The second region 20b is connected to the first region 20a in the outer region 7. An electrical signal applied to the first sense terminal electrode 15 is transmitted to the second region 20b via the first region 20a. As a result, an electrical signal is transmitted to the temperature sensor via the second region 20b.

The second sense wiring 21 is electrically connected to the second sense terminal electrode 16. The second sense wiring 21 extends from the outer region 7 toward the sensor region 11. The second sense wiring 21 transmits a control signal for the temperature sensor. Specifically, the second sense wiring 21 includes a first region 21a located in the outer region 7 and a second region 21b located in the active region 6. The first region 21a is electrically connected to the second sense terminal electrode 16. The second region 21b is electrically connected to the temperature sensor in the sensor region 11. The second region 21b is connected to the first region 21a in the outer region 7. An electrical signal applied to the second sense terminal electrode 16 is transmitted to the second region 21b via the first region 21a. As a result, an electrical signal is transmitted to the temperature sensor via the second region 21b.

In the region between adjacent RC-IGBT arrays 12 where the sensor region 11 is formed, a gate wiring 19, a first sense wiring 20, and a second sense wiring 21 are formed. The gate wiring 19, the first sense wiring 20, and the second sense wiring 21 run parallel to each other in the region between two adjacent RC-IGBT arrays 12.

With reference to Figures 1 and 5A, the following description focuses on the individual IGBT regions 8 included in the active region 6. For example, take the third IGBT region 8B from the other side (side surface 5D) included in the second array 12B as an example.

The IGBT region 8B is adjacent to two diode regions 9B on both sides in the first direction X (horizontal direction on the paper). The IGBT region 8B is further adjacent to two diode regions 9A, 9C on both sides in the second direction Y (vertical direction on the paper). Meanwhile, the IGBT region 8B is adjacent to two IGBT regions 8A and two IGBT regions 8C that are independent of the IGBT region 8B on both sides of two diagonal directions that intersect both the first direction X and the second direction Y. This forms a unit array UA of a staggered pattern of IGBT regions 8 and diode regions 9 that covers the entire active region 6. In the unit array UA, the IGBT region 8B located at the center is the reference IGBT region that serves as the reference region. In the unit array UA, the four diode regions 9A, 9C on both sides of the first direction X (horizontal direction on the paper) and the second direction Y (vertical direction on the paper) as viewed from the IGBT region 8B are heterogeneous diode regions as heterogeneous regions. In addition, in the unit array UA, the four IGBT regions 8A, 8C adjacent to the IGBT region 8B on both sides of two diagonal directions intersecting both the first direction X and the second direction Y as viewed from the IGBT region 8B and independent from the IGBT region 8B are homogeneous IGBT regions as homogeneous regions.

Specifically, the IGBT region 8B is adjacent to each of the two diode regions 9B included in the same RC-IGBT array (second array 12B) in the first direction X. In other words, the IGBT region 8B faces each of the two diode regions 9B on either side of the first direction X, with a boundary region 72 (see also FIG. 10) sandwiched therebetween, in the first direction X.

The IGBT region 8B faces one diode region 9A included in the RC-IGBT array (first array 12A) adjacent to one side Y1 in the second direction Y, and one or more second regions 19b of the gate wiring 19 (one in the example of FIG. 5A. Hereinafter, sometimes referred to as "first gate wiring 19bA" (see FIG. 5A)). The IGBT region 8B faces each of the two IGBT regions 8A on both sides of the diode region 9A in the first direction X, in the second direction Y, with the first gate wiring 19bA between them. The IGBT region 8A is an IGBT region independent of the IGBT region 8B.

Referring to Figures 5A and 5B, the IGBT region 8B faces the IGBT region 8A on one side (side surface 5B side) with a first facing width (facing width) W1. The IGBT region 8B faces the IGBT region 8A on the other side (side surface 5D side) with a second facing width (facing width) W2. The combined width of the first facing width W1 and the second facing width W2 is narrower than the width WG of the IGBT region 8. In the example of Figures 5A and 5B, the first facing width W1 is the same as the second facing width W2. The first facing width W1 may be wider than the second facing width W2. The first facing width W1 may be narrower than the second facing width W2.

Referring to FIG. 5B, the ratio W1/WG of the first opposing width W1 to the width WG of the IGBT region 8 (IGBT region 8B) may be 0.001 or more and less than 0.5. W1/WG may be 0.001 or more and less than 0.01, 0.01 or more and less than 0.05, 0.05 or more and less than 0.1, 0.1 or more and less than 0.15, 0.15 or more and less than 0.2, 0.2 or more and less than 0.25, 0.25 or more and less than 0.3, 0.3 or more and less than 0.35, 0.35 or more and less than 0.4, 0.4 or more and less than 0.45, or 0.45 or more and less than 0.5.

The first opposing width W1 may be 0.1 μm or more and less than 500 μm. The first opposing width W1 may be 0.1 μm or more and less than 50 μm, 50 μm or more and less than 100 μm, 100 μm or more and less than 150 μm, 150 μm or more and less than 200 μm, 200 μm or more and less than 250 μm, 250 μm or more and less than 300 μm, 300 μm or more and less than 350 μm, 350 μm or more and less than 400 μm, 400 μm or more and less than 450 μm, or 450 μm or more and less than 500 μm.

The first opposing width W1 may be wider than the first interval W5 between the IGBT region 8 and the diode region 9 that face each other in the second direction Y. The first opposing width W1 may be the same as the first interval W5. The first opposing width W1 may be narrower than the first interval W5.

The first opposing width W1 may be wider than the second interval W4 between two IGBT regions 8 opposing in the second direction Y. The first opposing width W1 may be the same as the second interval W4. The first opposing width W1 may be narrower than the second interval W4.

The first opposing width W1 may be wider than the line width W3 of the second region 19b of the gate wiring 19. The first opposing width W1 may be the same as the line width W3 of the second region 19b. The first opposing width W1 may be narrower than the line width W3 of the second region 19b.

The ratio W2/WG of the second opposing width W2 to the width WG of the IGBT region 8 (IGBT region 8B) may be 0.001 or more and less than 0.5. W2/WG may be 0.001 or more and less than 0.01, 0.01 or more and less than 0.05, 0.05 or more and less than 0.1, 0.1 or more and less than 0.15, 0.15 or more and less than 0.2, 0.2 or more and less than 0.25, 0.25 or more and less than 0.3, 0.3 or more and less than 0.35, 0.35 or more and less than 0.4, 0.4 or more and less than 0.45, or 0.45 or more and less than 0.5.

The second opposing width W2 may be 0.1 μm or more and 500 μm or less. The second opposing width W2 may be 0.1 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 350 μm or less, 350 μm or more and 400 μm or less, 400 μm or more and 450 μm or less, or 450 μm or more and less than 500 μm.

The second opposing width W2 may be wider than the first interval W5 between the IGBT region 8 and the diode region 9 that face each other in the second direction Y. The second opposing width W2 may be the same as the first interval W5. The second opposing width W2 may be narrower than the first interval W5.

The second opposing width W2 may be wider than the second interval W4 between two IGBT regions 8 opposing in the second direction Y. The second opposing width W2 may be the same as the second interval W4. The second opposing width W2 may be narrower than the second interval W4.

The second opposing width W2 may be wider than the line width W3 of the second region 19b of the gate wiring 19. The second opposing width W2 may be the same as the line width W3 of the second region 19b. The second opposing width W2 may be narrower than the line width W3 of the second region 19b.

1 and 5A, the IGBT region 8B faces one diode region 9C included in the RC-IGBT array 12 (third array 12C) adjacent to it on the other side Y2 of the second direction Y, across one or more second regions 19b of the gate wiring 19 (one in the example of FIG. 5A; hereinafter, sometimes referred to as "second gate wiring 19bB" (see FIG. 5A)). The IGBT region 8B faces each of the two IGBT regions 8C on either side of the diode region 9B in the first direction X, across the second gate wiring 19bB. The second gate wiring 19bB is another gate wiring extending parallel to the first gate wiring 19bA. The IGBT region 8 and the diode region 9 included in one RC-IGBT array 12 (third array 12C) are sandwiched in the second direction Y by the first gate wiring 19bA and the second gate wiring 19bB. The IGBT region 8C is an IGBT region independent of the IGBT region 8B.

The IGBT region 8B faces the IGBT region 8C on one side (side surface 5B) of the diode region 9C at a first facing width W1. The IGBT region 8B faces the IGBT region 8C on the other side (side surface 5D) of the diode region 9C at a second facing width W2.

The total width (first opposing width W1+second opposing width W2) of the portion where the IGBT region 8B, which is the reference IGBT region, faces the IGBT regions 8A and 8C, which are homogeneous IGBT regions, in the second direction Y is narrow. In the unit array UA, when a current flows through the IGBT region 8, the amount of heat generated does not increase locally in the unit array UA. In the unit array UA, when a current flows through the diode region 9, the amount of heat generated does not increase locally in the unit array UA.

With reference to Figures 5A and 5B, the following can be said about the arrangement of the IGBT regions 8 and diode regions 9 included in the multiple RC-IGBT arrays 12. That is, the multiple IGBT regions 8 included in each of the arrays 12A to 12F face in the second direction Y with each of the multiple diode regions 9 included in the RC-IGBT array (arrays 12A to 12F) adjacent to that array 12A to 12F in the second direction Y. Also, the multiple diode regions 9 included in each of the arrays 12A to 12F face in the second direction Y with each of the multiple IGBT regions 8 included in the RC-IGBT array (arrays 12A to 12F) adjacent to that array 12A to 12F in the second direction Y.

In the IGBT region 8 and the diode region 9 facing the second direction Y, the center of the IGBT region 8 in the first direction X and the center of the diode region 9 in the first direction X are aligned with each other in the first direction X. In other words, a plurality of IGBT regions 8 and a plurality of diode regions 9 are arranged alternately along the second direction Y.

In addition, one IGBT region 8 included in each of the arrays 12A to 12F is further opposed in the second direction Y to two IGBT regions 8 included in the RC-IGBT array (arrays 12A to 12F) adjacent to that array 12A to 12F in the second direction Y. The total width of the portion where one IGBT region 8 faces two IGBT regions 8 in the second direction Y (first opposing width W1 + second opposing width W2) is narrower than the width WG of the IGBT region 8. In other words, the total width of the portion where the IGBT regions 8 continuous in the second direction Y face the second direction Y in the active region 6 (first opposing width W1 + second opposing width W2) is narrow.

A diode region 9 included in each of the arrays 12A to 12F does not face, in the second direction Y, the diode region 9 included in the RC-IGBT array (arrays 12A to 12F) adjacent to that array 12A to 12F in the second direction Y. Therefore, the diode region 9 is not continuous in the second direction Y.

Referring to FIG. 3, the semiconductor device 1 further includes a collector terminal electrode 32 (see the dashed line in FIG. 3) formed on the second main surface 4 of the semiconductor layer 2. Specifically, the collector terminal electrode 32 is electrically connected to the IGBT region 8 (collector region 34 described next) and the diode region 9 (cathode region 61 described next).

The collector terminal electrode 32 forms an ohmic contact with the second main surface 4. The collector terminal electrode 32 transmits a collector signal to the IGBT region 8 and the diode region 9. The collector terminal electrode 32 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The collector terminal electrode 32 may have a single layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The collector terminal electrode 32 may have a layered structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are layered in any manner.

Each IGBT region 8 includes a p-type (second conductivity type) collector region 34 formed in a surface layer portion of the second main surface 4 of the semiconductor layer 2. The collector region 34 is exposed from the second main surface 4. The p-type impurity concentration of the collector region 34 may be 1.0×10 ¹⁵ cm ⁻³ or more and 1.0×10 ¹⁸ cm ⁻³ or less. The collector region 34 forms an ohmic contact with the collector terminal electrode 32. In this embodiment, the collector region 34 is formed in the surface layer portion of the second main surface 4 throughout the entire IGBT region 8.

Each diode region 9 includes an n ⁺ type cathode region 61 formed in a surface layer portion of the second main surface 4 of the semiconductor layer 2. The n-type impurity concentration of the cathode region 61 is higher than the n-type impurity concentration of the drift region 30 (see FIG. 9 and the like) described below. The cathode region 61 is exposed from the second main surface 4. The n-type impurity concentration of the cathode region 61 may be 1.0×10 ¹⁹ cm ⁻³ or more and 1.0×10 ²⁰ cm ⁻³ or less. The cathode region 61 forms an ohmic contact with the collector terminal electrode 32. In this embodiment, the cathode region 61 is formed in the surface layer portion of the second main surface 4 over the entire IGBT region 8.

Figure 6 is an enlarged view of the portion surrounded by dashed line VI in Figure 4. Figure 7 is an enlarged view of the portion surrounded by dashed line VII in Figure 6. Figure 8 is an enlarged view of the portion surrounded by dashed line VIII in Figure 6. Figure 9 is a cross-sectional view taken along line IX-IX in Figure 7. Figure 10 is a cross-sectional view taken along line X-X in Figure 8. Figure 11 is a cross-sectional view taken along line XI-XI in Figure 7.

9 to 11, the semiconductor device 1 further includes an n ^-type drift region 30 formed inside the semiconductor layer 2. Specifically, the drift region 30 is formed over the entire semiconductor layer 2 in the first direction X and the second direction Y. The drift region 30 is formed in a surface layer portion of the first main surface 3 of the semiconductor layer 2 in the normal direction Z (thickness direction of the semiconductor layer 2). The n-type (first conductivity type) impurity concentration of the drift region 30 may be not less than 1.0×10 ¹³ cm ^-3 and not more than 1.0×10 ¹⁵ cm ^-3 .

In this embodiment, the semiconductor layer 2 has a single-layer structure including an n ^- type semiconductor substrate 31. The semiconductor substrate 31 may be a silicon FZ (Floating Zone) substrate formed through an FZ method. The drift region 30 is formed by the semiconductor substrate 31.

The semiconductor device 1 includes an n-type buffer layer 33 formed in a surface layer portion of the second main surface 4 of the semiconductor layer 2. The buffer layer 33 may be formed over the entire surface layer portion of the second main surface 4. The n-type impurity concentration of the buffer layer 33 is higher than the n-type impurity concentration of the drift region 30. The n-type impurity concentration of the buffer layer 33 may be 1.0×10 ¹⁵ cm ⁻³ or more and 1.0×10 ¹⁷ cm ⁻³ or less. The thickness of the buffer layer 33 may be 0.5 μm or more and 30 μm or less.

Each IGBT region 8 includes a p-type (second conductivity type) collector region 34 formed in a surface layer portion of the second main surface 4 of the semiconductor layer 2. The collector region 34 is exposed from the second main surface 4. The collector region 34 may be formed throughout the entire IGBT region 8 in the surface layer portion of the second main surface 4. The p-type impurity concentration of the collector region 34 may be 1.0×10 ¹⁵ cm ^-3 or more and 1.0×10 ¹⁸ cm ^-3 or less. The collector region 34 forms an ohmic contact with the collector terminal electrode 32.

Referring to Figures 6 to 11, each IGBT region 8 includes a plurality of FET structures 35 formed on the first main surface 3 of the semiconductor layer 2. Specifically, the FET structures 35 include trench gate structures 36 formed on the first main surface 3. A plurality of trench gate structures 36 are formed at intervals along the first direction X in the IGBT region 8. The distance between two trench gate structures 36 adjacent to each other in the first direction X may be 1 μm or more and 8 μm or less. In Figures 6 to 8, the trench gate structures 36 are indicated by hatching.

The multiple trench gate structures 36 are formed in a band shape extending along the second direction Y in a plan view. The multiple trench gate structures 36 are formed in a stripe shape as a whole. Each of the multiple trench gate structures 36 has one end on one side of the second direction Y and the other end on the other side of the second direction Y.

Referring to Figures 4 and 5B, the trench gate structure 36 includes a first outer trench gate structure 37 and a second outer trench gate structure 38. The first outer trench gate structure 37 extends along the first direction X and connects one ends of the multiple trench gate structures 36. The second outer trench gate structure 38 extends along the first direction X and connects the other ends of the multiple trench gate structures 36.

The first outer trench gate structure 37 and the second outer trench gate structure 38 have the same structure as the trench gate structure 36, except that they extend in different directions. Below, the structure of the trench gate structure 36 will be described, and a description of the structures of the first outer trench gate structure 37 and the second outer trench gate structure 38 will be omitted.

Referring to Figures 9 to 11, each trench gate structure 36 includes a gate trench 39, a gate insulating layer 40, and a gate conductive layer 41. The gate trench 39 is formed in the first main surface 3. The gate trench 39 includes a sidewall and a bottom wall. The sidewall of the gate trench 39 may be formed perpendicular to the first main surface 3.

The sidewalls of the gate trench 39 may slope downward from the first main surface 3 toward the bottom wall. The gate trench 39 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The bottom wall of the gate trench 39 may be formed parallel to the first main surface 3. The bottom wall of the gate trench 39 may be formed in a curved shape toward the second main surface 4. The gate trench 39 includes a bottom wall edge portion. The bottom wall edge portion connects the sidewalls and bottom wall of the gate trench 39. The bottom wall edge portion may be formed in a curved shape toward the second main surface 4.

The depth D1 of the gate trench 39 may be 2 μm or more and 10 μm or less. The depth D1 of the gate trench 39 may be defined as the distance between the deepest depth position of the bottom wall of the gate trench 39 and the first main surface 3. The width of the gate trench 39 may be 0.5 μm or more and 3 μm or less. The width of the gate trench 39 is the width of the gate trench 39 in the first direction X.

The gate insulating layer 40 is formed in the form of a film along the inner wall of the gate trench 39. The gate insulating layer 40 defines a recess space within the gate trench 39. In this embodiment, the gate insulating layer 40 includes a silicon oxide film. The gate insulating layer 40 may include a silicon nitride film instead of or in addition to the silicon oxide film.

The gate conductive layer 41 is embedded in the gate trench 39 with the gate insulating layer 40 sandwiched therebetween. Specifically, the gate conductive layer 41 is embedded in a recess space defined by the gate insulating layer 40 in the gate trench 39. The gate conductive layer 41 is controlled by a gate signal. The gate conductive layer 41 may include conductive polysilicon.

The gate conductive layer 41 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The gate conductive layer 41 has an upper end portion located on the opening side of the gate trench 39. The upper end portion of the gate conductive layer 41 is located on the bottom wall side of the gate trench 39 with respect to the first main surface 3.

A recess is formed at the upper end of the gate conductive layer 41, recessed toward the bottom wall of the gate trench 39. The recess at the upper end of the gate conductive layer 41 is formed in a tapered shape toward the bottom wall of the gate trench 39. The upper end of the gate conductive layer 41 has a narrowed portion on the inside of the gate conductive layer 41.

9 and 10, the FET structure 35 includes a p-type body region 45 formed in a surface layer portion of the first main surface 3 of the semiconductor layer 2. The p-type impurity concentration of the body region 45 may be 1.0×10 ¹⁷ cm ⁻³ or more and 1.0×10 ¹⁸ cm ⁻³ or less. The body region 45 is formed on both sides of the trench gate structure 36. The body region 45 is formed in a strip shape extending along the trench gate structure 36 in a plan view. The body region 45 is exposed from a side wall of the gate trench 39. The bottom of the body region 45 is formed in a region between the first main surface 3 and the bottom wall of the gate trench 39 with respect to the normal direction Z.

The FET structure 35 includes an n ⁺ type emitter region 46 formed in a surface layer portion of the body region 45. The n-type impurity concentration of the emitter region 46 is higher than the n-type impurity concentration of the drift region 30. The n-type impurity concentration of the emitter region 46 may be 1.0×10 ¹⁹ cm ⁻³ or more and 1.0×10 ²⁰ cm ⁻³ or less.

In this embodiment, the FET structure 35 includes a plurality of emitter regions 46 formed on both sides of the trench gate structure 36. The emitter regions 46 are formed in a strip shape extending along the trench gate structure 36 in a plan view. The emitter regions 46 are exposed from the first main surface 3 and the sidewalls of the gate trench 39. The bottoms of the emitter regions 46 are formed in a region between the upper end of the gate conductive layer 41 and the bottom of the body region 45 in the normal direction Z.

In this embodiment, the FET structure 35 includes an n ⁺ type carrier storage region 47 formed in a region of the semiconductor layer 2 on the second main surface 4 side with respect to the body region 45. The n type impurity concentration of the carrier storage region 47 is higher than the n type impurity concentration of the drift region 30. The n type impurity concentration of the carrier storage region 47 may be 1.0×10 ¹⁵ cm ^-3 or more and 1.0×10 ¹⁷ cm ^-3 or less.

In this embodiment, the FET structure 35 includes a plurality of carrier storage regions 47 formed on both sides of the trench gate structure 36. The carrier storage regions 47 are formed in a strip shape extending along the trench gate structure 36 in a plan view. The carrier storage regions 47 are exposed from the side walls of the gate trench 39. The bottoms of the carrier storage regions 47 are formed in the region between the bottom of the body region 45 and the bottom wall of the gate trench 39 in the normal direction Z.

The carrier storage region 47 prevents carriers (holes) supplied to the semiconductor layer 2 from being drawn back (discharged) to the body region 45. This causes holes to accumulate in the region directly below the FET structure 35 in the semiconductor layer 2. As a result, the on-resistance and on-voltage are reduced.

The FET structure 35 includes a contact trench 48 formed in the first major surface 3 of the semiconductor layer 2. In this embodiment, the FET structure 35 includes a plurality of contact trenches 48 formed on both sides of the trench gate structure 36. The contact trenches 48 expose the emitter region 46. In this embodiment, the contact trenches 48 penetrate the emitter region 46.

The contact trench 48 is formed at a distance from the trench gate structure 36 in the first direction X. The contact trench 48 extends in a strip shape along the trench gate structure 36 in a plan view. In the second direction Y, the length of the contact trench 48 is equal to or less than the length of the trench gate structure 36. Specifically, the length of the contact trench 48 is less than the length of the trench gate structure 36.

The FET structure 35 includes a p ⁺ type contact region 49 formed in a region along the bottom wall of the contact trench 48 in the body region 45. The p-type impurity concentration of the contact region 49 is higher than the p-type impurity concentration of the body region 45. The p-type impurity concentration of the contact region 49 may be 1.0×10 ¹⁹ cm ⁻³ or more and 1.0×10 ²⁰ cm ⁻³ or less.

The contact region 49 is exposed from the bottom wall of the contact trench 48. In a plan view, the contact region 49 extends in a band shape along the contact trench 48. The bottom of the contact region 49 is formed in the region between the bottom wall of the contact trench 48 and the bottom of the body region 45 in the normal direction Z.

Thus, in the FET structure 35, the gate conductive layer 41 faces the body region 45 and the emitter region 46 with the gate insulating layer 40 in between. In this embodiment, the gate conductive layer 41 also faces the carrier storage region 47 with the gate insulating layer 40 in between. The channel of the IGBT is formed in the region between the emitter region 46 and the drift region 30 (carrier storage region 47) in the body region 45. The on/off of the channel is controlled by a gate signal.

Each IGBT region 8 further includes an emitter trench structure 73 formed on the first main surface 3 of the semiconductor layer 2. Specifically, each IGBT region 8 includes a plurality of emitter trench structures 73 formed on both sides of the FET structure 35. The emitter trench structure 73 is formed in a region adjacent to the FET structure 35 in the surface layer portion of the first main surface 3. The emitter trench structure 73 is formed in a band shape extending along the second direction Y in a plan view. The plurality of emitter trench structures 73 are formed in a stripe shape as a whole. The emitter trench structure 73 may be in a band shape parallel to the trench gate structure 36.

6 and 7, in each IGBT region 8, the trench gate structures 36 and the emitter trench structures 73 are arranged alternately at intervals along the first direction X. The trench gate structures 36 and the emitter trench structures 73 may be arranged alternately at equal intervals. The distance between two adjacent trench gate structures 36 and emitter trench structures 73 in the first direction X (first pitch P1 (see FIG. 7)) may be, for example, 1.0 μm or more and 3.5 μm or less.

Referring to Figures 9 and 10, the emitter trench structure 73 includes an emitter trench 74, an emitter insulating layer 75, and an emitter potential electrode layer 76. The emitter trench 74 is formed in the first main surface 3 of the semiconductor layer 2. The emitter trench 74 includes a sidewall and a bottom wall. The sidewall of the emitter trench 74 may be formed perpendicular to the first main surface 3.

The sidewall of the emitter trench 74 may be inclined downward from the first main surface 3 toward the bottom wall. The emitter trench 74 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The emitter region 46, the body region 45, and the carrier storage region 47 are exposed from the sidewall (outer sidewall) of the emitter trench 74 facing the FET structure 35. The bottom wall of the emitter trench 74 may be formed parallel to the first main surface 3. The bottom wall of the emitter trench 74 may be formed in a curved shape toward the second main surface 4. The emitter trench 74 includes a bottom wall edge portion. The bottom wall edge portion connects the sidewall and the bottom wall of the emitter trench 74. The bottom wall edge portion may be formed in a curved shape toward the second main surface 4 of the semiconductor layer 2.

The depth D3 of the emitter trench 74 may be 2 μm or more and 10 μm or less. The depth D3 of the emitter trench 74 may be equal to the depth D1 of the gate trench 39. The width of the emitter trench 74 may be 0.5 μm or more and 3 μm or less. The width of the emitter trench 74 is the width of the emitter trench 74 in the first direction X. The width of the emitter trench 74 may be equal to the width of the gate trench 39.

The emitter insulating layer 75 is formed in the form of a film along the inner wall of the emitter trench 74. The emitter insulating layer 75 defines a recess space within the emitter trench 74. In this embodiment, the emitter insulating layer 75 includes a silicon oxide film. The emitter insulating layer 75 may include a silicon nitride film instead of or in addition to the silicon oxide film.

The emitter potential electrode layer 76 is embedded in the emitter trench 74 with the emitter insulating layer 75 sandwiched therebetween. Specifically, the emitter potential electrode layer 76 is embedded in a recess space defined by the emitter insulating layer 75 in the emitter trench 74. The emitter potential electrode layer 76 may include conductive polysilicon. The emitter potential electrode layer 76 is controlled by an emitter signal.

The emitter potential electrode layer 76 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The emitter potential electrode layer 76 has an upper end portion located on the opening side of the emitter trench 74. The upper end portion of the emitter potential electrode layer 76 is located on the bottom wall side of the emitter trench 74 with respect to the first main surface 3.

A recess is formed at the upper end of the emitter potential electrode layer 76, recessed toward the bottom wall of the emitter trench 74. The recess at the upper end of the emitter potential electrode layer 76 is formed in a tapered shape toward the bottom wall of the emitter trench 74. The upper end of the emitter potential electrode layer 76 has a narrowed portion that is narrowed on the inside of the emitter potential electrode layer 76.

Referring to Figures 6 and 8, each diode region 9 includes a cell isolation structure 63 that defines a diode cell region 69. In Figures 6 and 8, the cell isolation structure 63 is indicated by hatching. Specifically, each diode region 9 includes a plurality of cell isolation structures 63 that define a plurality of diode cell regions 69, respectively.

The multiple cell isolation structures 63 are each formed in the region between multiple adjacent diode cell regions 69. Specifically, the multiple cell isolation structures 63 are each formed in a ring shape (a square ring shape in this embodiment) surrounding the diode cell region 69 in a plan view. The cell isolation structure 63 that divides one diode cell region 69 and the cell isolation structure 63 that divides the other diode cell region 69 are integrally formed in the region between the multiple adjacent diode cell regions 69.

The multiple cell separation structures 63 may be arranged at equal intervals in the first direction X. The multiple cell separation structures 63 are formed in a stripe pattern. The distance between two adjacent cell separation structures 63 in the first direction X (second pitch P2 (see FIG. 8)) may be, for example, 1.0 μm or more and 10.0 μm or less. The second pitch P2 may be the same as the first pitch P1 (see FIG. 7).

In this embodiment, the diode cell regions 69 partitioned by the cell separation structures 63 are formed at intervals along the first direction X in a planar view. The diode cell regions 69 are each formed in a band shape extending along the second direction Y in a planar view. The diode cell regions 69 are formed in a stripe shape as a whole. With respect to the second direction Y, the length of the diode cell region 69 may be equal to or less than the length of the trench gate structure 36. The length of the diode cell region 69 may be less than the length of the trench gate structure 36.

Referring to FIG. 10, the cell isolation structure 63 includes a cell isolation trench 64, a cell isolation insulating layer 65, and a cell isolation electrode layer 66. The cell isolation trench 64 is formed in the first main surface 3. The cell isolation trench 64 includes a sidewall and a bottom wall. The sidewall of the cell isolation trench 64 may be formed perpendicular to the first main surface 3.

The sidewalls of the cell separation trench 64 may slope downward from the first main surface 3 toward the bottom wall. The cell separation trench 64 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The bottom wall of the cell separation trench 64 may be formed parallel to the first main surface 3. The bottom wall of the cell separation trench 64 may be formed in a curved shape toward the second main surface 4. The cell separation trench 64 includes a bottom wall edge portion. The bottom wall edge portion connects the sidewalls and the bottom wall of the cell separation trench 64. The bottom wall edge portion may be formed in a curved shape toward the second main surface 4.

The depth D2 of the cell isolation trench 64 may be 2 μm or more and 10 μm or less. The depth D2 of the cell isolation trench 64 may be defined as the distance between the deepest depth position of the bottom wall of the cell isolation trench 64 and the first main surface 3. The depth D2 of the cell isolation trench 64 may be equal to the depth D1 of the gate trench 39 (see FIG. 9, etc.). The width of the cell isolation trench 64 may be 0.5 μm or more and 3 μm or less. The width of the cell isolation trench 64 is the width of the cell isolation trench 64 in the first direction X. The width of the cell isolation trench 64 may be equal to the width of the gate trench 39.

The cell isolation insulating layer 65 is formed in the form of a film along the inner wall of the cell isolation trench 64. The cell isolation insulating layer 65 defines a recess space within the cell isolation trench 64. In this embodiment, the cell isolation insulating layer 65 includes a silicon oxide film. The cell isolation insulating layer 65 may include a silicon nitride film instead of or in addition to the silicon oxide film.

The cell separation electrode layer 66 is embedded in the cell separation trench 64 with the cell separation insulating layer 65 sandwiched therebetween. Specifically, the cell separation electrode layer 66 is embedded in a recess space defined by the cell separation insulating layer 65 in the cell separation trench 64. The cell separation electrode layer 66 is controlled by an emitter signal. The cell separation electrode layer 66 may include conductive polysilicon.

The cell separation electrode layer 66 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The cell separation electrode layer 66 has an upper end portion located on the opening side of the cell separation trench 64. The upper end portion of the cell separation electrode layer 66 is located on the bottom wall side of the cell separation trench 64 with respect to the first main surface 3.

The upper end of the cell separation electrode layer 66 is tapered toward the first main surface 3. A recess is formed at the upper end of the cell separation electrode layer 66, recessed toward the bottom wall of the cell separation trench 64. The recess in the cell separation electrode layer 66 is tapered toward the bottom wall of the cell separation trench 64.

Each diode region 9 includes ap ⁻ type anode region 62 formed in a surface layer portion of the first main surface 3 of the semiconductor layer 2. The p-type impurity concentration of the anode region 62 may be equal to or lower than the p-type impurity concentration of the body region 45. The p-type impurity concentration of the anode region 62 is preferably lower than the p-type impurity concentration of the body region 45. The p-type impurity concentration of the anode region 62 may be equal to or higher than 1.0×10 ¹⁵ cm ⁻³ and lower than 1.0×10 ¹⁸ cm ⁻³ .

The anode region 62 is formed in each diode cell region 69. Therefore, the multiple anode regions 62 are arranged at equal intervals in the first direction X, and are formed in a striped shape overall. The anode region 62 forms a pn junction 68 with the semiconductor layer 2. This forms a pn junction diode D with the anode region 62 as the anode and the semiconductor layer 2 (cathode region 61) as the cathode. When the pn junction diode D switches from the off state to the on state, a forward current flows through the pn junction diode D. This causes a current to flow in the diode region 9.

In this embodiment, the boundary between the collector region 34 and the cathode region 61 in the first direction X is aligned with the boundary region 72 between the IGBT region 8 and the diode region 9 in a plan view.

Inside the cell separation trench 64, a recess 67 is defined by the sidewall of the cell separation trench 64, the upper end of the cell separation electrode layer 66, and the upper end of the cell separation insulating layer 65. The wide portion of the cell separation trench 64 is formed by the recess 67. The sidewall of the recess 67 (the sidewall of the cell separation trench 64) exposes the anode region 62.

As described above, the sidewall of the terminal emitter trench structure 73A closer to the diode region 9 forms the boundary region 72 between the IGBT region 8 and the diode region 9. In the region between the terminal emitter trench structure 73A and the cell isolation structure 63 closest to the IGBT region 8, a body region 45 and a carrier storage region 47 are formed in this order from the first main surface 3 side, similar to the FET structure 35. However, this region does not have an emitter region 46 formed therein, and is not a structure that forms a channel, so it may be referred to as a dummy FET structure 42. The dummy FET structure 42 is formed in the diode region 9.

With reference to Figures 9 to 11, the semiconductor device 1 includes an interlayer insulating layer 79 formed on the first main surface 3 of the semiconductor layer 2. The interlayer insulating layer 79 is formed in a film shape along the first main surface 3, and selectively covers the first main surface 3. Specifically, the interlayer insulating layer 79 selectively covers the IGBT region 8 and the diode region 9.

The interlayer insulating layer 79 may contain silicon oxide or silicon nitride. The interlayer insulating layer 79 may contain at least one of NSG (Non-doped Silicate Glass), PSG (Phosphor Silicate Glass), and BPSG (Boron Phosphor Silicate Glass). The thickness of the interlayer insulating layer 79 may be 0.1 μm or more and 1 μm or less.

In this embodiment, the interlayer insulating layer 79 has a laminated structure including a first insulating layer 80, a second insulating layer 81, and a third insulating layer 82, which are laminated in this order from the first main surface 3 side. The first insulating layer 80 may include silicon oxide (e.g., a thermal oxide film). The second insulating layer 81 may include an NGS layer, a PSG layer, or a BPSG layer. The third insulating layer 82 may include a BPSG layer, an NGS layer, or a PSG layer. The third insulating layer 82 may include an insulating material having properties different from those of the second insulating layer 81.

The first insulating layer 80 is formed in the form of a film on the first main surface 3. The first insulating layer 80 is continuous with the gate insulating layer 40, the region isolation insulating layer 55, and the cell isolation insulating layer 65. The thickness of the first insulating layer 80 may be 500 Å or more and 2000 Å or less. The second insulating layer 81 is formed in the form of a film on the first insulating layer 80. The thickness of the second insulating layer 81 may be 500 Å or more and 4000 Å or less. The third insulating layer 82 is formed in the form of a film on the second insulating layer 81. The thickness of the third insulating layer 82 may be 1000 Å or more and 8000 Å or less.

Referring to FIG. 11, the gate conductive layer 41 of the FET structure 35 has a gate extraction electrode layer 41a that is extended from the gate trench 39 onto the first main surface 3. The gate extraction electrode layer 41a is extended from the gate trench 39 of the first outer trench gate structure 37 onto the first main surface 3. The gate extraction electrode layer 41a is extended along the second direction Y.

The gate extraction electrode layer 41a is specifically formed inside the interlayer insulating layer 79. The gate extraction electrode layer 41a is extended onto the first insulating layer 80 and is interposed in the region between the first insulating layer 80 and the second insulating layer 81. The gate extraction electrode layer 41a is electrically connected to the gate wiring 19 (see FIG. 1) in a region not shown. A gate signal applied to the gate terminal electrode 14 is transmitted to the gate conductive layer 41 via the gate wiring 19 and the gate extraction electrode layer 41a.

The emitter potential electrode layer 76 of the emitter trench structure 73 has an extraction electrode layer 76a that is pulled out from the emitter trench 74 onto the first main surface 3. The emitter potential electrode layer 76 is pulled out along the second direction Y.

The extraction electrode layer 76a is specifically formed inside the interlayer insulating layer 79. The extraction electrode layer 76a is extended onto the first insulating layer 80 and is interposed in the region between the first insulating layer 80 and the second insulating layer 81. The extraction electrode layer 76a is electrically connected to the emitter terminal electrode 13. An emitter signal applied to the extraction electrode layer 76a is transmitted to the emitter potential electrode layer 76 via the extraction electrode layer 76a.

Referring to FIG. 10, the interlayer insulating layer 79 includes an emitter opening 83. The emitter opening 83 exposes the contact trench 48. The emitter opening 83 is in communication with the contact trench 48. In this embodiment, the contact trench 48 is formed in the first main surface 3, penetrating the first insulating layer 80 and the second insulating layer 81.

The emitter opening 83 penetrates the third insulating layer 82, exposing the contact trench 48. The emitter opening 83 forms an opening between itself and the contact trench 48. The edge of the emitter opening 83 is curved toward the inside of the interlayer insulating layer 79. As a result, the emitter opening 83 has an opening width larger than the opening width of the contact trench 48.

The interlayer insulating layer 79 includes a diode opening 84. The diode opening 84 exposes the diode region 9. Specifically, the diode opening 84 penetrates the interlayer insulating layer 79 and exposes a plurality of anode regions 62 (diode cell regions 69) and a plurality of cell isolation structures 63.

The portion of the inner wall of the diode opening 84 that is aligned with the second direction Y may be located above the anode region 62. The portion of the inner wall of the diode opening 84 that is aligned with the second direction Y may be located above the cell separation structure 63. In the example of FIG. 10, the portion of the inner wall of the diode opening 84 that is aligned with the second direction Y is located above the body region 45 of the dummy FET structure 42.

Referring to FIG. 11, the interlayer insulating layer 79 includes a first opening 86. The first opening 86 exposes the lead electrode layer 76a in the IGBT region 8. The first opening 86 is formed such that the opening width narrows from the opening side toward the bottom wall side.

Referring to Figures 9 and 10, the semiconductor device 1 includes an emitter plug electrode 91 embedded in a portion of the interlayer insulating layer 79 that covers the IGBT region 8. The emitter plug electrode 91 penetrates the interlayer insulating layer 79 and is electrically connected to the emitter region 46 and the contact region 49. Specifically, the emitter plug electrode 91 is embedded in the contact trench 48. The emitter plug electrode 91 is electrically connected to the emitter region 46 and the contact region 49 within the contact trench 48.

In this embodiment, the emitter plug electrode 91 has a layered structure including a barrier electrode layer 92 and a main electrode layer 93. The barrier electrode layer 92 is formed in the form of a film along the inner wall of the contact trench 48 so as to contact the interlayer insulating layer 79. The barrier electrode layer 92 defines a recess space within the contact trench 48.

The barrier electrode layer 92 may have a single-layer structure including a titanium layer or a titanium nitride layer. The barrier electrode layer 92 may have a laminated structure including a titanium layer and a titanium nitride layer. In this case, the titanium nitride layer may be laminated on the titanium layer.

The main electrode layer 93 is embedded in the contact trench 48 with the barrier electrode layer 92 sandwiched therebetween. Specifically, the main electrode layer 93 is embedded in a recess space defined by the barrier electrode layer 92 in the contact trench 48. The main electrode layer 93 may contain tungsten.

Referring to FIG. 11, the semiconductor device 1 includes a first plug electrode 94 embedded in the first opening 86. The first plug electrode 94 is electrically connected to the extraction electrode layer 76a within the first opening 86. The first plug electrode 94 has a structure corresponding to the emitter plug electrode 91. The description of the emitter plug electrode 91 applies mutatis mutandis to the description of the first plug electrode 94. The structures in the first plug electrode 94 that face the structures described for the emitter plug electrode 91 are given the same reference numerals and will not be described.

Referring to Figures 9 to 11, the emitter terminal electrode 13 is formed on an interlayer insulating layer 79. The emitter terminal electrode 13 may contain at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy. The emitter terminal electrode 13 may have a single-layer structure containing any one of these conductive materials. The emitter terminal electrode 13 may have a layered structure in which at least two of these conductive materials are layered in any order. The thickness of the emitter terminal electrode 13 may be 1.0 μm or more and 6.0 μm or less.

In this embodiment, the emitter terminal electrode 13 has a laminated structure including a first electrode layer 22, a second electrode layer 23, and a third electrode layer 24, which are laminated in this order from the first main surface 3 side. The first electrode layer 22 may include an aluminum-silicon-copper alloy (Al-Si-Cu). The second electrode layer 23 may include titanium nitride (TiN). The second electrode layer 23 may be referred to as a barrier layer. The third electrode layer 24 may include an aluminum-copper alloy (Al-Cu).

The emitter terminal electrode 13 is electrically connected to the emitter region 46 and the contact region 49 via an emitter plug electrode 91 on the interlayer insulating layer 79. Specifically, the emitter terminal electrode 13 extends into the emitter opening 83 from above the interlayer insulating layer 79. The emitter terminal electrode 13 is electrically connected to the emitter plug electrode 91 in the emitter opening 83. The emitter terminal electrode 13 is electrically connected to the emitter region 46 and the contact region 49 via the emitter plug electrode 91.

Referring to FIG. 10, the emitter terminal electrode 13 further extends into the diode opening 84 through the inner wall of the diode opening 84 from above the interlayer insulating layer 79. The emitter terminal electrode 13 functions as an anode terminal electrode in the diode region 9.

The emitter terminal electrode 13 is in contact with the inner wall of the diode opening 84. The emitter terminal electrode 13 is electrically connected to the anode region 62 at the diode opening 84. The emitter terminal electrode 13 is electrically connected to the cell separation electrode layer 66 at the diode opening 84. In this embodiment, the emitter terminal electrode 13 is directly connected to the anode region 62 and the cell separation electrode layer 66.

Specifically, the emitter terminal electrode 13 extends from above the first main surface 3 into the recess 67 (cell separation trench 64) within the diode opening 84. The emitter terminal electrode 13 is connected to the cell separation electrode layer 66 within the recess 67. The emitter terminal electrode 13 is also connected to the anode region 62 above the first main surface 3 and within the recess 67. The emitter terminal electrode 13 forms an ohmic contact with the anode region 62.

Referring to FIG. 11, the emitter terminal electrode 13 is electrically connected to a first plug electrode 94 on the interlayer insulating layer 79. The emitter signal is transmitted to the emitter potential electrode layer 76 via the first plug electrode 94.

Although specific illustrations are omitted, when a conductor (e.g., a bonding wire) is connected to the emitter terminal electrode 13, a single-layer electrode made of a nickel layer or a gold layer, or a laminated electrode including a nickel layer and a gold layer, may be formed on the emitter terminal electrode 13. In the laminated electrode, the gold layer may be formed on the nickel layer.

Although specific illustrations are omitted, the gate terminal electrode 14, the first sense terminal electrode 15, the second sense terminal electrode 16, the current detection terminal electrode 17 and the release terminal electrode 18 are formed on the interlayer insulating layer 79, similar to the emitter terminal electrode 13.

The multiple terminal electrodes 14-18 may each contain at least one of aluminum, copper, aluminum-silicon-copper alloy, aluminum-silicon alloy, and aluminum-copper alloy. The multiple terminal electrodes 14-18 may each have a single-layer structure containing any one of these conductive materials. The multiple terminal electrodes 14-18 may each have a layered structure in which at least two of these conductive materials are layered in any order. In this embodiment, the multiple terminal electrodes 14-18 contain the same conductive material as the emitter terminal electrode 13.

When a conducting wire (e.g., a bonding wire) is connected to each of the multiple terminal electrodes 14-18, a single-layer electrode made of a nickel layer or a gold layer, or a laminated electrode including a nickel layer and a gold layer, may be formed on each of the multiple terminal electrodes 14-18. In the laminated electrode, the gold layer may be formed on the nickel layer.

FIG. 12 is a schematic plan view of a semiconductor package 101 including a semiconductor device 1. FIG. 13 is a cross-sectional view showing the mounting structure of the semiconductor package 101 in FIG. 12.

The semiconductor package 101 includes the semiconductor device 1, electrodes 102-107, wires 133-136, and a resin package 108. In FIG. 12, the resin package 108 is indicated by a two-dot chain line. As shown in FIG. 13, the semiconductor package 101 is mounted on a mounting board 109. Depending on the type of semiconductor device 1, the semiconductor package 101 is used as an electronic component that performs switching functions, rectification functions, amplification functions, etc. in an electric circuit.

The electrode 102 includes a die bonding pad (heat dissipation unit) 110 and a lead 111. The die bonding pad 110 and the lead 111 are made of a conductive material such as copper.

The die bonding pad 110 is flat. The die bonding pad 110 has an arrangement surface 110A and a back surface 110B. The arrangement surface 110A faces one side of the normal direction Z. One side of the normal direction Z coincides with the upper side of the paper in FIG. 13. The back surface 110B faces the other side of the normal direction Z. The other side of the normal direction Z coincides with the lower side of the paper in FIG. 13. The semiconductor device 1 is arranged on the arrangement surface 110A. The die bonding pad 110 has a hole 112 formed therein, penetrating from the arrangement surface 110A to the back surface 110B.

The lead 111 extends linearly from the die bonding pad 110. The lead 111 is for insertion mounting. As shown in FIG. 13, the lead 111 is inserted into the hole 113. This causes the semiconductor package 101 to be mounted on the mounting board 109. To fix the lead 111 to the mounting board 109, the hole 113 is filled with solder 114. As shown in FIG. 12, the lead 111 has a connecting portion 111A and a terminal portion 112B. It functions as a collector terminal that is connected to the collector terminal electrode 32 (see the dashed line portion in FIG. 3) of the semiconductor device 1.

The connecting portion 111A is connected to the die bonding pad 110. The connecting portion 111A extends from the die bonding pad 110 in a direction intersecting with the placement surface 110A. The terminal portion 112B is connected to the connecting portion 111A. The terminal portion 112B has a portion that protrudes from the resin package 108.

Electrode 103 includes wire bonding pad 115 and lead 116. Electrode 104 includes wire bonding pad 117 and lead 118. Electrode 105 includes wire bonding pad 119 and lead 120. Electrode 106 includes wire bonding pad 121 and lead 122. Electrode 107 includes wire bonding pad 123 and lead 124. Wire bonding pads 115, 117, 119, 121, 123 and leads 116, 118, 120, 122, 124 are made of a conductive material such as copper.

As shown in FIG. 13, the leads 116, 118, 120, 122, and 124 are inserted into the holes 113. This causes the semiconductor package 101 to be mounted on the mounting board 109. The holes 113 are filled with solder 114 to secure the leads 116, 118, 120, 122, and 124 to the mounting board 109.

Referring mainly to FIG. 13, the resin package 108 covers the semiconductor device 1 and the electrodes 102 to 107. The resin package 108 is made of epoxy resin. The resin package 108 has a first surface 108A and a second surface 108B. The first surface 108A has a flat surface 108C and a tapered surface 108D. The first surface 108A of the resin package 108 contacts the second main surface 4 of the semiconductor device 1. The second surface 108B has a plurality of flat surfaces 108E and a plurality of tapered surfaces 108F. The resin package 108 has a screw hole 108H formed therein. A screw 130 is inserted into the screw hole 108H to fix the resin package 108 to the heat sink 129.

The wires 133 to 136 are made of a metal such as aluminum. The wire 133 is bonded to the emitter terminal electrode 13 and the wire bonding pad 115 of the semiconductor device 1. This electrically connects the emitter terminal electrode 13 and the wire bonding pad 115. The wire 134 is bonded to the current detection terminal electrode 17 and the wire bonding pad 119 of the semiconductor device 1. This electrically connects the current detection terminal electrode 17 and the wire bonding pad 119. The wire 135 is bonded to the first sense terminal electrode 15 or the second sense terminal electrode 16 (the first sense terminal electrode 15 in the example of FIG. 12) of the semiconductor device 1 and the wire bonding pad 121. This electrically connects the first sense terminal electrode 15 or the second sense terminal electrode 16 (the first sense terminal electrode 15 in the example of FIG. 12) and the wire bonding pad 121. The wire 136 is bonded to the gate terminal electrode 14 and the wire bonding pad 123 of the semiconductor device 1. This electrically connects the gate terminal electrode 14 and the wire bonding pad 123. Note that the wire bonding pad 117 is not electrically connected to the semiconductor device 1.

Heat generated in the semiconductor device 1 is dissipated via the die bonding pad 110 and the heat sink 129. The placement surface 110A of the die bonding pad 110 is in contact with the entire second main surface 4 of the semiconductor device 1, thereby allowing the second main surface 4 of the semiconductor device 1 to be uniformly cooled. On the other hand, no member for dissipating heat (heat dissipation unit) is in contact with the first main surface 3 of the semiconductor device 1.

As described above, according to this embodiment, in the active region 6, the multiple IGBT regions 8 and the multiple diode regions 9 are each arranged in a staggered pattern in a planar view. Therefore, in the active region 6, the total width (first opposing width W1 + second opposing width W2) of the portions where the IGBT regions 8 that are continuous in the second direction Y face the second direction Y is narrow.

In the RC-IGBT semiconductor device described in Patent Document 1, multiple IGBT regions and multiple diode regions are arranged in a matrix. Consider a case in which multiple IGBT regions 8 and multiple diode regions 9 are arranged in rows along the second direction Y in the semiconductor device 1, as in Patent Document 1.

When multiple IGBT regions 8 and multiple diode regions 9 are arranged in a row along the second direction Y, the IGBT regions 8 that are continuous in the second direction Y face each other widely, and the diode regions 9 that are continuous in the second direction Y face each other widely. When the IGBT is on, a current flows simultaneously through the multiple IGBT regions 8. When a current flows through the IGBT regions 8, the IGBT regions 8 generate heat. When the diode is on, a current flows simultaneously through the multiple diode regions 9. When a current flows through the diode regions 9, the diode regions 9 generate heat.

If multiple IGBT regions 8 are arranged in a row along the second direction Y, there is a risk that the amount of heat generated will be locally large in the area where the IGBT regions 8 are arranged. Also, if multiple diode regions 9 are arranged in a row along the second direction Y, there is a risk that the amount of heat generated will be locally large in the area where the diode regions 9 are arranged. Therefore, when the IGBT or diode is on, the active region 6 may become locally hot.

In particular, the center of the active region 6 is surrounded by the IGBT region 8 and the diode region 9, both of which are heat generating regions. As a result, the center of the active region 6 is an area that is difficult to dissipate heat. Therefore, when the IGBT or the diode is on, the center of the active region 6 may become particularly hot. On the other hand, in order to prevent the active region 6 from becoming too hot, it is possible to reduce the amount of current flowing through the IGBT region 8 and the diode region 9. However, in order to maintain high current characteristics of the RC-IGBT, it is necessary to ensure a large amount of current flowing through the IGBT region 8 and the diode region 9.

In the semiconductor device 1 according to the first embodiment, a staggered pattern (unit array UA of the staggered pattern) of IGBT regions 8 and diode regions 9 is formed over the entire active region 6. Therefore, the total width (first opposing width W1 + second opposing width W2) of the portions of the IGBT regions 8 that are continuous in the second direction Y and face the second direction Y is narrow. In addition, the multiple diode regions 9 do not face the second direction Y.

As a result, when the IGBT and the diode are on, local increases in the amount of heat generated in the active region 6 can be suppressed. This makes it possible to suppress temperature increases in the active region 6 without keeping the amount of current flowing through the IGBT region 8 and the diode region 9 low. In particular, it is possible to suppress temperature increases in the center of the active region 6. Therefore, it is possible to reduce the maximum temperature of the semiconductor device 1 while maintaining high current characteristics of the RC-IGBT.

FIG. 14 is a bottom view for explaining a semiconductor device 151 according to a modified example in which the configuration of the collector region 34 and the cathode region 61 is changed. FIG. 14 is a view corresponding to FIG. 3. FIG. 15 is a cross-sectional view of the semiconductor device 151 according to the modified example of FIG. 14.

The semiconductor device 151 according to the modified example of FIG. 14 and FIG. 15 differs from the semiconductor device 1 according to the first embodiment in that the cathode region 61 includes a lead-out region 182. The lead-out region 182 is a region that crosses the boundary region 72 (see FIG. 15) between the IGBT region 8 and the diode region 9 and is led out to the IGBT region 8. The lead-out region 182 is led out from the diode region 9 to the IGBT region 8 along the first direction X.

As shown in FIG. 14, in the semiconductor device 151, in the first array 12A, the third array 12C, and the fifth array 12E, the lead-out regions 182 are formed at both ends of the cathode region 61 in the first direction X. Therefore, in the first array 12A, the third array 12C, and the fifth array 12E, the area of the collector region 34 is narrower and the cathode region 61 is wider than in the semiconductor device 1 (see FIG. 3). FIG. 15 shows a cross section of the IGBT region 8 and the diode region 9 included in the first array 12A, the third array 12C, and the fifth array 12E, and corresponds to FIG. 10.

On the other hand, the second array 12B, the fourth array 12D, and the sixth array 12F do not have a lead-out region 182, as in the semiconductor device 1 (see FIG. 3). In the example of FIG. 14, in the first to sixth RC-IGBT arrays 12A to 12F, the boundaries of the collector regions 34 and the cathode regions 61 are all aligned in the first direction X.

The pull-out region 182 overlaps the IGBT region 8 with a predetermined overlap width W. The start point of the overlap width W is set at the boundary region 72 between the IGBT region 8 and the diode region 9. The end point of the overlap width W is set at the boundary between the collector region 34 and the pull-out region 182.

The ratio W/WG of the overlap width W to the width WG of the IGBT region 8 (see FIG. 5B, etc.) may be 0.001 or more and 0.5 or less. The ratio W/WG may be 0.001 or more and 0.01 or less, 0.01 or more and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.35 or more and 0.4 or less, 0.4 or more and 0.45 or less, or 0.45 or more and 0.5 or less.

The overlap width W may be 1 μm or more and 200 μm or less. The overlap width W may be 1 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, or 150 μm or more and 200 μm or less.

The overlap width W may be 1 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or less, or 180 μm or more and 200 μm or less. The overlap width W is preferably 10 μm or more and 150 μm or less.

The pull-out region 182 may face one or more FET structures 35 in the normal direction Z. The pull-out region 182 may face 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20 FET structures 35.

FIG. 16 is a schematic plan view of a semiconductor device 201 according to a second embodiment of the present disclosure. FIG. 17 is a schematic plan view showing the structure of a first main surface 3 of the semiconductor device 201. In the second embodiment, only the parts that differ from the first embodiment will be mainly described, and the same reference symbols will be used for the same configurations as those described so far, and their description will be omitted.

The semiconductor device 201 according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in that the area ratio of the diode region 9 to the active region 6 is approximately 50%. In other words, in a plan view, the area ratio of the IGBT 8 to the active region 6 is approximately 50%. In the active region 6, the planar area of the IGBT 8 and the planar area of the diode region 9 are approximately the same. The width WG of each IGBT region 8 (see FIG. 17) is approximately the same as the width WD of each diode region 9 (see FIG. 17).

In the semiconductor device 201, a plurality of IGBT regions 8 and a plurality of diode regions 9 are arranged in a staggered pattern in a plan view throughout the active region 6. That is, a staggered pattern (unit array UA of the staggered pattern) of the IGBT regions 8 and diode regions 9 is formed throughout the active region 6.

In the semiconductor device 201, each IGBT region 8 faces one diode region 9 included in the RC-IGBT array adjacent to it in the second direction Y, across the second region 19b of the gate wiring 19. Each IGBT region 8 does not face an IGBT region 8 included in the RC-IGBT array adjacent to it in the second direction Y in the second direction Y.

Furthermore, each diode region 9 faces one IGBT region 8 included in the RC-IGBT array 12 adjacent thereto in the second direction Y, across the second region 19b of the gate wiring 19. Each diode region 9 does not face the diode region 9 included in the RC-IGBT array 12 adjacent thereto in the second direction Y.

According to the second embodiment, in the active region 6, the multiple IGBT regions 8 and the multiple diode regions 9 are each arranged in a staggered pattern in a plan view. Not only the multiple diode regions 9, but also the multiple IGBT regions 8 do not face the second direction Y. Therefore, compared to the first embodiment, local increases in the amount of heat generated in the active region 6 when the IGBTs and diodes are on can be further suppressed. This makes it possible to further suppress temperature increases in the active region 6.

FIG. 18 is a schematic plan view of a semiconductor device 301 according to a third embodiment of the present disclosure. FIG. 19 is a schematic plan view showing the structure of the first main surface 3 of the semiconductor device 301.

The semiconductor device 301 according to the third embodiment differs from the semiconductor device 1 according to the first embodiment in that the staggered pattern (unit array UA of the staggered pattern) of the IGBT regions 8 and the diode regions 9 is formed only in the central portion 6a of the active region 6, rather than over the entire active region 6. In the peripheral portion 6b of the active region 6, instead of the above-mentioned array pattern, an array pattern in which a plurality of IGBT regions 8 are arranged in rows along the second direction Y, and an array pattern in which a plurality of diode regions 9 are arranged in rows along the second direction Y, are adopted. In the example of Figures 18 and 19, in the region of the active region 6 closest to the side surface 5B, a plurality of IGBT regions 8 are arranged in rows along the second direction Y, and in the region on the side surface 5D side of that region, a plurality of diode regions 9 are each arranged in rows along the second direction Y. In addition, in the active region 6, in the region closest to the side surface 5D, multiple IGBT regions 8 are lined up in a row along the second direction Y, and in the region on the side surface 5B side of that region, multiple diode regions 9 are lined up in a row along the second direction Y.

The central portion 6a of the active region 6 is surrounded by the IGBT region 8 and the diode region 9, both of which are heat generating regions. Therefore, the central portion 6a of the active region 6 is an area that is difficult to dissipate heat.

The staggered pattern of the IGBT region 8 and the diode region 9 is formed in the central portion 6a of the active region 6, which is the portion that is least likely to dissipate heat, so that the temperature rise in the central portion 6a of the active region 6 can be suppressed. This makes it possible to reduce the maximum temperature of the semiconductor device 301.

The package structure of the semiconductor package 101 in FIG. 12 and the mounting structure in FIG. 13 are also applied to the semiconductor device 301.

FIG. 20 is a schematic plan view of a semiconductor device 401 according to a fourth embodiment of the present disclosure. FIG. 21 is a schematic plan view showing the structure of a first main surface 3 of the semiconductor device 401.

The semiconductor device 401 according to the fourth embodiment differs from the semiconductor device 1 according to the first embodiment in that the staggered pattern (unit array UA of the staggered pattern) of the IGBT regions 8 and diode regions 9 is formed only on the outer periphery 6b of the active region 6, rather than over the entire active region 6. In the central portion of the active region 6, instead of the above-mentioned arrangement pattern, an arrangement pattern in which a plurality of IGBT regions 8 are arranged in a row along the second direction Y, and an arrangement pattern in which a plurality of diode regions 9 are arranged in a row along the second direction Y are adopted.

FIG. 22 is a schematic cross-sectional view of a semiconductor package 450 including a semiconductor device 401.

The semiconductor package 450 includes a semiconductor device 401, a first heat dissipation pad (heat dissipation unit) 451, a second heat dissipation pad 452, a spacer (heat dissipation unit) 453 for regulating the distance between the top surface of the semiconductor device 401 and the second heat dissipation pad 452, a resin package 454, a first lead 456, a second lead 457, a third lead 458, a fourth lead 459, a fifth lead 460, a sixth lead 461, and wires 471 to 475.

The first heat dissipation pad 451 is flat. The first heat dissipation pad 451 is made of a conductive material such as copper. The first heat dissipation pad 451 has a flat placement surface 451A. The placement surface 451A faces one side of the normal direction Z. The one side of the normal direction Z coincides with the upper side of the paper surface of FIG. 22.

The first lead 456, the second lead 457, the third lead 458, the fourth lead 459, the fifth lead 460 and the sixth lead 461 are shaped to extend linearly from the first heat dissipation pad 451. The first lead 456, the second lead 457, the third lead 458, the fourth lead 459, the fifth lead 460 and the sixth lead 461 are arranged in a line in the first direction X. The first direction X is a direction perpendicular to the paper surface of FIG. 22. The first lead 456, the second lead 457, the third lead 458, the fourth lead 459, the fifth lead 460 and the sixth lead 461 are made of a conductive material such as copper.

The wires 471 to 475 are made of a metal such as aluminum. The wire 471 is joined to the collector terminal electrode 32 (see the dashed line in FIG. 20) of the semiconductor device 401 and the first lead 456. This electrically connects the collector terminal electrode 32 and the first lead 456. The wire 472 is joined to the emitter terminal electrode 13 (see FIG. 20) of the semiconductor device 401 and the second lead 457. This electrically connects the emitter terminal electrode 13 and the second lead 457.

The wire 473 is joined to the current detection terminal electrode 17 (see FIG. 20) and the fourth lead 459 of the semiconductor device 401. This electrically connects the current detection terminal electrode 17 and the fourth lead 459. The wire 474 is joined to the first sense terminal electrode 15 or the second sense terminal electrode 16 (for example, the first sense terminal electrode 15 in this embodiment) of the semiconductor device 401 and the fifth lead 460. This electrically connects the first sense terminal electrode 15 or the second sense terminal electrode 16 (for example, the first sense terminal electrode 15) and the fifth lead 460. The wire 475 is joined to the gate terminal electrode 14 (see FIG. 20) and the sixth lead 461 of the semiconductor device 401. This electrically connects the gate terminal electrode 14 and the sixth lead 461. The third lead 458 is not electrically connected to the semiconductor device 401.

The second heat dissipation pad 452 is flat. The second heat dissipation pad 452 is made of a conductive material such as copper. The second heat dissipation pad 452 is disposed on one side of the first heat dissipation pad 451 in the normal direction Z, sandwiching the semiconductor device 401 therebetween.

The spacer 453 is a columnar body extending in the normal direction Z. The spacer 453 is disposed between the first heat dissipation pad 451 and the second heat dissipation pad 452. The spacer 453 is made of a conductive material such as copper. An end face 453A of the spacer 453 contacts the center of the semiconductor device 401, more specifically, the center of the first main surface 3 (the center 6a of the active region 6 (see FIG. 20, etc.)). As a result, only the center 6a is cooled on the first main surface 3 of the semiconductor device 401.

Heat generated in the semiconductor device 401 is dissipated via the first heat dissipation pad 451, the spacer 453, and the second heat dissipation pad 452. The placement surface 451A of the first heat dissipation pad 451 contacts the entire second main surface 4 of the semiconductor device 401, thereby uniformly cooling the second main surface 4 of the semiconductor device 401. Meanwhile, the end surface 453A of the spacer 453 contacts the first main surface 3 of the semiconductor device 401 only at the center.

As described above, referring to Figures 20 and 21, in the semiconductor device 401, the central portion 6a of the active region 6 is an area that dissipates heat easily. On the other hand, the peripheral portion 6b of the active region 6 is an area that dissipates heat less easily than the central portion 6a. Since the staggered pattern of the IGBT region 8 and the diode region 9 is formed in the peripheral portion 6b of the active region 6, which is less likely to dissipate heat, it is possible to suppress a rise in temperature in the peripheral portion 6b of the active region 6. This makes it possible to reduce the maximum temperature of the semiconductor device 401.

In addition, a package structure similar to the semiconductor package 450 may be applied to the semiconductor device 1, the semiconductor device 151, or the semiconductor device 201.

The embodiments of the present disclosure may also be implemented in other forms.

In each of the above-described embodiments, the semiconductor layer 2 may have a layered structure including a p-type semiconductor substrate and an n ^- type epitaxial layer formed on the semiconductor substrate, instead of the n ^- type semiconductor substrate 31. In this case, the p-type semiconductor substrate faces the collector region 34. Furthermore, the n ^- type epitaxial layer faces the drift region 30.

The p-type semiconductor substrate may be made of silicon. The n ^- type epitaxial layer may be made of silicon. The ^n- type epitaxial layer is formed by epitaxially growing silicon from the main surface of the p-type semiconductor substrate.

In each of the above-mentioned embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted. In other words, the p-type portion may be formed as n-type, and the n-type portion may be formed as p-type.

The following features can be extracted from the description in this specification and the drawings.

[Appendix 1-1]
A semiconductor layer (2) having a first major surface (3) and a second major surface (4) opposite thereto;
An IGBT region (8) formed in the semiconductor layer (2), the IGBT region (8) having a gate trench (39) formed therein;
a diode region (9) formed in the semiconductor layer (2);
a plurality of gate wirings (19b) formed on the first main surface (3);
In a predetermined region of an active region (6) including the IGBT region (8) and the diode region (9), one of the IGBT region (8) and the diode region (9) is a reference region (8B), and the other is a heterogeneous region (9A, 9B, 9C) different from the reference region (8B);
the reference region (8B) faces the heterogeneous region (9B) in a first direction (X) perpendicular to an extension direction of the gate trench (39) in a plan view;
A semiconductor device (1, 151, 201, 301, 401), wherein, in a predetermined region of the active region (6), the reference region (8B) is further opposed to the heterogeneous region (9A) in a second direction (Y) parallel to the extension direction of the gate trench (39) in a planar view, across a first gate wiring (19bA) included in the plurality of gate wirings (19b).

According to this configuration, in a predetermined region of the active region (6), one of the reference regions (8B) of the IGBT region (8) and the diode region (9) faces the other heterogeneous region (9A) of the IGBT region (8) and the diode region (9) across the first gate wiring (19bA) in the second direction (Y) parallel to the extension direction of the gate trench (39) in a plan view. Therefore, in a predetermined region of the active region (6), the reference region (8B) does not face the homogeneous region (8A) of the same type as the reference region (8B) across the first gate wiring (19bA) in the second direction (Y), or even if it faces the homogeneous region (8A) in the second direction (Y), the facing width with the homogeneous region (8C) is narrow. This makes it possible to suppress a local increase in the amount of heat generated in a predetermined region of the active region (6) when a current flows through the reference region (8B) and the homogeneous region (8A). Therefore, it is possible to suppress temperature rise in a specific area of the active area (6).

[Appendix 1-2]
the plurality of gate wirings (19b) include the first gate wiring (19bA) and a second gate wiring (19bB) extending along the first gate wiring (19bA);
the reference region (8B) is sandwiched in the second direction (Y) by the first gate wiring (19bA) and the second gate wiring (19bB);
The semiconductor device (1, 151, 201, 301, 401) according to Appendix 1-1, wherein the reference region (8B) is further opposed to the heterogeneous region (9C) in the second direction (Y) across the second gate wiring (19bB).

[Appendix 1-3]
The semiconductor device (1, 151, 301, 401) described in Appendix 1-1 or Appendix 1-2, wherein the reference region (8B) is formed independently of the reference region (8B) and is further opposed to a homogeneous region (8A) of the same type as the reference region (8B) in the second direction (Y) across the first gate wiring (19bA).

[Appendix 1-4]
the reference region (8B) includes a reference IGBT region (8B) consisting of the IGBT region (8);
The semiconductor device (1, 151, 301, 401) described in Appendix 1-3, wherein the reference IGBT region (8B) faces a homogeneous IGBT region (8A) that is the homogeneous region (8A) in the second direction (Y) across the first gate wiring (19bA).

[Appendix 1-5]
The semiconductor device (1, 151, 301, 401) described in Appendix 1-4, wherein an opposing width (W1, W2) between the reference IGBT region (8A) and the homogeneous IGBT region (8A) in the second direction (Y) is equal to or greater than a line width (W3) of the first gate wiring (19b).

[Appendix 1-6]
The semiconductor device (201) according to claim 1-1 or 1-2, wherein the reference region (8B) is formed independently of the reference region (8B) and does not face a homogeneous region (8A) of the same type as the reference region (8B) in the second direction (Y).

[Appendix 1-7]
The semiconductor device (1, 151, 201, 301) according to any one of Supplementary Notes 1-1 to 1-6, wherein the predetermined region is a region including a central portion (6a) of the active region (6) in a planar view.

[Appendix 1-8]
The second main surface (4) is an area whose entire area is in contact with the heat dissipation unit (110),
The semiconductor device (1, 151, 201, 301) according to appendix 1-7, wherein a heat dissipation unit is not in contact with the first main surface (3).

[Appendix 1-9]
The semiconductor device (1, 151, 201, 401) according to any one of claims 1-1 to 1-6, wherein the predetermined region is a region including an outer periphery (6b) of the active region (6) in a plan view.

[Appendix 1-10]
The entire second main surface (4) and a central portion (6a) of the first main surface (3) are in contact with a heat dissipation unit (451, 453),
The semiconductor device (1, 151, 201, 401) according to appendix 1-9, wherein a heat dissipation unit is not in contact with the outer periphery (6a) of the first main surface (3).

[Appendix 1-11]
The semiconductor device (1, 151, 201) according to Supplementary Note 1-7 or Supplementary Note 1-9, wherein the predetermined area is the entire area of the active area (6).

[Appendix 1-12]
Further comprising a unit sequence (UA),
the unit array (UA) includes the reference region (8B), a plurality of the heterogeneous regions (9A, 9B, 9C) adjacent to the reference region (8B) in the first direction (X) and the second direction (Y), and the homogeneous regions (8A, 8C) adjacent to the reference region (8B) on both sides of two diagonal directions intersecting both the first direction (X) and the second direction (Y) and independent of the reference region (8B),
The semiconductor device (1, 151, 201, 301, 401) according to any one of Supplementary Notes 1-3 to 1-6, wherein the unit array (UA) is formed over the entire active region (6) in a planar view.

[Appendix 1-13]
the IGBT region and the diode region each include a plurality of the IGBT regions and a plurality of the diode regions,
a plurality of region arrays including a plurality of the IGBT regions and a plurality of the diode regions, the plurality of the IGBT regions and the plurality of the diode regions being alternately arranged along the first direction, the plurality of region arrays being arranged at intervals in the second direction on the first main surface;
a plurality of the IGBT regions included in a predetermined region array among the plurality of region arrays face, in the second direction, each of a plurality of the diode regions included in a region array adjacent in the second direction to the predetermined region array,
The semiconductor device according to claim 1-1, wherein the plurality of diode regions included in the predetermined region array are opposed in the second direction to each of the plurality of IGBT regions included in the region array adjacent to the predetermined region array in the second direction.

[Appendix 1-14]
The diode region (9) includes a cathode region (61) formed in a surface layer portion of the second main surface (4),
The semiconductor device (1, 151, 301, 401) according to any one of Supplementary Notes 1-1 to 1-13, wherein the cathode region (61) includes an extraction region (182) that crosses the boundary region (72) and is extracted to the IGBT region side.

[Appendix 1-15]
The semiconductor device (1, 151, 301, 401) according to any one of Supplementary Notes 1-1 to 1-14, wherein, in a plan view, the area ratio of the diode region (9) to the active region (6) is 25% or more and 45% or less.

[Appendix 1-16]
the IGBT region (8) and the diode region (9) each include a plurality of IGBT regions (8) and a plurality of diode regions (9);
The semiconductor device (1, 151, 201) according to any one of Appendix 1-1 to Appendix 1-15, wherein, in a plan view, the plurality of IGBT regions (8) and the plurality of diode regions (9) are each staggered.

1: Semiconductor device 2: Semiconductor layer 3: First principal surface 4: Second principal surface 5A: Side surface 5B: Side surface 5C: Side surface 5D: Side surface 6: Active region 6a: Central portion 6b: Peripheral portion 7: Outer region 8: IGBT area 8A: IGBT area (same type IGBT area, same type area)
8B: IGBT area (reference IGBT area, reference area)
8C: IGBT area (same type IGBT area, homogeneous area)
9: Diode region 9A: Diode region (heterogeneous diode region, heterogeneous region)
9B: Diode region (heterogeneous diode region, heterogeneous region)
9C: Diode region (heterogeneous diode region, heterogeneous region)
11: Sensor region 12: IGBT array (region array)
12A: First array 12B: Second array 12C: Third array 12D: Fourth array 12E: Fifth array 12F: Sixth array 13: Emitter terminal electrode 14: Gate terminal electrode 15: First sense terminal electrode 16: 2. Sense terminal electrode 17: Current detection terminal electrode 18: Open terminal electrode 19: Gate wiring 19a: First region 19b: Second region 19bA: First gate wiring 19bB: Second gate wiring 20: First sense wiring 20a: First region 20b: second region 21: second sense wiring 21a: first region 21b: second region 22: first electrode layer 23: second electrode layer 24: third electrode layer 30: drift region 31: semiconductor substrate 32 : Collector terminal electrode 33 : Buffer layer 34 : collector region 35 : FET structure 36 : trench gate structure 37 : first outer trench gate structure 38 : second outer trench gate structure 39 : gate trench 40 : gate insulating layer 41 : gate conductive layer 41 a : gate extraction electrode layer 42 : Dummy FET structure 45: body region 46: emitter region 47: carrier storage region 48: contact trench 49: contact region 55: region isolation insulating layer 61: cathode region 62: anode region 63: cell isolation structure 64: cell isolation trench 65: Cell isolation insulating layer 66 : Cell isolation electrode layer 67 : Recess 68 : pn junction 69 : Diode cell region 72 : Boundary region 73 : Emitter trench structure 73A : Termination emitter trench structure 74 : Emitter trench 75 : Emitter insulating layer 76 : emitter potential electrode layer 76a : extraction electrode layer 79 : interlayer insulating layer 80 : first insulating layer 81 : second insulating layer 82 : third insulating layer 83 : emitter opening 84 : diode opening 86 : first opening 91 : emitter plug Electrode 92 : Barrier electrode layer 93 : Main electrode layer 94 : First plug electrode 101 : Semiconductor package 102 : Electrode 103 : Electrode 104 : Electrode 105 : Electrode 106 : Electrode 107 : Electrode 108 : Resin package 108A : First surface 108B : Second surface 108C: Flat surface 108D: Tapered surface 108E: Flat surface 108F: Tapered surface 108H: Screw hole 109: Mounting substrate 110: Die bonding pad (heat dissipation unit)
110A: placement surface 110B: back surface 111: lead 111A: connection portion 112: hole 112B: terminal portion 113: hole 114: solder 115: wire bonding pad 116: lead 117: wire bonding pad 118: lead 119: wire bonding pad 120: Lead 121: Wire bonding pad 122: Lead 123: Wire bonding pad 124: Lead 129: Heat sink 130: Screw 133: Wire 134: Wire 135: Wire 136: Wire 151: Semiconductor device 182: Lead-out region 201: Semiconductor device 301: Semiconductor device 401: Semiconductor device 450: Semiconductor package 451: First heat dissipation pad (heat dissipation unit)
451A: Placement surface 452: Second heat dissipation pad 453: Spacer (heat dissipation unit)
453A: End surface 454: Resin package 456: First lead 457: Second lead 458: Third lead 459: Fourth lead 460: Fifth lead 461: Sixth lead 471: Wire 472: Wire 473: Wire 474: Wire 475 : Wire D : pn junction diode D1 : Depth D2 : Depth D3 : Depth P1 : First pitch P2 : Second pitch UA : Unit array W : Overlap width W1 : First opposing width (opposing width)
W2: Second opposing width (opposing width)
W3: Line width W4: First interval W5: Second interval WD: Width WG: Width X: First direction Y: Second direction Y1: One side Y2: Other side Z: Normal direction

Claims (15)

1. a semiconductor layer having a first major surface and an opposite second major surface;
   an IGBT region formed in the semiconductor layer, the IGBT region having a gate trench;
   a diode region formed in the semiconductor layer;
   a plurality of gate wirings formed on the first main surface;
   In a predetermined region of an active region including the IGBT region and the diode region, one of the IGBT region and the diode region is a reference region, and the other is a heterogeneous region different from the reference region,
   the reference region faces the different region in a first direction perpendicular to an extension direction of the gate trench in a plan view;
   a first gate wiring included in the plurality of gate wirings is sandwiched between the first gate wiring and the second gate wiring, the first gate wiring being ... and the second gate wiring being sandwiched between the first gate wiring and the second gate wiring, in a second direction parallel to the extension direction of the gate trench in a planar view.
2. the plurality of gate wirings include the first gate wiring and a second gate wiring extending along the first gate wiring,
   the reference region is sandwiched in the second direction by the first gate wiring and the second gate wiring,
   2 . The semiconductor device according to claim 1 , wherein said reference region is further opposed to said different type region in said second direction with said second gate wiring therebetween.
3. The semiconductor device according to claim 1 or 2, wherein the reference region is formed independently of the reference region and is further opposed in the second direction to a homogeneous region of the same type as the reference region, with the first gate wiring interposed therebetween.
4. the reference region includes a reference IGBT region formed of the IGBT region,
   4. The semiconductor device according to claim 3, wherein said reference IGBT region faces said homogeneous IGBT region, which is said homogeneous region, in said second direction with said first gate wiring interposed therebetween.
5. The semiconductor device according to claim 4, wherein the width of the reference IGBT region and the homogeneous IGBT region facing each other in the second direction is equal to or greater than the line width of the first gate wiring.
6. The semiconductor device according to claim 1 or 2, wherein the reference region is formed independently of the reference region and does not face a homogeneous region of the same type as the reference region in the second direction.
7. The semiconductor device according to any one of claims 1 to 6, wherein the predetermined region is a region that includes a central portion of the active region in a plan view.
8. the second main surface is an area whose entire area is in contact with a heat dissipation unit,
   The semiconductor device according to claim 7 , wherein a heat dissipation unit is not in contact with the first main surface.
9. The semiconductor device according to any one of claims 1 to 6, wherein the predetermined region is a region that includes the outer periphery of the active region in a plan view.
10. the entire second main surface and a central portion of the first main surface are in contact with a heat dissipation unit,
    The semiconductor device according to claim 9 , wherein a heat dissipation unit is not in contact with an outer periphery of the first main surface.
11. Further comprising a unit sequence,
    the unit array includes the reference region, a plurality of the heterogeneous regions adjacent to the reference region in the first direction and the second direction, and the homogeneous regions adjacent to the reference region on both sides of two oblique directions intersecting the reference region in both the first direction and the second direction and independent of the reference region,
    7. The semiconductor device according to claim 3, wherein the unit array is formed over the entire active region in a plan view.
12. the IGBT region and the diode region each include a plurality of the IGBT regions and a plurality of the diode regions,
    a plurality of region arrays including a plurality of the IGBT regions and a plurality of the diode regions, the plurality of the IGBT regions and the plurality of the diode regions being alternately arranged along the first direction, the plurality of region arrays being arranged at intervals in the second direction on the first main surface;
    a plurality of the IGBT regions included in a predetermined region array among the plurality of region arrays face, in the second direction, each of a plurality of the diode regions included in a region array adjacent in the second direction to the predetermined region array,
    2. The semiconductor device according to claim 1, wherein a plurality of the diode regions included in the predetermined region array face in the second direction, respectively, a plurality of the IGBT regions included in the region array adjacent in the second direction to the predetermined region array.
13. the diode region includes a cathode region formed in a surface layer portion of the second main surface,
    13. The semiconductor device according to claim 1, wherein the cathode region includes a lead-out region that crosses a boundary region that is a boundary between the diode region and the IGBT region and is led out to the IGBT region side.
14. The semiconductor device according to any one of claims 1 to 13, wherein the area ratio of the diode region to the active region in a plan view is 25% or more and 45% or less.
15. the IGBT region and the diode region each include a plurality of IGBT regions and a plurality of diode regions;
    15. The semiconductor device according to claim 1, wherein the plurality of IGBT regions and the plurality of diode regions are each arranged in a staggered pattern in a plan view.

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