WO2024139513A1

WO2024139513A1 - Power amplifier and mobile terminal

Info

Publication number: WO2024139513A1
Application number: PCT/CN2023/123631
Authority: WO
Inventors: 彭振飞; 苏强
Original assignee: 广州慧智微电子股份有限公司
Priority date: 2022-12-29
Filing date: 2023-10-09
Publication date: 2024-07-04
Also published as: CN115955201A; CN115955201B

Abstract

A power amplifier (1) and a mobile terminal. The power amplifier (1) comprises: a bias circuit (10) and an amplifier circuit (11); the amplifier circuit (11) comprises a first transistor (M1) and a shunt circuit; the bias circuit (10) provides bias current to the amplifier circuit (11); the amplifier circuit (11) amplifies an inputted radio frequency signal and outputs an amplified radio frequency signal; a gate of the first transistor (M1) is connected to the bias circuit (10), a source of the first transistor (M1) is grounded, and a drain of the first transistor (M1) is connected to a DC power supply (VDD); an input end of the shunt circuit is connected to the gate of the first transistor (M1); the bias current outputted by the bias circuit (10) is conducted by means of an output end of the shunt circuit, so as to drive the first transistor (M1) using the bias current.

Description

A power amplifier and a mobile terminal

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on the Chinese patent application with application number 202211718282.X and application date December 29, 2022, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference.

Technical Field

The present application relates to the technical field of power amplifiers, and in particular to a power amplifier and a mobile terminal.

Background technique

Radio frequency power amplifiers (PA) are widely used in mobile communication devices of the second generation (2G)/third generation (3G)/fourth generation (4G)/fifth generation (5G). In order to increase the data transmission rate, 3G/4G/5G communications use high-order modulation methods, such as Quadrature Phase Shift Keying (QPSK) and Quadrature Amplitude Modulation (QAM). The output signal of high-order modulation is a non-constant envelope signal. Therefore, in order to reduce signal distortion, a linear PA is required.

PA usually uses compound semiconductor technology such as GaAs Hetero Junction Bipolar Transistor (GaAs HBT). Although GaAs HBT has the advantages of high efficiency and high linearity, it is relatively expensive. If the N-channel field effect transistor (N Field Effect Transistor, NFET) in the lower-cost complementary metal-oxide-semiconductor (CMOS) process is used, the linearity of NFET is low under large signals and it is difficult to design a high-power and high-linearity power amplifier, so the designed power amplifier shows low linearity at high power.

Summary of the invention

In view of this, embodiments of the present application hope to provide a power amplifier and a mobile terminal.

The technical solution of the embodiment of the present application is implemented as follows:

In a first aspect, an embodiment of the present application provides a power amplifier, the power amplifier comprising: a bias circuit and an amplifying circuit; the amplifying circuit comprising: a first transistor and a shunt circuit;

Providing bias current to the amplifier circuit through the bias circuit;

The input radio frequency signal is amplified through the amplifier circuit, and the amplified radio frequency signal is output;

The gate of the first transistor is connected to the bias circuit, the source of the first transistor is grounded, and the The drain of the body tube is connected to the power supply;

The input end of the shunt circuit is connected to the gate of the first transistor, and the first bias current output by the bias circuit is derived through the output end of the shunt circuit to drive the first transistor using the first bias current.

In the above power amplifier, the shunt circuit includes: a second transistor;

The gate of the second transistor and the drain of the second transistor are respectively connected to the gate of the first transistor; the bias current output by the bias circuit is derived through the source of the second transistor.

In the above power amplifier, the shunt circuit includes: a diode;

The anode of the diode is connected to the gate of the first transistor; the bias current output by the bias circuit is derived through the cathode of the diode.

In the above power amplifier, the shunt circuit includes: a first resistor;

One end of the first resistor is connected to the gate of the first transistor; the bias current output by the bias circuit is derived through the other end of the first resistor.

In the above power amplifier, the output terminal of the shunt circuit is grounded.

In the above power amplifier, the bias circuit includes a third transistor and a first capacitor;

The gate of the third transistor is connected to one end of the first capacitor, and the other end of the first capacitor is grounded; the source of the third transistor is connected to the gate of the first transistor; and the drain of the third transistor is connected to a power supply;

providing a bias current to the gate of the first transistor through the third transistor;

The radio frequency signal transmitted in the path where the drain of the third transistor and the gate of the third transistor are located is introduced into the ground through the first capacitor.

In the above power amplifier, the bias circuit further includes a fourth transistor and a fifth transistor;

The gate of the fourth transistor is connected to the gate of the third transistor; the drain of the fourth transistor is connected to the gate of the third transistor and the DC power supply respectively; the source of the fourth transistor is connected to the gate of the fifth transistor and the drain of the fifth transistor; the source of the fifth transistor is grounded.

In the above power amplifier, the bias circuit further includes a second resistor;

One end of the second resistor is connected to the gate of the first transistor; the other end of the second resistor is connected to the source of the third transistor;

When the current transmitted by the gate of the first transistor changes with the temperature of the first transistor, the current is adjusted by using the second resistor to adjust the bias voltage of the first transistor.

In the above power amplifier, the bias circuit further includes a third resistor;

One end of the third resistor is connected to the drain of the fourth transistor; the other end of the third resistor is connected to the gate of the third transistor;

The third resistor is used to isolate the leaked RF signal from the power supply.

In the above power amplifier, the power amplifier is a CMOS power amplifier.

In a second aspect, an embodiment of the present application provides a mobile terminal, the mobile terminal comprising a power amplifier as described in any one of the above items.

The embodiment of the present application provides a power amplifier and a mobile terminal, wherein the power amplifier comprises: a bias circuit and an amplifying circuit; the amplifying circuit comprises: a first transistor and a shunt circuit; the bias circuit provides a bias current for the amplifying circuit; the amplifying circuit amplifies an input radio frequency signal and outputs the amplified radio frequency signal; the gate of the first transistor is connected to the output end of the bias circuit, The source of the first transistor is grounded, and the drain of the first transistor is connected to the power supply; the input end of the shunt circuit is connected to the gate of the first transistor; the first bias current output by the bias circuit is derived through the output end of the shunt circuit to drive the first transistor using the first bias current. With the above implementation scheme, in the process of amplifying the power of the input RF signal, the bias current output in the bias circuit of the power amplifier increases with the increase of the RF signal power by improving the power amplifier, so that the bias voltage affecting the input end of the amplifier circuit will also increase with the increase of the bias current output in the bias circuit, and the linearity of the transistor that amplifies the RF signal in the amplifier circuit is improved by using the variable bias voltage. In the embodiment of the present application, the linearity of the transistor that amplifies the RF signal is adjusted by using the variable bias voltage, and the linearity of the low-cost CMOS power amplifier is improved, which not only improves the linearity of the CMOS power amplifier under large signal conditions, but also improves the linearity of the CMOS power amplifier. After the CMOS power amplifier is improved, the high-cost GaAs HBT is replaced by the improved CMOS power amplifier, and the mobile terminal using the improved CMOS power amplifier has a lower cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a CMOS power amplifier structure in the related art;

FIG2 is a schematic diagram of a power amplifier circuit structure provided in an embodiment of the present application;

FIG3 is a schematic diagram of an amplifying circuit structure provided in an embodiment of the present application;

FIG4 is a second schematic diagram of an amplifying circuit structure provided in an embodiment of the present application;

FIG5 is a second schematic diagram of a power amplifier circuit structure provided in an embodiment of the present application;

FIG6 is a third schematic diagram of a power amplifier circuit structure provided in an embodiment of the present application;

FIG7 is a fourth schematic diagram of a power amplifier circuit structure provided in an embodiment of the present application;

FIG8 is a schematic diagram of a power amplifier circuit structure 5 provided in an embodiment of the present application;

FIG9 is a sixth schematic diagram of a power amplifier circuit structure provided in an embodiment of the present application;

FIG10 is a schematic diagram of a power amplifier circuit structure according to an embodiment of the present application;

FIG11 is a schematic diagram of a power amplifier circuit structure eight provided in an embodiment of the present application;

FIG12 is a schematic diagram of a DC-IV characteristic curve of the improved current-controlled power amplifier circuit under a direct current (DC) state;

FIG. 13 is a schematic diagram showing a comparison curve between a power gain curve of a CMOS power amplifier in the related art, a power gain curve of an HBT power amplifier in the related art, and a power gain curve of the improved power amplifier in the present application.

Detailed ways

In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the technical solution of the present application is further elaborated in detail below in combination with the drawings and specific embodiments of the specification. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meanings as those commonly understood by those skilled in the art to which this application belongs. It is only for the purpose of describing the embodiments of the present application and is not intended to limit the present application.

In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. It should also be noted that the terms "first/second/third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first/second/third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

In the related art, the structure of a CMOS power amplifier is generally as shown in FIG1, wherein a transistor M0 configured for signal amplification and a transistor M1 in a bias circuit structure form a current mirror circuit to provide a bias voltage for the transistor M0, wherein the bias circuit structure in the dotted box in FIG1 provides a bias voltage for the amplifier tube M0. The disadvantage of the CMOS power amplifier in the related art is that the bias circuit in the dotted box provides a fixed bias voltage for the transistor M0, and the transistor M0 configured for RF signal amplification is biased at a fixed gate voltage, and its linearity is weak at high power.

Therefore, CMOS power amplifiers are difficult to design into high-power, high-linearity power amplifiers due to their low large-signal linearity. Therefore, they are rarely used as linear PAs in RF signal power amplifiers, but mainly as saturated PAs. For example, mobile amplifiers in 2G Global System for Mobile Communications (GSM) communications have been widely implemented using CMOS technology. Since CMOS technology has the outstanding advantage of low cost, if the circuit structure of CMOS power amplifiers can be improved and used for linear PAs, the cost of terminal PAs can be greatly reduced.

In order to solve the technical problems in the related art, the embodiment of the present application provides a power amplifier 1, as shown in FIG2, the power amplifier 1 includes: a bias circuit 10 and an amplifier circuit 11; the amplifier circuit 11 includes: a first transistor M1 and a shunt circuit. Among them, the bias circuit 10 provides a bias current for the amplifier circuit 11; the amplifier circuit 11 amplifies the input radio frequency signal and outputs the amplified radio frequency signal. Specifically, the gate of the first transistor M1 is connected to the bias circuit 10, the source of the first transistor M1 is grounded, and the drain of the first transistor M1 is connected to the power supply; the input end of the shunt circuit is connected to the gate of the first transistor M1, and the bias current output by the bias circuit 10 is derived through the output end of the shunt circuit to drive the first transistor M1 with the bias current. Among them, the first transistor M1 can be directly grounded or grounded through other components, which is not specifically limited in the embodiment of the present application.

In one embodiment of the present application, an improved voltage-driven power amplifier is provided, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a modulation-doped field-effect transistor (MODFET), a CMOS, a high electron mobility transistor (HEMT) amplifier, etc., which is based on the advantages of a current-driven power amplifier circuit, such as an HBT, a homojunction bipolar transistor power amplifier, and can adjust the gain of the power amplifier by adjusting the bias current, so that the gain of the amplifier can increase with the increase of power, thereby improving the linearity of the voltage-driven power amplifier. That is, the power amplifier in the embodiment of the present application can be set by setting a shunt circuit so that it can The voltage driven power amplifier is driven by current driving.

Based on this, in a specific embodiment of the present application, the Ids generated in the bias circuit structure is discharged through a shunt circuit, so that the transistor of the CMOS process can be driven by the bias current.

In one embodiment of the present application, the power amplifier is a field effect transistor power amplifier, and the transistors used in the circuit structure are all field effect transistors, such as MOSFET, MODFET, CMOS, HEMT transistors, etc., which can be the same type of field effect transistors or different types of field effect transistors. In other embodiments, the transistors in the bias circuit can be either field effect transistors or bipolar junction transistors (Bipolar Junction Transistor, BJT), such as HBT transistors, homojunction bipolar transistors, etc.

In an embodiment of the present application, when the transistor is a CMOS transistor, the input terminal of the CMOS transistor is a gate, the output terminal is a drain, and the ground terminal is a source.

In one embodiment of the present application, the structure of the power amplifier 1 is shown in FIG2 , wherein the first transistor M1 is a CMOS transistor, and the three terminals of the first transistor M1 are respectively a gate g, a drain d, and a source s. The power amplifier 1 includes the first transistor M1 configured to amplify an input RF signal and output the amplified RF signal, and a shunt circuit configured to provide the bias circuit 10 to the Ids input ground of the gate of the first transistor M1, and further includes the bias circuit 10.

In an embodiment of the present application, the gate of the first transistor M1 is connected to the bias circuit 10 , the source of the first transistor M1 is grounded, and the drain of the first transistor M1 is connected to a power source.

In one embodiment of the present application, since the driving of the first transistor M1 requires voltage, in order to achieve the purpose of improving the linearity of the first transistor M1 by using the bias current provided by the bias circuit 10, with respect to the first transistor M1 in the CMOS power amplifier in the related art, a voltage-controlled CMOS transistor can be transformed into an equivalent current-controlled device by connecting a shunt circuit in parallel, as shown in FIG3 , the first transistor M1 and the shunt circuit constitute a transformed current-controlled amplifier circuit, i.e., an improved amplifier circuit 11, and the circuit structure of the amplifier circuit 11 is shown in FIG3 .

In one embodiment of the present application, as shown in FIG3 , the amplifier circuit 11 includes a first transistor M1 and a shunt circuit. The first transistor M1 is a CMOS transistor. The first transistor M1 is connected in parallel with a shunt circuit. The circuit connection method is that the gate of the first transistor M1 is connected to the input end of the shunt circuit, the source of the first transistor M1 is grounded, and the drain of the first transistor M1 is connected to the power supply. The bias current output by the bias circuit 10 is derived through the output end of the shunt circuit, and the bias current is used to drive the first transistor M1.

It should be noted that, through the shunt circuit in the amplifier circuit, the bias current Ids output by the bias circuit to the gate of the first transistor M1 is derived through the output end of the shunt circuit, so that the gate of the first transistor M1 is input with the bias voltage provided by the bias circuit 10, and the linearity of the first transistor M1 is adjusted by the bias voltage. As the power of the input large signal changes, the input bias voltage will change with the change of power, and the linearity of the first transistor M1 is adjusted by the variable bias voltage.

It should be noted that VB provides a voltage for the bias circuit 10 , and the voltage needs to keep the bias circuit 10 in a saturation region so that the Ids of the bias circuit 10 changes linearly with the voltage, thereby making the amplifier more linear.

In one embodiment of the present application, the shunt circuit includes a second transistor; the gate of the second transistor and the drain of the second transistor are respectively connected to the gate of the first transistor; and the bias current output by the bias circuit is derived through the source of the second transistor.

In one embodiment of the present application, the shunt circuit in the amplifier circuit 11 may include a second transistor M2. As shown in FIG. 4 , the gate of the second transistor M2 and the drain of the second transistor M2 are respectively connected to the gate of the first transistor M1, and the bias current provided by the bias circuit 10 is derived through the source of the second transistor M2.

In one embodiment of the present application, the bias circuit 10 provides a bias voltage for the gate of the first transistor M1. When the input power gradually increases, the bias current provided by the bias circuit gradually increases, resulting in an increase in the bias voltage output to the gate of the first transistor M1. The changed bias voltage is used to improve the linearity of the first transistor M1.

It should be noted that the principle of its implementation has been described in the above implementation process. Specifically, you can refer to the above implementation process and will not repeat it here.

In one embodiment of the present application, the shunt circuit includes a diode; the anode of the diode is connected to the gate of the first transistor; and the bias current output by the bias circuit is derived through the cathode of the diode.

In an embodiment of the present application, the shunt circuit may be a diode, the anode of the diode is connected to the gate of the first transistor M1, and the cathode of the diode is used to derive the bias current provided by the bias circuit 10.

It should be noted that the cathode of the diode can be grounded or connected to other circuit elements.

It should be noted that the specific implementation principle can be referred to the above embodiment and will not be repeated here.

In one embodiment of the present application, the shunt current includes a first resistor; one end of the first resistor is connected to the gate of the first transistor; and the bias current output by the bias circuit is derived through the other end of the first resistor.

In an embodiment of the present application, the shunt circuit may be a resistor, one end of the resistor is connected to the gate of the first transistor M1 , and the other end of the resistor is used to derive the bias current provided by the bias circuit 10 .

It should be noted that the other end of the resistor can be grounded or connected to other circuit elements.

In one embodiment of the present application, in addition to the transistors, resistors and diodes included above, other electronic components in the shunt circuit that can conduct direct current all fall within the protection scope of the present application. Specifically, they can be selected according to actual conditions and are not specifically limited in the embodiment of the present application.

In an embodiment of the present application, the output end of the shunt circuit is grounded.

In one embodiment of the present application, the output end of the shunt circuit is grounded, and the bias current output from the bias circuit is derived through a grounding connection.

It should be noted that the output end of the shunt circuit can also be connected to other electronic circuits, as long as it can derive the bias current output from the bias circuit 10. Specifically, it can be selected according to actual conditions, and no specific limitation is made in the embodiments of the present application.

In one embodiment of the present application, the bias circuit includes a third transistor and a first capacitor; the gate of the third transistor is connected to one end of the first capacitor, and the other end of the first capacitor is grounded; the source of the third transistor is connected to the gate of the first transistor; the drain of the third transistor is connected to the power supply; A tube is used to provide a bias current to the gate of the first transistor; and a radio frequency signal transmitted in the path where the drain of the third transistor and the gate of the third transistor are located is introduced into the ground through the first capacitor.

In one embodiment of the present application, the biasing method of the CMOS power amplifier is improved to achieve a large signal gain characteristic similar to that of an HBT circuit.

In one embodiment of the present application, the gate of the first transistor M1 is connected to the source of the third transistor M3, the gate of the second transistor M2 and the drain of the second transistor M2, respectively; the source of the first transistor M1 and the source of the second transistor M2 are grounded, respectively; the drain of the first transistor M1 is connected to the DC power supply VDD; the gate of the third transistor M3 is connected to one end of the first capacitor C1; the drain of the third transistor M3 is connected to the power supply VB; the other end of the first capacitor C1 is grounded.

In one embodiment of the present application, since the driving of the first transistor M1 requires voltage, in order to achieve the purpose of improving the linearity of the first transistor M1 by using the bias voltage provided by the third transistor M3, with respect to the first transistor M1 in the CMOS power amplifier in the related art, a CMOS transistor in a diode connection mode is connected in parallel, so that the voltage-controlled CMOS transistor can be transformed into an equivalent current-controlled device. By way of example, as shown in FIG. 4 , the first transistor M1 and the second transistor M2 constitute a modified current-controlled amplifier circuit.

In one embodiment of the present application, as shown in FIG4 , the transistor amplifier circuit 11 includes a first transistor M1 and a second transistor M2, the first transistor M1 and the second transistor M2 are CMOS transistors, the first transistor M1 is connected in parallel with a second transistor M2 in a diode connection manner, and the circuit connection manner is that the gate of the first transistor M1 is connected to the gate and drain of the second transistor M2, the source of the first transistor M1 is grounded, the drain of the first transistor M1 is connected to a power supply, and the source of the second transistor M2 is grounded.

It should be noted that, through the second transistor M2 in the transistor amplifier circuit, the bias current Ids output by the third transistor M3 to the gate of the first transistor M1 is introduced into the ground through the gate of the second transistor M2, so that the bias voltage provided by the third transistor M3 is input to the gate of the first transistor M1, and the first transistor M1 is driven by the bias voltage. As the power of the input large signal changes, the input bias voltage is variable, and the linearity of the first transistor M1 is adjusted by the variable bias voltage.

In one embodiment of the present application, the structure of the power amplifier 1 is shown in FIG5 , which includes the first transistor M1 and the second transistor M2, and further includes a bias circuit 10, wherein the bias circuit 10 includes a third transistor M3 and a first capacitor C1, and the third transistor M3 is a CMOS transistor. The third transistor M3 is connected in a source follower connection manner, wherein the source of the third transistor M3 is connected to the gate of the first transistor M1, the drain of the third transistor M3 is connected to the power supply VB, and the gate of the third transistor M3 is grounded; one end of the first capacitor C1 is connected to the gate of the third transistor M3, and the other end of the first capacitor C1 is grounded.

It should be noted that the power supply VB provides a voltage for the drain of the third transistor M3 , and the voltage is required to keep the third transistor M3 in a saturation region, so that the Ids of the third transistor M3 changes linearly with the gate, thereby making the amplifier more linear.

It should be noted that the third transistor M3 is a source follower connection mode, and the third transistor M3 provides a bias current for M1. As the power of the RF signal input increases, the third transistor The Ids of M3 will increase accordingly, and correspondingly the voltage of the gate of the first transistor M1 will also increase accordingly, thereby improving the linearity of the power amplifier.

It should be noted that the above Ids represents the current of the drain of the third transistor M3 relative to the source.

In one embodiment of the present application, the first capacitor C1 is a linear capacitor, which can reduce the impedance of the gate of the third transistor M3, reduce the RF swing of the gate voltage VG2 of the third transistor M3, and make the RF signal amplitude mainly on the voltage Vgs of the gate of M3 relative to the source. The voltage and current nonlinear characteristics of M3 increase the current flowing through M3, thereby improving the gain of the power amplifier under large signals.

In one embodiment of the present application, the power amplifier 1 also includes an input impedance matching circuit and an output impedance matching circuit; the input impedance matching circuit is connected in series to the branch where the gate of the first transistor is located; the output impedance matching circuit is connected in series to the branch where the drain of the first transistor is located; the input impedance matching circuit is used to adjust the input impedance of the first transistor, and the output impedance matching circuit is used to adjust the output impedance of the first transistor, and the adjusted input impedance and the adjusted output impedance are matched with the load impedance.

In one embodiment of the present application, as shown in FIG6 , the power amplifier circuit also includes an input impedance matching circuit and an output impedance matching circuit. The input impedance matching circuit is connected in series to a branch where the gate of the first transistor M1 is located, and the output matching circuit is connected in series to a branch where the drain of the first transistor M1 is located.

In one embodiment of the present application, the input impedance matching circuit and the output impedance matching circuit respectively provide appropriate input impedance and output impedance for the power amplifier, which adjusts the input impedance and output impedance of the first transistor M1 to match the load impedance of the external circuit.

It should be noted that the load impedance of the external circuit is generally 50 ohm.

In one embodiment of the present application, the input impedance matching circuit may be a capacitor and/or a resistor; the output impedance matching circuit may be a capacitor and/or a resistor.

In one embodiment of the present application, exemplarily, as shown in Figure 7, the capacitor in the input impedance matching circuit is connected in series to the branch where the input end of the first transistor M1 is located; one end of the capacitor is connected to the gate of the first transistor M1, and the input RF signal is output from the other end of the capacitor in the input impedance matching circuit through the capacitor and transmitted to the gate of the first transistor M1; the capacitor in the output impedance matching circuit is connected in series to the branch where the output end of the first transistor M1 is located; one end of the capacitor in the input impedance matching circuit is connected to the drain of the first transistor M1, and the input RF signal is amplified by the first transistor M1, and the amplified RF signal is output from the other end of the capacitor in the output impedance matching circuit.

In one embodiment of the present application, the input impedance matching circuit includes a capacitor C2, and the RF signal input to the gate of the first transistor M1 is input through one end of the capacitor C2 and output from the other end of the capacitor C2 to the gate of the first transistor M1; the output impedance matching circuit includes a capacitor C3, and the amplified RF signal is output through the drain of the first transistor M1 and output through the capacitor C3.

In an embodiment of the present application, the input impedance matching circuit and/or the output impedance matching circuit may also be a combination circuit of an inductor, a capacitor, and a resistor. It should be noted that the input impedance matching circuit and the output impedance matching circuit may be composed of any components that can match the input impedance and output impedance of the PA, and are not limited to the above-mentioned capacitors and resistors. Specifically, they may be combined according to actual conditions. The selection is not specifically limited in the embodiments of the present application.

In one embodiment of the present application, the power amplifier also includes a first inductor; one end of the first inductor is connected to the drain of the first transistor; the other end of the first inductor is connected to a DC power supply; and the first inductor is used to isolate the RF signal transmitted in the path between the drain of the first transistor and the DC power supply.

In an embodiment of the present application, as shown in FIG8 , the power amplifier circuit further includes a first inductor L1, one end of the first inductor L1 is connected to the drain of the first transistor M1, and the other end is connected to the DC power supply VDD, and the first inductor L1 can isolate the radio frequency signal leaked through the drain of the first transistor M1 in the path where the first inductor L1 is located. Specifically, when the input radio frequency signal leaks along the gate of the first transistor M1 through the drain of the first transistor M1 to the path where the first inductor L1 is located, the first inductor L1 is used to isolate the radio frequency signal leaked in the path.

In an embodiment of the present application, when the first transistor M1 is turned on, in order to prevent the RF signal leaked by the first transistor M1 from affecting the DC power supply VDD, the first inductor L1 can be used to isolate the RF signal leaked by the first transistor M1 from the DC power supply VDD.

In one embodiment of the present application, the bias circuit also includes a fourth transistor and a fifth transistor; the gate of the fourth transistor is connected to the gate of the third transistor, the drain of the fourth transistor is respectively connected to the gate of the third transistor and a DC power supply to form a current mirror with the third transistor; the source of the fourth transistor is connected to the gate of the fifth transistor and the drain of the fifth transistor; the source of the fifth transistor is grounded.

In an embodiment of the present application, as shown in FIG. 9 , the structure of the bias circuit 10 further includes a fourth transistor M4 and a fifth transistor M5. The fourth transistor M4 and the fifth transistor M5 are connected in a cascade manner. The gate and the drain of the fourth transistor M4 are connected to the gate of the third transistor M3. The source of the fourth transistor M4 is connected to the gate and the drain of the fifth transistor M5. The source of the fifth transistor M5 is grounded. The fourth transistor M4 and the fifth transistor M5 are CMOS transistors connected in a diode connection manner.

In one embodiment of the present application, the bias circuit also includes a second resistor; one end of the second resistor is connected to the gate of the first transistor; the other end of the second resistor is connected to the source of the third transistor; when the current transmitted by the gate of the first transistor changes with the temperature of the first transistor, the second resistor is used to adjust the current to adjust the bias voltage of the first transistor.

It should be noted that the current transmitted by the gate of the first transistor may increase as the temperature of the first transistor increases, and the current is adjusted by the second resistor to adjust the bias voltage of the first transistor.

In one embodiment of the present application, as shown in FIG. 10 , the bias circuit 10 further includes a second resistor R2, one end of the second resistor R2 is connected to the source of the third transistor M3, and the other end of the second resistor R2 is connected to the gate of the first transistor M1, and negative feedback is performed on the first transistor M1 through the second resistor R2 to ensure the stability of the working state of the first transistor M1.

In one embodiment of the present application, the bias circuit also includes a third resistor; one end of the third resistor is connected to the drain of the fourth transistor; the other end of the third resistor is connected to the gate of the third transistor; and the third resistor is used to isolate the leaked RF signal from the power supply.

In one embodiment of the present application, a radio frequency signal is transmitted in a path between the gate of the third transistor and the drain of the fourth transistor, and the transmitted radio frequency signal leaks to the In the power supply, the third resistor can be used to isolate the radio frequency signal leaking to the power supply.

In an embodiment of the present application, as shown in FIG. 11 , the bias circuit further includes a third resistor R3 , one end of the third resistor R3 is connected to the gate and drain of the fourth transistor M4 , and the other end of the third resistor R3 is connected to the gate of the third transistor M3 .

In an embodiment of the present application, the radio frequency signal leaked from the third transistor M3 is isolated by the third resistor R3 to prevent the radio frequency signal from entering the fourth transistor M4 and the fifth transistor M5 to affect the power supply DC bias voltage.

In one embodiment of the present application, the input RF signal is transmitted along the source of the third transistor M3 through the gate of the third transistor M3 to the gate of the fourth transistor M4. In order to ensure that the leaked RF signal does not enter the fourth transistor M4 and the fifth transistor M5 and affect the second bias voltage, a resistor R4 is set between the third transistor M3 and the fourth transistor M4, and the resistor R4 is used to isolate the RF signal transmitted to the gate of the fourth transistor M4.

It should be noted that, depending on the implementation method of the CMOS power amplifier, the circuit structure in the embodiment of the present application can also use other types of CMOS power amplifiers, such as common source and common gate type or differential type.

It should be noted that the CMOS circuit process of the embodiment of the present application can be a pure complementary metal oxide semiconductor (Bulk CMOS) process or a silicon technology (Silicon-On-Insulator, SOI) CMOS process.

It should be noted that the CMOS transistor in the embodiment of the present application may be NMOS or PMOS.

It should be noted that the embodiment of the present application utilizes a low-cost CMOS process and achieves power characteristics similar to those of an HBT device through an improved power amplifier circuit. It has a simple structure and good versatility and can be used to design a linear power amplifier.

In an embodiment of the present application, the total width ratio of M1 and M2 can be equivalent to the current amplification factor β of HBT, and its typical value can be about 100 to 150. Its DC-IV characteristic is similar to an exponential relationship, similar to that of HBT transistor, as shown in FIG12 .

In one embodiment of the present application, as shown in FIG13, the gain power curves of two power amplifiers in the related art and the improved power amplifier of the present application are shown. As can be seen from FIG13, the gain of the traditional CMOS power amplifier generally shows a downward trend when the output power is large, and the overall performance is a gain compression characteristic; the HBT power amplifier generally has a region where the gain increases with the power due to the exponential characteristics and the effect of the bias circuit, and the overall performance is a gain expansion characteristic; and the CMOS power amplifier of the embodiment of the present application can achieve a gain curve similar to HBT through a working mode similar to the circuit designed in the HBT power amplifier, and also has a gain expansion characteristic. Since the HBT has better high-frequency performance, its single-stage gain is generally higher than that of the CMOS power amplifier. For PA, the gain expansion characteristic is more advantageous for designing a linear PA. In a multi-stage PA, it can be combined with the gain compression characteristic of the pre-amplifier to achieve a flat gain curve, thereby obtaining better linearity.

It can be understood that in a power amplifier provided in an embodiment of the present application, in the process of amplifying the power of an input RF signal, by improving the CMOS power amplifier, the bias current output in the bias circuit thereof increases with the increase of the RF signal power, thereby affecting the bias voltage at the input end of the amplifier circuit and also increasing with the increase of the bias current output in the bias circuit. The linearity of the transistor that amplifies the radio frequency signal in the amplifier circuit is improved by using a variable bias voltage. In the present application, the linearity of the transistor that amplifies the radio frequency signal is adjusted by using a variable bias voltage, and the linearity of the low-cost CMOS power amplifier is improved. Not only the linearity of the CMOS power amplifier under large signal conditions is improved, but also after the linearity of the CMOS power amplifier is improved, the high-cost GaAs HBT is replaced by the improved CMOS power amplifier, and the mobile terminal cost is lower.

It should be noted that by connecting the modified current-source device in a bias circuit similar to HBT and using the second transistor M2 connected as a source follower to provide bias to the amplifier tube, a gain expansion effect similar to that of the HBT circuit can be achieved, ultimately improving the linearity of the power amplifier.

Based on the above embodiments, a mobile terminal is also provided in the embodiments of the present application. The mobile terminal includes any one of the power amplifiers in the above embodiments. The composition of the power amplifier and its implementation principle have been discussed in the above embodiments and will not be repeated here.

It should be noted that in the embodiments of the present application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

The above is only a specific implementation of the embodiment of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

A power amplifier, comprising: a bias circuit and an amplifier circuit; the amplifier circuit comprises a first transistor and a shunt circuit;

Providing a bias current to the amplifier circuit through the bias circuit;

Amplifying the input radio frequency signal through the amplifier circuit, and outputting the amplified radio frequency signal;

The gate of the first transistor is connected to the bias circuit, the source of the first transistor is grounded, and the drain of the first transistor is connected to a power supply;

The input end of the shunt circuit is connected to the gate of the first transistor, and the first bias current output by the bias circuit is derived through the output end of the shunt circuit, so as to drive the first transistor using the first bias current.
The power amplifier of claim 1, wherein the shunt circuit comprises a second transistor;

The gate of the second transistor and the drain of the second transistor are respectively connected to the gate of the first transistor; the bias current output by the bias circuit is derived through the source of the second transistor.
The power amplifier of claim 1, wherein the shunt circuit comprises a diode;

The anode of the diode is connected to the gate of the first transistor; the bias current output by the bias circuit is derived through the cathode of the diode.
The power amplifier according to claim 1, wherein the shunt circuit comprises a first resistor;

One end of the first resistor is connected to the gate of the first transistor; the bias current output by the bias circuit is derived through the other end of the first resistor.
The power amplifier according to claim 1, wherein an output terminal of the shunt circuit is grounded.
The power amplifier according to claim 1, wherein the bias circuit comprises a third transistor and a first capacitor;

The gate of the third transistor is connected to one end of the first capacitor, and the other end of the first capacitor is grounded; the source of the third transistor is connected to the gate of the first transistor; and the drain of the third transistor is connected to a power supply;

Providing a bias current to the gate of the first transistor through the third transistor;

The radio frequency signal transmitted in the path where the drain of the third transistor and the gate of the third transistor are located is introduced into the ground through the first capacitor.
The power amplifier according to claim 1, wherein the bias circuit further comprises a fourth transistor and a fifth transistor;

The gate of the fourth transistor is connected to the gate of the third transistor; the drain of the fourth transistor is connected to the gate of the third transistor and the DC power supply respectively; the source of the fourth transistor is connected to the The gate of the fifth transistor is connected to the drain of the fifth transistor; and the source of the fifth transistor is grounded.
The power amplifier according to claim 7, wherein the bias circuit further comprises a second resistor;

One end of the second resistor is connected to the gate of the first transistor; the other end of the second resistor is connected to the source of the third transistor;

When the current transmitted by the gate of the first transistor changes with the temperature of the first transistor, the current is adjusted by using the second resistor to adjust the bias voltage of the first transistor.
The power amplifier according to claim 7, wherein the bias circuit further comprises a third resistor;

One end of the third resistor is connected to the drain of the fourth transistor; the other end of the third resistor is connected to the gate of the third transistor;

The third resistor is used to isolate the leaked radio frequency signal from the power supply.
The power amplifier according to claim 1, wherein the power amplifier is a CMOS power amplifier.
A mobile terminal, comprising the power amplifier according to any one of claims 1 to 10.