WO2024108548A1

WO2024108548A1 - Six-input dynamic comparator

Info

Publication number: WO2024108548A1
Application number: PCT/CN2022/134355
Authority: WO
Inventors: 温明杰; 雒超; 曹刚; 郭国平
Original assignee: 中国科学技术大学
Priority date: 2022-11-25
Filing date: 2022-11-25
Publication date: 2024-05-30

Abstract

Provided in the present disclosure is a six-input dynamic comparator, comprising: a dynamic amplifier and a latch, which are connected in sequence, the dynamic amplifier comprising a positive input unit, a negative input unit, a clock unit and an output unit, wherein the positive input unit comprises: a first positive input end, a second positive input end and a third positive input end; the negative input unit comprises: a first negative input end, a second negative input end and a third negative input end; the clock unit is configured to send a square-wave clock signal; and the output unit comprises a first output node and a second output node. The dynamic amplifier is configured to realize summation and amplification of six input signals, and the first output node and the second output node output a first output signal and a second output signal, respectively; and the latch is configured to amplify both the first output signal and the second output signal, respectively, so as to obtain a third output signal and a fourth output signal in a reverse manner, and is configured to compare the magnitude of third output signal and the magnitude of the fourth output signal, so as to perform discharge output.

Description

Six-input dynamic comparator

Technical Field

The present disclosure relates to the technical field of integrated circuits, and in particular to a low kick-back noise six-input dynamic comparator at extremely low temperatures.

Background technique

Analog-to-digital converters (ADCs) can convert continuous analog signals into discrete digital signals. With the continuous development of technologies such as quantum computing and deep space exploration, low-power and high-precision analog-to-digital converters are required to work normally at extremely low temperatures. The cascaded integrator feedforward noise shaping successive approximation ADC combines the advantages of DeltaSigma and SAR structures, and can significantly improve the signal-to-noise ratio by combining oversampling technology. The core of the cascaded integrator feedforward noise shaping successive approximation ADC is a multi-input comparator, which is currently difficult to meet the low kickback noise requirements in extremely low temperature environments. Therefore, how to provide a multi-input comparator that can work at extremely low temperatures while achieving low kickback noise is a technical issue that needs to be solved urgently.

Summary of the invention

The present disclosure provides a six-input dynamic comparator, comprising: a dynamic amplifier and a latch connected in sequence; the dynamic amplifier comprises: a positive input unit, a negative input unit, a clock unit, and an output unit. The positive input unit includes: a first positive input terminal Vp1, which is configured to input a first positive input signal; a second positive input terminal Vp2, which is configured to input a second positive input signal; and a third positive input terminal Vp3, which is configured to input a third positive input signal. The negative input unit includes: a first negative input terminal Vn1, which is configured to input a first negative input signal; a second negative input terminal Vn2, which is configured to input a second negative input signal; and a third negative input terminal Vn3, which is configured to input a third negative input signal. The clock unit is configured to send a square wave clock signal CLK. The output unit includes: a first output node _AP and a second output node _AN , and the dynamic amplifier is configured to realize the summing and amplification of six input signals, and the first output node _AP and the second output node _AN respectively output a first output signal AP and a second output signal AN. The latch is configured to respectively amplify and invert the first output signal and the second output signal to obtain a third output signal AP′ and a fourth output signal AN′, and discharge and output according to the comparison of the magnitude of the third output signal and the fourth output signal.

According to an embodiment of the present disclosure, the dynamic amplifier also includes a footer tube unit, which includes a first footer tube MN7 and a second footer tube MN8; wherein the gates of the first footer tube MN7 and the second footer tube MN8 are commonly connected to the clock unit, the drain of the first footer tube MN7 is connected to the second output node _AN , and the drain of the second footer tube MN8 is connected to the first output node _AP .

According to an embodiment of the present disclosure, the positive input unit also includes: a first core input tube MN1 and a first capacitor tube MN1′, both of whose gates are connected to the first positive input terminal Vp1; a second core input tube MN2 and a second capacitor tube MN2′, both of whose gates are connected to the second positive input terminal Vp2; a third core input tube MN3 and a third capacitor tube MN3′, both of whose gates are connected to the third positive input terminal Vp3; wherein the drains of the first core input tube MN1, the second core input tube MN2 and the third core input tube MN3 are respectively connected to the source of the first footer tube MN7, the source and drain of the first capacitor tube MN1′, the second capacitor tube MN2′ and the third capacitor tube MN3′ are short-circuited and respectively connected to the source of the second footer tube MN8, and the width-to-length ratio of the first core input tube MN1, the second core input tube MN2 and the third core input tube MN3 is 1:k:m, k and m represent the amplification coefficient, and k and m are integers.

According to an embodiment of the present disclosure, the negative input unit also includes: a fourth core input tube MN4 and a fourth capacitor tube MN4′, both of which have gates connected to the first negative input terminal Vn1; a fifth core input tube MN5 and a fifth capacitor tube MN5′, both of which have gates connected to the second negative input terminal Vn2; a sixth core input tube MN6 and a sixth capacitor tube MN6′, both of which have gates connected to the third negative input terminal Vn3; wherein the drains of the fourth core input tube MN4, the fifth core input tube MN5, and the sixth core input tube MN6 are respectively connected to the source of the second footer tube MN8, the source and drain of the fourth capacitor tube MN4′, the fifth capacitor tube MN5′, and the sixth capacitor tube MN6′ are short-circuited and respectively connected to the source of the first footer tube MN7, and the width-to-length ratio of the fourth core input tube MN4, the fifth core input tube MN5, and the sixth core input tube MN6 is 1:k:m, k and m represent the amplification factor, and k and m are integers.

According to an embodiment of the present disclosure, the dynamic amplifier further includes: a first reset tube MP1, a second reset tube MP2, a third reset tube MP3, and a tail tube MN9; the drain of the first reset tube MP1 is connected to the second output node _AN , and the source is connected to the power supply terminal VDD; the drain of the second reset tube MP2 is connected to the first output node _AP , and the source is connected to the power supply terminal VDD, and the gate of the second reset tube MP2 and the gate of the first reset tube MP1 are commonly connected to the clock unit; the source of the third reset tube MP3 is connected to the sources of the first core input tube MN1, the second core input tube MN2, and the third core input tube MN3, and the drain of the third reset tube MP3 is connected to the power supply terminal VDD; the drain of the tail tube MN9 is connected to the sources of the fourth core input tube MN4, the fifth core input tube MN5, and the sixth core input tube MN6 and is connected to the source of the third reset tube MP3, the source of the tail tube MN9 is grounded, and the gate of the tail tube MN9 and the gate of the third reset tube MP3 are commonly connected to the clock unit.

According to the embodiment of the present disclosure, the six-input dynamic comparator further includes: a first capacitor C1 and a second capacitor C2. The first capacitor C1 has one end connected to the second output node _AN and the other end grounded; the second capacitor C2 has one end connected to the first output node _AP and the other end grounded.

According to an embodiment of the present disclosure, the latch includes: a first inverter pair and a second inverter pair. The first inverter pair is connected to the second output node _AN and is configured to amplify and invert the second output signal AN to obtain a fourth output signal AN′; the second inverter pair is connected to the first output node _AP and is configured to amplify and invert the first output signal AP to obtain a third output signal AP′.

According to the embodiment of the present disclosure, the first inverter pair includes: a fourth PMOS transistor MP4 and a tenth NMOS transistor MN10. The gate of the fourth PMOS transistor MP4 is connected to the second output node _AN , and the source is connected to the power supply terminal VDD; the source of the tenth NMOS transistor MN10 is grounded, the gate is connected to the first output node _AP , the drain is connected to the drain of the fourth PMOS transistor MP4, and then the fourth output signal _AN ′ is output from the fourth output node AN′. The second inverter pair includes an eleventh PMOS transistor MP11 and a thirteenth NMOS transistor MN13; the gate of the eleventh PMOS transistor MP11 is connected to the first output node _AP , and the source is connected to the power supply terminal VDD; the source of the thirteenth NMOS transistor MN13 is grounded, the gate is connected to the first output node _AP , and the drain is connected to the drain of the eleventh PMOS transistor MP11, and then the third output signal _AP ′ is output from the third output node AP′.

According to the embodiment of the present disclosure, the latch further includes: a fifth PMOS tube MP5, a sixth PMOS tube MP6, a ninth PMOS tube MP9, a tenth PMOS tube MP10, a fourteenth NMOS tube MN14, and a fifteenth NMOS tube MN15.

The gate of the fifth PMOS transistor MP5 is connected to the fourth output node _AN ′, the source is connected to the power supply terminal, and the connection end of the drain is provided with the first discharge node A;

The sixth PMOS transistor MP6 has a gate connected to the fourth output node _AN ′, a source connected to the power supply terminal, and a drain connected to the fifth output node VOUTN;

The gate of the fourteenth NMOS transistor MN14 is connected to the fourth output node _AN ′, the drain is connected to the first discharge node A, and the source is grounded;

The gate of the tenth PMOS transistor MP10 is connected to the third output node A _P ′, the source is connected to the power supply terminal, and the connection end of the drain is provided with a second discharge node B;

The gate of the ninth PMOS transistor MP9 is connected to the third output node A _P ′, the source is connected to the power supply terminal, and the drain is connected to the sixth output node VOUTP;

The gate of the fifteenth NMOS transistor MN15 is connected to the third output node A _P ′, the drain is connected to the second discharge node B, and the source is grounded.

According to an embodiment of the present disclosure, the latch further includes: a third inverter pair and a fourth inverter pair.

The third inverter pair includes a seventh PMOS transistor MP7 and an eleventh NMOS transistor MN11, wherein the source of the seventh PMOS transistor MP7 is connected to the power supply terminal, the drain is connected to the fifth output node VOUTN, and the gate is connected to the sixth output node VOUTP, and the source of the eleventh NMOS transistor MN11 is connected to the first discharge node A, the drain is connected to the fifth output node VOUTN, and the gate is connected to the sixth output node VOUTP; the fourth inverter pair includes an eighth PMOS transistor MP8 and a twelfth NMOS transistor MN12, wherein the source of the eighth PMOS transistor MP8 is connected to the power supply terminal, the drain is connected to the sixth output node VOUTP, and the gate is connected to the fifth output node VOUTN, and the source of the twelfth NMOS transistor MN12 is connected to the second discharge node B, the drain is connected to the sixth output node VOUTP, and the gate is connected to the fifth output node VOUTN.

The six-input dynamic comparator provided by the present invention reduces the kick-back noise; realizes the amplification gain, weakens the offset voltage equivalent to the input of the second-stage latch, and reduces the equivalent input noise size; only needs one external clock CLK, and the present structure reduces the clock error and reduces the load of CLK; the six core input tubes achieve different amplification factors for different signal paths by setting different width-to-length ratios; and realizes fast latching.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the composition and principle of a six-input dynamic comparator according to an embodiment of the present disclosure;

FIG2 is a schematic diagram of the time domain response of a dynamic comparator;

FIG3 is a schematic diagram of the circuit structure of a six-input dynamic comparator according to an embodiment of the present disclosure;

FIG4 is a schematic diagram of the circuit structure of a multi-input dynamic amplifier of a six-input dynamic comparator according to an embodiment of the present disclosure;

FIG5 is a schematic diagram of the circuit structure of a latch of a six-input dynamic comparator according to an embodiment of the present disclosure;

FIG6 is a schematic diagram of transient simulation waveforms of a six-input dynamic comparator according to an embodiment of the present disclosure;

FIG7 is a schematic diagram of an equivalent input noise simulation of a six-input dynamic comparator according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of an offset voltage simulation of a six-input dynamic comparator according to an embodiment of the present disclosure.

FIG9 a is a schematic diagram showing a comparison of the kickback noise voltage between the six-input dynamic comparator according to an embodiment of the present disclosure and the traditional double-tail current-mode comparator at room temperature 300K.

FIG9 b is a schematic diagram showing a comparison of the kickback noise voltage between the six-input dynamic comparator of the embodiment of the present disclosure and the traditional double-tail current-type comparator under the condition of an extremely low temperature of 4.2K.

Detailed ways

The present invention provides a six-input dynamic comparator, which solves the problem of multi-input comparator circuit design in cascaded integrator feedforward noise shaping successive approximation ADC by cascading a pre-stage dynamic amplifier and a secondary latch circuit, and can realize six-way input voltage signals, while ensuring a faster comparison speed, reducing offset voltage and kickback noise. At the same time, the six-input dynamic comparator can work at an extremely low temperature (4.2K) to realize the functions of amplifying signals and comparing the magnitudes of multiple input voltages, while reducing input offset voltage and achieving lower kickback noise, thereby meeting the requirements of high precision and high resolution.

In the process of implementing the present disclosure, the inventors found that the multi-input comparator needs to amplify and compare the six input signals, namely the differential residual voltage signal Vres+, Vres-, the residual first-order integral signal Vint1+, Vint1-, and the residual second-order integral signal Vint2+, Vint2- in the capacitor DAC. Usually, according to actual needs, Vres+ and Vres- are not amplified, while the residual first-order integral signal Vint1+, Vint1- and the residual second-order integral signal Vint2+, Vint2- need to achieve k times and m times of amplification factors, and then the six signals are added and compared. The open-loop comparator has no feedback loop and consumes a lot of power. Under the requirements of low-power design, a dynamic latch comparator is required, and its basic principle is amplification and positive feedback. The traditional StrongArm type dynamic comparator cannot work at advanced process nodes (low power supply voltage). Since the latch structure has a large input offset voltage Voffset, the equivalent input offset voltage of the comparator is also relatively large. At the same time, the rail-to-rail voltage change of the input tube drain voltage brings a large kickback noise. In high-resolution scenarios, the input difference may cause bit errors and metastable problems in the uV level voltage signal. The double-tail current type dynamic comparator separates the gain stage and the latch stage, but at the cost of requiring a larger current to bring additional power consumption, and also requires an additional CLKB clock that is opposite to CLK. This structure requires CLK and CLKB to have precise timing requirements. Using an inverter to implement CLKB will also bring a larger capacitive load to CLK. Due to the presence of input tube gate-drain capacitance, changes in the drain voltage of the double-tail current type and Elzakker type dynamic comparators will be coupled to the input end, resulting in larger kickback noise. Therefore, the present disclosure provides a better low kickback noise six-input dynamic comparator suitable for extremely low temperatures.

In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

In an embodiment of the present disclosure, a six-input dynamic comparator is provided. As shown in FIG. 1 and FIG. 3 to FIG. 5 , the six-input dynamic comparator includes: a dynamic amplifier and a latch connected in sequence;

The dynamic amplifier, as an amplification stage, comprises: a positive input unit, a negative input unit, a clock unit, and an output unit.

The positive input unit comprises: a first positive input terminal Vp1 Vp1, configured to input a first positive input signal Vip; a second positive input terminal Vp2, configured to input a second positive input signal Vint1p; a third positive input terminal Vp3, configured to input a third positive input signal Vint2p;

The negative input unit comprises: a first negative input terminal Vn1 configured to input a first negative input signal Vin; a second negative input terminal Vn2 configured to input a second negative input signal Vint1n; a third negative input terminal Vn3 configured to input a third negative input signal Vint2n;

A clock unit, configured to emit a square wave clock signal CLK;

An output unit, comprising: a first output node _AP and a second output node _AN , wherein the dynamic amplifier is configured to implement summing and amplifying six input signals, and the first output node _AP and the second output node _AN respectively output a first output signal AP and a second output signal AN;

The latch is configured as a latch stage to amplify and invert the first output signal and the second output signal to obtain a third output signal AP′ and a fourth output signal AN′, respectively, and to discharge and output based on the comparison of the magnitudes of the third output signal and the fourth output signal to obtain final output signals Voutp and Voutn.

According to an embodiment of the present disclosure, the positive input unit also includes: a first core input tube MN1 and a first capacitor tube MN1′, both of whose gates are connected to the first positive input terminal Vp1; a second core input tube MN2 and a second capacitor tube MN2′, both of whose gates are connected to the second positive input terminal Vp2; a third core input tube MN3 and a third capacitor tube MN3′, both of whose gates are connected to the third positive input terminal Vp3; wherein the drains of the first core input tube MN1, the second core input tube MN2 and the third core input tube MN3 are respectively connected to the source of the first footer tube MN7, the source and drain of the first capacitor tube MN1′, the second capacitor tube MN2′ and the third capacitor tube MN3′ are short-circuited and respectively connected to the source of the second footer tube MN8, and the width-to-length ratio of the first core input tube MN1, the second core input tube MN2 and the third core input tube MN3 is 1:k:m, k and m represent the amplification factor, and k and m are integers.

According to an embodiment of the present disclosure, the negative input unit further includes: a fourth core input tube MN4 and a fourth capacitor tube MN4′, both of whose gates are connected to the first negative input terminal Vn1; a fifth core input tube MN5 and a fifth capacitor tube MN5′, both of whose gates are connected to the second negative input terminal Vn2; a sixth core input tube MN6 and a sixth capacitor tube MN6′, both of whose gates are connected to the third negative input terminal Vn3; wherein the drains of the fourth core input tube MN4, the fifth core input tube MN5 and the sixth core input tube MN6 are respectively connected to the source of the second footer tube MN8, the source and drain of the fourth capacitor tube MN4′, the fifth capacitor tube MN5′ and the sixth capacitor tube MN6′ are short-circuited and respectively connected to the source of the first footer tube MN7, and the width-to-length ratio of the fourth core input tube MN4, the fifth core input tube MN5 and the sixth core input tube MN6 is 1:k:m, k and m represent amplification factors, k and m are integers, it should be noted that k and m can also be non-integers, and the specific values are adjusted according to the actual application.

According to an embodiment of the present disclosure, the dynamic amplifier further includes: a first reset tube MP1, a drain connected to the second output node _AN , and a source connected to the power supply terminal VDD; a second reset tube MP2, a drain connected to the first output node _AP , a source connected to the power supply terminal VDD, and a gate of the second reset tube MP2 and a gate of the first reset tube MP1 are commonly connected to a clock unit; a third reset tube MP3, a source connected to the sources of the first core input tube MN1, the second core input tube MN2, and the third core input tube MN3, and a drain of the third reset tube MP3 is connected to the power supply terminal VDD; a tail tube MN9, a drain connected to the sources of the fourth core input tube MN4, the fifth core input tube MN5, and the sixth core input tube MN6 and connected to the source of the third reset tube MP3, a source of the tail tube MN9 is grounded, and a gate of the tail tube MN9 and a gate of the third reset tube MP3 are commonly connected to the clock unit.

According to the embodiment of the present disclosure, the dynamic amplifier further includes: a first capacitor C1, one end of which is connected to the second output node _AN and the other end is grounded; and a second capacitor C2, one end of which is connected to the first output node _AP and the other end is grounded.

According to an embodiment of the present disclosure, a latch includes: a first inverter pair and a second inverter pair.

The first inverter pair is connected to the second output node _AN , and is configured to amplify and invert the second output signal AN to obtain a fourth output signal AN′; the second inverter pair is connected to the first output node _AP , and is configured to amplify and invert the first output signal AP to obtain a third output signal AP′.

According to the embodiment of the present disclosure, the first inverter pair includes: a fourth PMOS transistor MP4, whose gate is connected to the second output node _AN , and whose source is connected to the power supply terminal VDD; a tenth NMOS transistor MN10, whose source is grounded, whose gate is connected to the first output node _AP , whose drain is connected to the drain of the fourth PMOS transistor MP4, and then outputs a fourth output signal _AN ′ through the fourth output node AN′.

The second inverter pair includes: an eleventh PMOS transistor MP11, whose gate is connected to the first output node _AP , and whose source is connected to the power supply terminal VDD; a thirteenth NMOS transistor MN13, whose source is grounded, whose gate is connected to the first output node _AP , and whose drain is connected to the drain of the eleventh PMOS transistor MP11, and then outputs a third output signal _AP ′ through a third output node AP′.

According to the embodiment of the present disclosure, the capacitance value CL of the first capacitor C1 is the gate capacitance value of the fourth PMOS tube MP4 in the latch connected to the first output node _AP , and the capacitance value CL+ΔC of the second capacitor C2 is the gate capacitance value of the tenth NMOS tube MN10 in the latch, wherein the closer ΔC is to zero, the better, reflecting the capacitance difference caused by the process difference between the tenth NMOS tube MN10 and the fourth PMOS tube MP4.

According to the embodiment of the present disclosure, the latch further includes: a fifth PMOS tube MP5, a gate connected to the fourth output node _AN ′, a source connected to the power supply terminal, and a connection end of the drain is provided with a first discharge node A; a sixth PMOS tube MP6, a gate connected to the fourth output node _AN ′, a source connected to the power supply terminal, and a drain connected to the fifth output node VOUTN; a fourteenth NMOS tube MN14, a gate connected to the fourth output node _AN ′, a drain connected to the first discharge node A, and a source grounded; a tenth PMOS tube MP10, a gate connected to the third output node _AP ′, a source connected to the power supply terminal, and a connection end of the drain is provided with a second discharge node B; a ninth PMOS tube MP9, a gate connected to the third output node _AP ′, a source connected to the power supply terminal, and a drain connected to the sixth output node VOUTP; a fifteenth NMOS tube MN15, a gate connected to the third output node _AP ′, a drain connected to the second discharge node B, and a source grounded.

According to the embodiment of the present disclosure, the latch further includes: a third inverter pair, including a seventh PMOS tube MP7 and an eleventh NMOS tube MN11, wherein the source of the seventh PMOS tube MP7 is connected to the power supply terminal, the drain is connected to the fifth output node VOUTN, and the gate is connected to the sixth output node VOUTP, the source of the eleventh NMOS tube MN11 is connected to the first discharge node A, the drain is connected to the fifth output node VOUTN, and the gate is connected to the sixth output node VOUTP; a fourth inverter pair, including an eighth PMOS tube MP8 and a twelfth NMOS tube MN12, wherein the source of the eighth PMOS tube MP8 is connected to the power supply terminal, the drain is connected to the sixth output node VOUTP, and the gate is connected to the fifth output node VOUTN, the source of the twelfth NMOS tube MN12 is connected to the second discharge node B, the drain is connected to the sixth output node VOUTP, and the gate is connected to the fifth output node VOUTN. Finally, the final output signals Voutn and Voutp are outputted through the fifth output node VOUTN and the sixth output node VOUTP, respectively.

More specifically, as shown in FIG. 1 , the six-input dynamic comparator is composed of a first-stage dynamic amplifier and a second-stage latch, and realizes the comparison and fast latching functions of six input signals under power supply and a square wave clock signal CLK with a duty cycle of 50%.

FIG2 is a schematic diagram of the time domain response of a dynamic comparator. As shown in FIG2, an open-loop amplifier has the characteristics of high gain, but low bandwidth, which requires a longer settling time _t1 for high and low levels. Assuming that the gain of a unipolar amplifier is A, the settling time is τ, and the main pole frequency of the amplifier is p(ω), then

GBW is the gain bandwidth product, GBW = A*p(ω), the amplification speed of the latch signal shows an exponential growth trend with time. When the initial signal is larger, the latch speed of the comparator is faster (such as t ₂ ). The input signal is first quickly amplified to a certain value by the open-loop comparator, and then it is used as the input of the latch comparator for positive feedback amplification, so that the comparison result can be quickly obtained.

FIG3 is a schematic diagram of the circuit structure of a six-input dynamic comparator of an embodiment of the present disclosure; the circuit of the six-input dynamic comparator includes a first-stage dynamic amplifier and a second-stage latch. The first-stage dynamic amplifier requires a CLK clock signal and uses six core input tubes MN1, MN4, MN2, MN5, MN3, and MN6, whose width-to-length ratios are 1:1:k:k:m:m, respectively; wherein k and m represent the amplification factor. At the same time, the six cross-coupled tubes MN1', MN4', MN2', MN5', MN3', and MN6' are intended to reduce the kickback noise, and their width-to-length ratios are 3/5 of the corresponding core input tubes. By means of complementary cross-coupling, lower kickback noise is achieved. At the same time, the summing and amplification function of the six input signals is realized. The second stage is the latch stage, and in the comparison stage, the two inverters MN10, MN13, MP4, and MP11 are used to further amplify the signal amplified by the first stage, thereby improving the gain. At the same time, MN14, MN15 and two back-to-back inverters MN11, MN12, MP7, and MP8 are used to realize the functions of comparing the size of the voltage signal and fast latching.

Fig. 4 is a schematic diagram of the circuit structure of a multi-input dynamic amplifier of a six-input dynamic comparator of an embodiment of the present disclosure; wherein the sampling differential pair structure reduces the common-mode interference at the input end and suppresses the common-mode noise. MN1, MN2, MN3, MN4, MN5, and MN6 are core input tubes, MN1', MN2', MN3', MN4', MN5', and MN6' are capacitor tubes with source and drain short-circuited, and the width-to-length ratio of the capacitor tube is 3/5 of the corresponding core input tube, and the kickback noise is reduced by cross-coupling. A pair of footer tubes MN7 and MN8 are added under the output nodes _AN and _AN to increase the overdrive voltage of the input tube, which can reduce the kickback noise. The core input tubes MN1, MN2, MN3, MN4, MN5, and MN6 convert voltage to current for the six input signals, and realize dynamic amplification when CLK is at a high level.

5 is a schematic diagram of the circuit structure of the latch of the six-input dynamic comparator of the embodiment of the present disclosure; compared with the traditional two-stage dynamic comparator, MP4, MN10, MP11, MN10 are used as inverter pairs to amplify the signals AN and AP emitted from the AN _nodes and _AN nodes into reverse signals AN` and AP`, respectively, and at the same time, MP6, MN14, MP9, MNl5 are used to further amplify and transmit them to the output latch stage (latch stage), thereby achieving a relatively high amplification gain, reducing the offset voltage of the second-stage latch equivalent to the input, and reducing the equivalent input noise size.

Here’s how it works:

Reset stage: When CLK is low level (GND), MP1, MP2, MP3 are turned on, MP1, MP2 set the first output node _AP and the second output node _AN to VDD, footer tubes MN7, MN8 are turned off, and the source level of input tubes MN1, MN2, MN3, MN4, MN5, MN6 is connected to VDD by the opening of MP3, so that the input tubes are quickly turned off, which speeds up the comparison speed. The first output node _AP and the second output node _AN node are charged to the high level VDD, the third output node _AP 'and the fourth output node AN _' become the low level GND, MP5, MP6, MP9, MP10 are turned on, and the fifth output node VOUTN, the sixth output node VOUTP, the first discharge node A, and the second discharge node B signals are pulled to the high level VDD, so as to realize the reset function of the amplifier stage and the latch stage.

Comparison stage: CLK is high level, reset tubes MP1, MP2, MP3 are turned off, and MN7, MN8, MN9 are turned on. The first output node _AP and the second output node _AN start to discharge from VDD, and the discharge speed depends on the input voltage amplitude. When the _AN or _AP node drops to VDD-|V _thp |, MP4 and MP11 are turned on. MP4, MN10, MP11, MN13 act as an inverter pair to amplify the first output signal AP and the second output signal AN output from the _AN and _AP nodes into the inverted signals of the third output signal AP′ and the fourth output signal AN′, and then AN` and AP` are further amplified and transmitted to the output latch level by MP6, MN14, MP9, MN15. MN14 and MN15 are turned on successively according to the size of AN` and AP`, and the first discharge node A and the second discharge node B are discharged to GND,

Take AP`(t) as the voltage value of the third output node A _P ′, AN`(t) as the voltage value of the fourth output node _AN ′, if AP`(t)＜AN`(t), MN14 will be turned on first, and the first discharge node A will be discharged first. When the voltage of the first discharge node A is lower than (VDD-V _thn ), MN11 will be turned on first, and the output node VOUTN will be discharged. At the same time, through the positive feedback latch of MP7, MN11, MP8, and MN12, VOUTN will be locked at the low level GND, and VOUTP will be locked at the logic high level VDD; on the contrary, if AP`(t)＞AN`(t), VOUTN will be locked at the high level VDD, and VOUTP will be locked at the logic low level GND.

Considering that the preamplifier is the main noise contributor, the noise generated by the latch can be ignored. Then the equivalent input noise is

for

Among them, A(t) is the amplification factor, C _L is the load capacitance value of capacitor C1 or capacitor C2, K is the Boltzmann constant, T is the temperature, γ is the thermal noise coefficient of the MOS tube, g _m is the transconductance value of the six core input tubes, and t is the dynamic amplification time.

A(t) = g _m t/C _L

t＝ _2CLΔV / _Ib

Wherein, _gm is the transconductance value of the six input tubes, ΔV is the voltage difference between the first output signal AP and the second output signal AN in the comparison phase, and _Ib is the current value of the tail current tube MN9.

By increasing the width-to-length ratio of the differential input pair, the amplification factor can be increased and the equivalent input noise can be reduced. Meanwhile, reducing the width-to-length ratio of the tail current tube can achieve a smaller source-drain current I _b of the tail current tube MN9, achieve a larger dynamic amplification time t, and further reduce input noise.

Compared with the traditional dynamic comparator which needs a clock signal CLK and a clock reverse signal CLKB, the new comparator only needs an external clock CLK. The structure reduces the clock error and the load of CLK. The six core input tubes are set with different width-to-length ratios of 1:1:k:k:m:m; where k and m represent the amplification coefficients, so as to achieve different amplification factors for different signal paths. The introduction of footer tubes MN4 and MN5 reduces the kickback noise and increases the overdrive voltage V _GS -V _TH of the input tube. The six cross-coupled tubes are used for complementation to further reduce the impact of the kickback noise. The MP3 tube speeds up the reset speed in the reset stage. The signal amplified in the first stage is further amplified by the inverter in the second stage latch and MP6, MN14, MP9, and MN15, achieving a relatively high amplification gain, reducing the offset voltage of the second stage latch equivalent to the input, and reducing the equivalent input noise. The fast latching function is realized by the back-to-back latch stage.

Using the Spectre simulation tool, at the 180nm process node, VDD = 1.8V, the frequency of the clock signal _fclk = 1GHz, the capacitance CL of the load capacitor (C1, C2) connected to the first output node _AP and the second output node _AN is 500fF, and the simulation verification is performed under Temp = 27℃ and Temp = -269℃ respectively. The input common mode voltage is Vcm = 0.9mV, Vcm is the common mode voltage value of the input signal, which is a constant DC level to ensure the normal operation of the MOS tube. Using the Cadence ultra-low temperature library simulation, the transient characteristics of the comparator under the input voltage Vp1-Vn1 = -50mV are simulated, and the waveform is shown in Figure 6. It can be seen that each node of the comparator works normally in the clock reset stage and the comparison stage, and the full function of the design can be realized. Using the transient noise simulation method at room temperature Temp = 27℃, as shown in Figure 7, the X-axis ΔVin is Vp1-Vn1, indicating the input differential voltage size when Vp2 Vp3 Vn2 Vn3 is equal to the common mode voltage. The Y-axis P is the probability that the comparator outputs correctly. When the input voltage difference is 400μV, the probability of the number of correct output signals at the output terminals VOUTP and VOUTN is 84%. It can be concluded that the standard deviation of the comparator noise is 400μV, and the power of the noise is the square of the standard deviation of the noise, which is equal to 0.16μV ^2. At low temperatures, because the temperature decreases, the transient noise will be further reduced to about 1/71 of the original value. The offset voltage of the comparator is further obtained by Monte Carlo simulation, as shown in Figure 8, the horizontal axis Values represents the size of the offset voltage, and the vertical axis represents the number of samples. It can be seen that the average value of the offset voltage is 0.65mV and the standard deviation is 5.44mV. Figures 9a and 9b respectively reflect the kickback noise simulation of the six-input dynamic comparator of the present disclosure and the traditional double-tail current type comparator under two conditions of low temperature 4.2K and room temperature 300K. Combined with Figures 9a and 9b, the six-input dynamic comparator of the present disclosure has lower kickback noise than the traditional double-tail current type comparator.

The present disclosure provides a six-input dynamic comparator, the process used in the circuit has passed the test, characterization, and modeling at extremely low temperatures, and the dynamic comparator circuit has also passed the functional simulation verification of the extremely low temperature environment. In the quantum computing reading system, a low-power and high-precision analog-to-digital converter is required to work normally at extremely low temperatures. The cascaded integrator feedforward noise shaping successive approximation ADC combines the advantages of DeltaSigma and SAR structures, and can significantly improve the signal-to-noise ratio by combining oversampling technology. The core of the ADC of this structure is a low-power dynamic comparator, and a new technology of multi-input comparator that can work at extremely low temperatures and achieve low kickback noise is urgently needed. In view of the above problems, a low kickback noise six-input dynamic comparator that can work at extremely low temperatures (4K) is designed. Compared with the traditional dynamic comparator that requires two clock signals, the new comparator only needs a single clock, which reduces the requirements for clock accuracy. The six cross-coupled tubes are complementary to reduce the impact of kickback noise. A relatively high amplification gain is achieved by adding an inverter and an amplifier tube in the second stage, which weakens the offset voltage equivalent to the input of the second-stage latch, and reduces the equivalent input noise size. Its functions and noise characteristics were simulated and verified based on the ultra-low temperature model library, while achieving lower power consumption.

The specific implementations of the present disclosure described above do not constitute a limitation on the protection scope of the present disclosure. Any other corresponding changes and modifications made according to the technical concept of the present disclosure should be included in the protection scope of the claims of the present disclosure.

Claims

A six-input dynamic comparator comprises: a dynamic amplifier and a latch connected in sequence;

The dynamic amplifier comprises:

Positive input unit, including:

The first positive input terminal Vp1 is configured to input a first positive input signal;

The second positive input terminal Vp2 is configured to input a second positive input signal;

The third positive input terminal Vp3 is configured to input a third positive input signal;

Negative input unit, including:

The first negative input terminal Vn1 is configured to input a first negative input signal;

The second negative input terminal Vn2 is configured to input a second negative input signal;

The third negative input terminal Vn3 is configured to input a third negative input signal;

A clock unit configured to emit a square wave clock signal CLK; and

An output unit, comprising: a first output node AP and a second output node AN , wherein the dynamic amplifier is configured to implement summing and amplifying six input signals, and the first output node AP and the second output node AN respectively output a first output signal AP and a second output signal AN;

The latch is configured to amplify and invert the first output signal and the second output signal to obtain a third output signal AP′ and a fourth output signal AN′, respectively, and to perform discharge output according to the comparison of the magnitudes of the third output signal and the fourth output signal.
According to the six-input dynamic comparator of claim 1, the dynamic amplifier further comprises a footer tube unit, the footer tube unit comprises a first footer tube MN7 and a second footer tube MN8;

The gates of the first footer transistor MN7 and the second footer transistor MN8 are commonly connected to the clock unit, the drain of the first footer transistor MN7 is connected to the second output node AN , and the drain of the second footer transistor MN8 is connected to the first output node AP .
The six-input dynamic comparator according to claim 2, the positive input unit further comprising:

The gates are both connected to the first core input transistor MN1 and the first capacitor transistor MN1′ of the first positive input terminal Vp1;

The gates of the second core input transistor MN2 and the second capacitor transistor MN2′ are both connected to the second positive input terminal Vp2;

The gates of the third core input transistor MN3 and the third capacitor transistor MN3′ are both connected to the third positive input terminal Vp3;

Among them, the drains of the first core input tube MN1, the second core input tube MN2, and the third core input tube MN3 are respectively connected to the source of the first footer tube MN7, the sources and drains of the first capacitor tube MN1′, the second capacitor tube MN2′, and the third capacitor tube MN3′ are short-circuited and respectively connected to the source of the second footer tube MN8, and the width-to-length ratio of the first core input tube MN1, the second core input tube MN2, and the third core input tube MN3 is 1:k:m, k and m represent amplification factors, and k and m are integers.
The six-input dynamic comparator according to claim 2, the negative input unit further comprising:

A fourth core input transistor MN4 and a fourth capacitor transistor MN4', both of which have gates connected to the first negative input terminal Vn1;

A fifth core input transistor MN5 and a fifth capacitor transistor MN5′, both of which have gates connected to the second negative input terminal Vn2;

A sixth core input transistor MN6 and a sixth capacitor transistor MN6′, both of which have gates connected to the third negative input terminal Vn3;

Among them, the drains of the fourth core input tube MN4, the fifth core input tube MN5, and the sixth core input tube MN6 are respectively connected to the source of the second footer tube MN8, the sources and drains of the fourth capacitor tube MN4′, the fifth capacitor tube MN5′, and the sixth capacitor tube MN6′ are short-circuited and respectively connected to the source of the first footer tube MN7, and the width-to-length ratio of the fourth core input tube MN4, the fifth core input tube MN5, and the sixth core input tube MN6 is 1:k:m, k and m represent amplification factors, and k and m are integers.
According to any one of claims 1 to 4, the six-input dynamic comparator, the dynamic amplifier further comprises:

A first reset transistor MP1, with a drain connected to the second output node AN and a source connected to the power supply terminal VDD;

A second reset tube MP2, with a drain connected to the first output node AP , a source connected to the power supply terminal VDD, and a gate of the second reset tube MP2 and a gate of the first reset tube MP1 connected to the clock unit;

A third reset tube MP3, a source electrode of which is connected to the sources of the first core input tube MN1, the second core input tube MN2 and the third core input tube MN3, and a drain electrode of the third reset tube MP3 is connected to the power supply terminal VDD;

The drain of the tail tube MN9 is connected to the sources of the fourth core input tube MN4, the fifth core input tube MN5, and the sixth core input tube MN6 and is connected to the source of the third reset tube MP3. The source of the tail tube MN9 is grounded, and the gate of the tail tube MN9 and the gate of the third reset tube MP3 are commonly connected to the clock unit.
The six-input dynamic comparator according to any one of claims 1 to 4, further comprising:

A first capacitor C1, one end of which is connected to the second output node AN , and the other end of which is grounded; and

The second capacitor C2 has one end connected to the first output node A P , and the other end grounded.
The six-input dynamic comparator according to claim 1, wherein the latch comprises:

A first inverter pair is connected to the second output node AN and is configured to amplify and invert the second output signal AN to obtain a fourth output signal AN′; and

The second inverter pair is connected to the first output node AP , and is configured to amplify and invert the first output signal AP to obtain a third output signal AP'.
The six-input dynamic comparator according to claim 7, wherein:

The first inverter pair comprises:

A fourth PMOS transistor MP4, having a gate connected to the second output node AN and a source connected to the power supply terminal VDD;

The tenth NMOS transistor MN10 has a source electrode grounded, a gate electrode connected to the first output node AP , a drain electrode connected to the drain electrode of the fourth PMOS transistor MP4, and outputs a fourth output signal AN ′ through the fourth output node AN′;

The second inverter pair comprises:

An eleventh PMOS transistor MP11, a gate electrode of which is connected to the first output node AP , and a source electrode of which is connected to the power supply terminal VDD;

The thirteenth NMOS transistor MN13 has a source connected to the ground, a gate connected to the first output node AP , and a drain connected to the drain of the eleventh PMOS transistor MP11, and then outputs a third output signal AP ' through the third output node AP'.
The six-input dynamic comparator according to claim 8, wherein the latch further comprises:

A fifth PMOS transistor MP5, having a gate connected to the fourth output node AN ′, a source connected to the power supply terminal, and a drain terminal provided with a first discharge node A;

a sixth PMOS transistor MP6, having a gate connected to the fourth output node AN ′, a source connected to the power supply terminal, and a drain connected to the fifth output node VOUTN;

A fourteenth NMOS transistor MN14, having a gate connected to the fourth output node AN ′, a drain connected to the first discharge node A, and a source grounded;

a tenth PMOS transistor MP10, having a gate connected to the third output node A P ′, a source connected to the power supply terminal, and a connection end of the drain provided with a second discharge node B;

a ninth PMOS transistor MP9, having a gate connected to the third output node A P ′, a source connected to the power supply terminal, and a drain connected to the sixth output node VOUTP;

The fifteenth NMOS transistor MN15 has a gate connected to the third output node A P ′, a drain connected to the second discharge node B, and a source grounded.
The six-input dynamic comparator according to claim 8, wherein the latch further comprises:

a third inverter pair, comprising a seventh PMOS transistor MP7 and an eleventh NMOS transistor MN11, wherein the source of the seventh PMOS transistor MP7 is connected to the power supply terminal, the drain is connected to the fifth output node VOUTN, and the gate is connected to the sixth output node VOUTP, and the source of the eleventh NMOS transistor MN11 is connected to the first discharge node A, the drain is connected to the fifth output node VOUTN, and the gate is connected to the sixth output node VOUTP;

The fourth inverter pair includes an eighth PMOS tube MP8 and a twelfth NMOS tube MN12, wherein the source of the eighth PMOS tube MP8 is connected to the power supply terminal, the drain is connected to the sixth output node VOUTP, and the gate is connected to the fifth output node VOUTN; the source of the twelfth NMOS tube MN12 is connected to the second discharge node B, the drain is connected to the sixth output node VOUTP, and the gate is connected to the fifth output node VOUTN.