WO2024108488A1

WO2024108488A1 - Nitride-based semiconductor device and method for manufacturing the same

Info

Publication number: WO2024108488A1
Application number: PCT/CN2022/134081
Authority: WO
Inventors: Ronghui Hao
Original assignee: Innoscience (Zhuhai) Technology Co., Ltd.
Priority date: 2022-11-24
Filing date: 2022-11-24
Publication date: 2024-05-30
Also published as: CN118251774A

Abstract

The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source and a drain electrodes, and a gate electrode. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer and has a bandgap greater than that of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. The source and the drain electrodes are disposed over the second nitride-based semiconductor layer. The gate electrode is disposed over the second nitride-based semiconductor layer and located between the source and drain electrodes. The second nitride-based semiconductor layer has a thicker portion located at least one side of the gate electrode.

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventor: Ronghui HAO

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having a barrier layer with an asymmetrical profile.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source and a drain electrodes, and a gate electrode. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer and has a bandgap greater than that of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. The source and the drain electrodes are disposed over the second nitride-based semiconductor layer. The gate electrode is disposed over the second nitride-based semiconductor layer and located between the source and drain electrodes. The second nitride-based semiconductor layer has a thicker portion located at least one side of the gate electrode.

In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed. An intermediate nitride-based semiconductor layer is formed over the first nitride-based semiconductor layer, wherein the intermediate second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer. At least a portion of the intermediate nitride-based semiconductor layer is removed to form a second nitride-based semiconductor layer having at least one thicker portion. A gate electrode is formed on the second nitride-based semiconductor layer, wherein the thicker portion of the second nitride-based semiconductor layer is located at a side of the gate electrode.

In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a channel layer, a barrier layer, a gate structure, and a source and a drain electrodes. The barrier layer is disposed over the channel layer. The gate structure includes a doped semiconductor layer disposed on the barrier layer and a gate electrode disposed on the doped semiconductor layer. The source and the drain electrodes are disposed over the barrier layer and located at two different sides of the gate structure. The barrier layer has a first protruding portion located in a drain region between the drain electrode and the gate electrode and a thinner portion at least having a part directly under the gate structure. The first protruding portion has a top surface higher than that of the thinner portion.

By the above configuration, in the present disclosure, by performing a patterning process on an intermediate nitride-based semiconductor layer to form a barrier layer with a thicker portion at a drain side of the gate electrode, hot electron effect can be relieved. The manufacturing method of the present disclosure can be adapted to manufacture a miniaturized semiconductor device, and the manufactured semiconductor device can have a good reliability.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D show different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 4 is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 5 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 6 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 7 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure; and

FIG. 8 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure.

Referring to FIG. 1, the nitride-based semiconductor device 1A includes a substrate 10, a buffer layer 12, nitride-based

semiconductor layers

14, 16A,

electrodes

20, 22, a doped nitride-based semiconductor layer 32, a gate electrode 34, and a passivation layer 40.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

The buffer layer 12 is disposed between the substrate 10 and the nitride-based semiconductor layer 14. The buffer layer 12 can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 14, thereby curing defects due to the mismatches/difference. The buffer layer 12 may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and the buffer layer 12. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer 12. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

In order to conform to the trend of miniaturization of electronic devices, semiconductor devices are manufactured to be smaller. To make the miniaturized semiconductor device work normally, the external power supply voltage should be reduced in proportion to the size of the device. However, it is difficult to reduce the magnitude of the external power supply voltage in practice. As an excessive voltage is applied to the miniaturized semiconductor device, the electric field in the device would maintain at a high level. Energy of some electrons is significantly higher than the average kinetic energy in thermal balance and become hot electrons. Hot electron effect would deteriorate the reliability of the such device.

In order to overcome the aforesaid issue, the present disclosure provides a novel structure.

The nitride-based semiconductor layer 14 can be disposed on/over/above the buffer layer 12. After that, an intermediate nitride-based semiconductor layer is formed to cover the nitride-based semiconductor layer 14. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _xGa _(1–x) N where x ≤ 1. The exemplary materials of the intermediate nitride-based semiconductor layer can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layer 14 and the intermediate nitride-based semiconductor layer are selected such that the intermediate nitride-based semiconductor layer has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 14, which causes electron affinities thereof different from each other and forms a heterojunction therebetween.

For example, when the nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the intermediate nitride-based semiconductor layer can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layer 14 and the intermediate nitride-based semiconductor layer can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the nitride-based semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

Under a normal operation, a voltage applied to a drain electrode is usually higher than a voltage applied to a source voltage. Thus, a drain region between the gate and the drain electrodes would have a high electric field intensity, and this is the region where the hot electron effect affects the most.

To relieve the hot electron effect in the drain region, in the present disclosure, a patterning process is performed to the intermediate nitride-based semiconductor layer to remove excess portions thereof, such that a nitride-based semiconductor 16A is formed, in which the nitride-based semiconductor layer 16A is formed to include a thinner portion 162, a thickness variable portion 164, and a thicker portion 166. That is to say, the nitride-based semiconductor 16A is formed to have an asymmetry profile. The formed nitride-based semiconductor layer 16A is disposed on/over/above the nitride-based semiconductor layer 14. The formed nitride-based semiconductor layer 16A makes contact with the nitride-based semiconductor layer 14.

The thicker portion 166 has a thickness greater than that of the thinner portion 162. The thicker portion 166 has a top surface higher than that of the thinner portion 162, and thus the thicker portion 166 can serve as a protruding portion. The thickness variable portion 164 has a variable thickness. The thickness variable portion 164 is located between the thinner portion 162 and the thicker portion 166. The thickness variable portion 164 connects the thinner portion 162 to the thicker portion 166. The top surface of the thickness variable portion 164 connects a top surface of the thinner portion 162 to a top surface of the thicker thickness variable portion 164.

Since the formation of the 2DEG region results from polarization effect of the nitride-based semiconductor layers 14 and 16A, the thickness ratio of the nitride-based

semiconductor layers

16A and 14 determines the extent of polarization effect therein. Thus, a zone Z1 of the 2DEG region under the thicker portion 166 of the nitride-based semiconductor 16A has the highest electron density. A zone Z2 of the 2DEG region under the thinner portion 166 of the nitride-based semiconductor 16A has the lowest electron density. The zone Z1 of the 2DEG region directly under the thicker portion 166 has a greater electron density than that of a zone Z2 of the 2DEG region directly under the thinner portion 162. A zone Z3 of the 2DEG region under the thickness variable portion 164 of the nitride-based semiconductor 16A has a variable electron density. In the embodiment, the top surface of the thickness variable portion 164 is an inclined top surface, and thus the zone Z3 has a linearly varied electron density. In some embodiments, the shape of the top surface of the thickness variable portion 164 can be adjusted, so as to adjust the electron density distribution thereunder. For example, in some embodiments, the top surface of the thickness variable portion 164 can be a curved top surface or a combination of inclined top surface and curved top surface.

The

electrodes

20, 22 are disposed on/over/above the thinner portion 162 and the thicker portion 166 of the nitride-based semiconductor layer 16A, respectively, such that the electrode 20 has a bottom surface lower than that of the electrode 22. The

electrodes

20, 22 make contact with the thinner portion 162 and the thicker portion 166 of the nitride-based semiconductor layer 16A, respectively. In some embodiments, the electrode 20 can serve as a source electrode, and the electrode 22 can serve as a drain electrode.

In some embodiments, the

electrodes

20 and 22 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

20 and 22 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. Each of the

electrodes

20 and 22 may be a single layer, or plural layers of the same or different composition. The

electrodes

20 and 22 form ohmic contacts with the nitride-based semiconductor layer 16A. Furthermore, the ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

20 and 22.

The doped nitride-based semiconductor layer 32 is disposed on/over/above the thinner portion 162 of the nitride-based semiconductor layer 16A. The doped nitride-based semiconductor layer 32 makes contact with the thinner portion 162 of the nitride-based semiconductor layer 16A. The gate electrode 34 is disposed on/over/above the doped nitride-based semiconductor layer 32. The gate electrode 34 makes contact with the doped nitride-based semiconductor layer 32. The top surface of the thickness variable portion 164 faces the gate electrode 34. The thickness variable portion 164 is located between the gate electrode 34 and the electrode 22. The doped nitride-based semiconductor layer 32 is disposed between the gate electrode 34 and the nitride-based semiconductor layer 16A. The doped nitride-based semiconductor layer 32 and the gate electrode 34 are located/disposed between the electrode 20 and the electrode 22. The doped nitride-based semiconductor layer 32 and the gate electrode 34 can act as a gate structure.

A width of the doped nitride-based semiconductor layer 32 is greater than that of the gate electrode 34. In some embodiments, a width of the doped nitride-based semiconductor layer 32 is substantially the same as a width of the gate electrode 34. The profiles of the doped nitride-based semiconductor layer 32 and the gate electrode 34 are the same, for example, both of them are rectangular profiles. In other embodiments, the profiles of the doped nitride-based semiconductor layer 32 and the gate electrode 34 can be different from each other, for example, the profile of the doped nitride-based semiconductor layer 32 can be a trapezoid profile, while the profile of the gate electrode 34 can be a rectangular profile.

In the exemplary illustration of FIG. 1, the nitride-based semiconductor device 1A is an enhancement mode device, which is in a normally-off state when the gate electrode 34 is at approximately zero bias. Specifically, the doped nitride-based semiconductor layer 32 may create at least one p-n junction with the nitride-based semiconductor layer 16A to deplete the 2DEG region, such that at least one zone Z4 of the 2DEG region corresponding to a position below the corresponding the doped nitride-based semiconductor layer 32 has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked.

Due to such mechanism, the nitride-based semiconductor device 1A has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 34 or a voltage applied to the gate electrode 34 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 34) , the zone of the 2DEG region below the gate electrode 34 is kept blocked, and thus no current flows therethrough.

In some embodiments, the doped nitride-based semiconductor layer 32 can be omitted, such that the nitride-based semiconductor device 1A is a depletion-mode device, which means the nitride-based semiconductor device 1A in a normally-on state at zero gate-source voltage.

The gate electrode 34 (or the gate structure) has two opposite sides, for example, a source side SS and a drain side DS. A region between the gate electrode 34 and the electrode 22 serving as a drain electrode can serve as a drain region, and a region between the gate electrode 34 and the electrode 20 serving as a source electrode can serve as a source region. The electrode 20 serving as a source electrode and a part of the thinner portion 162 thereunder are located at the source side SS of the gate electrode 34 (i.e., the source region) . The electrode 22 serving as a drain electrode and the thicker portion 166 thereunder are located at the drain side DS of the gate electrode 34 (i.e., the drain region) . The thinner portion 162 horizontally extends from a position P1 between the thicker portion 166 and the gate electrode 34 to a position P2 under the electrode 20, such that at least a part of the thinner portion 162 is directly under the gate structure. That is to say, the thinner portion 162 extends from the drain region to the source region.

Based on the above, in the present disclosure, the thicker portion 166 of the nitride-based semiconductor layer 16A is located at the drain side DS of the gate electrode 34 (or the drain region) , and the electrode 22 serving as the drain electrode is located on/over/above the thicker portion 166. Thus, by such a configuration, the zone Z1 of the 2DEG region with high electron density is located at a drain side DS of the gate electrode 34, which is advantageous to relieve hot electron effect in the drain region. Furthermore, the current density of the nitride-based semiconductor device 1A can be improved, and thus the performance of the nitride-based semiconductor device 1A can be elevated.

The doped nitride-based semiconductor layer 32 can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped nitride-based semiconductor layer 32 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg. In some embodiments, the nitride-based semiconductor layer 14 includes undoped GaN and the nitride-based semiconductor layer 16A includes AlGaN, and the doped nitride-based semiconductor layer 32 is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the nitride-based semiconductor device 1A into an off-state condition.

The exemplary materials of the gate electrode 34 may include metals or metal compounds. The gate electrode 34 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.

The passivation layer 40 is disposed on/over/above the nitride-based semiconductor layer 16A, the

electrodes

20, 22, and the doped nitride-based semiconductor layer 32, and the gate electrode 34. The passivation layer 40 covers the nitride-based semiconductor layer 16A, the

electrodes

20, 22, and the doped nitride-based semiconductor layer 32, and the gate electrode 34. The material of the passivation layer 40 can include, for example but are not limited to, dielectric materials. For example, the passivation layer 40 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the passivation layer 40 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO _x layer, a SiN _x layer, a high-k dielectric material (e.g., HfO ₂, Al ₂O ₃, TiO ₂, HfZrO, Ta ₂O ₃, HfSiO ₄, ZrO ₂, ZrSiO ₂, etc) , or combinations thereof.

Different stages of a method for manufacturing the nitride-based semiconductor device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D as described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, a substrate 10 is provided. A buffer layer 12 is formed on/over/above the substrate 10 by using deposition techniques. A nitride-based semiconductor layer 14 is formed on/over/above the buffer layer 12. An intermediate nitride-based semiconductor layer 16’ is formed on/over/above the first nitride-based semiconductor layer 14, in which the intermediate nitride-based semiconductor layer 16’ has a bandgap greater than that of the nitride-based semiconductor layer 14, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.

Referring to FIG. 2B, a patterning process is performed on the intermediate nitride-based semiconductor layer 16’, such that at least a portion of the intermediate nitride-based semiconductor layer 16’ is removed, thereby forming a nitride-based semiconductor layer 16 with a thicker portion 166.

Referring to FIG. 2C, an intermediate doped nitride-based semiconductor layer 32’ is formed to cover an entirety of a top surface of the nitride-based semiconductor layer 16, in which the intermediate doped nitride-based semiconductor layer 32’ can be a p-type doped nitride-based semiconductor layer.

Referring to FIG 2D, portions of the intermediate doped nitride-based semiconductor layer 32’ are removed, and thus a doped nitride-based semiconductor layer 32 is formed. A gate electrode 34 is formed on/over/above the doped nitride-based semiconductor layer 32.

Electrodes

20, 22 are formed on the nitride-based semiconductor layer 16, such that the

electrodes

20, 22 are formed at a source side SS and a drain side DS of the gate electrode 34, respectively. The thicker portion 166 of the nitride-based semiconductor layer 16A is located at the drain side DS of the gate electrode 34. Then, a passivation layer 40 is formed to cover the nitride-based semiconductor layer 16A, the

electrodes

20, 22, the doped nitride-based semiconductor layer 32, and the gate electrode 34, thereby obtaining the nitride-based semiconductor device 1A in the FIG. 1.

FIG. 3 is a vertical view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure. The nitride-based semiconductor device 1B is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the nitride-based semiconductor layer 16B has a thinner portion 162,

portions

1641, 1642 with a variable thickness, and

thicker portions

1661, 1662. Each of the

thicker portions

1661, 1662 has a top surface higher than that of the thinner portion 162.

Specifically, the thickness variable portion 1641 and the thicker portion 1661 are located at the drain side DS of the gate electrode 34, and the thickness variable portion 1642 and the thicker portion 1662 are located at the source side SS of the gate electrode 34. The thickness variable portion 1641 connects the thinner portion 162 to the thicker portion 1661. The thickness variable portion 1642 connects the thinner portion 162 to the thicker portion 1662. The thicker portion 1661 at the drain side DS has the substantially same thickness as that of the thicker portion 1662 at the source side SS, such that a bottom surface of the electrode 20 disposed on the thicker portion 1661 and a bottom surface of the electrode 22 disposed on the thicker portion 1662 are at the substantially same height level.

Thus, by the aforesaid configuration, the zones Z1 of the 2DEG region with high electron density are located/formed at the source side SS and the drain side DS of the gate electrode 34, respectively. Therefore, hot electron effect can be further alleviated. In addition, the zones Z3 of the 2DEG region with variable electron density are located/formed at the source side SS and the drain side DS of the gate electrode 34, respectively. Such a configuration can provide/form a variable electric field distribution above the zones Z3 at the drain side DS and source side SS, respectively, so as to avoid excessive electric field variation at both sides DS, SS. The reliability of the nitride-based semiconductor device 1A can be further improved.

During the formation of the nitride-based semiconductor layer 16, a mask layer applied to the patterning process can be replaced, such that a portion of the intermediate nitride-based semiconductor layer is removed, thereby forming the nitride-based semiconductor layer 16B having two

thicker portions

1661, 1662 located at two opposite sides SS, DS of the gate electrode 34, respectively.

FIG. 4 is a vertical view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. The nitride-based semiconductor device 1C is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the nitride-based semiconductor layer 16C has two thickness

variable portions

1641, 1642, and two

thicker portions

1661, 1662 at the drain side DS.

Specifically, the thicker portion 1662 has a thickness greater than that of the thicker portion 1661. The thickness variable portion 1641 is located between the thinner portion 162 and the thicker portion 1661. The thickness variable portion 1641 connects the thinner portion 162 to the thicker portion 1661. The thickness variable portion 1642 connects the thicker portion 1661 to the thicker portion 1662. The thickness

variable portions

1641, 1642, and the

thicker portions

1661, 1662 can act/viewed as a protruding portion having a top surface with different heights.

Thus, by the aforesaid configuration, the zones Z1a, Z1b of the 2DEG region with high electron density are located/formed at the drain side DS of the gate electrode 34, in which the zones Z1b near the electrode 22 has an electron density higher than that of the zone Z1a away from the electrode 22. In the embodiment, since the electrode 22 can serve as a drain electrode, a region near the electrode 22 has a relatively high electric field intensity. By aforesaid thickness design, the location of the zone Z1a of the 2DEG region with highest electron density can be near the electrode 22, hot electron effect near the electrode 22 can be further alleviated. In addition, the zones Z3a, Z3b of the 2DEG region with variable electron density are located/formed at the drain side DS of the gate electrode 34, such that a zone Z’ of 2DEG region including zones Z1a, Z1b, Z3a, Z3b can have an increasing and continuous electron density from the gate electrode 34 to the electrode 22. Such a configuration can provide/form a variable electric field distribution at the drain side DS, so as to avoid excessive electric field variation at the drain side DS. The reliability of the nitride-based semiconductor device 1C can be further improved.

In some embodiments, the top surface of the thickness variable portion 1642 may be more oblique than the top surface of the thickness variable portion 1641. The reason to such the configuration is that the thickness variable portion 1642 can enhance the electron density strongly than that provided by the thickness variable portion 1641 (i.e., stronger increasing per unit distance) . The thickness variable portion 1642 is further from the gate electrode 34 than the thickness variable portion 1641 is, so enhancement to the electron density at the zone Z3b is reasonable and the gate-drain side can still keep from potential breakdown risk.

FIG. 5 is a top view of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure. The nitride-based semiconductor device 1D is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the doped nitride-based semiconductor layer 32D extends toward the electrode 22 and terminates at a position on the thickness variable portion 164, such that at least a part of the thickness variable portion 164 is covered by the doped nitride-based semiconductor layer 32D. At least a portion of the doped nitride-based semiconductor layer 32D climbs inclined and upwardly along the top surface of the thickness variable portion 164. Regarding the thickness variable portion 164, the underlying electron density may increase as the thickness varied. The sharp variation in the thickness will make sharp variation in the electron density as well, which reduces the device reliability. The slowly gradual variation in the thickness will make the device dimension increase. That is, in order to meet a specific device requirement, it may difficult to achieve as only the thickness serving as a device design factor. The doped nitride-based semiconductor layer 32D climbing the top surface of the thickness variable portion 164 can further support the modulation to the underlying electron density.

FIG. 6 is a top view of a nitride-based semiconductor device 1E according to some embodiments of the present disclosure. The nitride-based semiconductor device 1E is similar to the nitride-based semiconductor device 1D as described and illustrated with reference to FIG. 5, except that the top surface of the thickness variable portion 164 is fully covered by the doped nitride-based semiconductor layer 32E. Such a configuration can meet a specific device requirement. For example, the sharp change to the electron density may occur at a position far away the gate-drain side, so as to avoid the breakdown at the gate-drain side.

FIG. 7 is a vertical cross-sectional view of a semiconductor device 1F according to some embodiments of the present disclosure. The nitride-based semiconductor device 1F is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the semiconductor device 1F further includes field plates SPF1, SPF2. Each of the field plates SPF1, SPF2 is connected to the electrode 20. The field plate SPF2 is higher than the field plate SPF1. The field plate SPF1 horizontally extends from the electrode 20 to a position directly above the gate electrode 34 and to a position between the gate electrode 34 and the electrode 22. The end surface of the field plate SPF1 vertically align with the start of the slope of the nitride-based semiconductor layer 16. The field plate SPF2 horizontally extends from the electrode 20 to a position between the gate electrode 34 and the electrode 22. The end surface of the field plate SPF2 can exceed the slope of the nitride-based semiconductor layer 16. The length of the field plate SPF2 is greater than that of the field plate SPF1. In some embodiments, the electrode 20 can serve as a source electrode, and thus the field plates SPF1, SPF2 can serve as source field plates. Such a configuration can achieve a better electric field distribution. The configuration is made according to the consideration of parasitic capacitance.

The exemplary materials of the field plates SPF1, SPF2 can include, for example but are not limited to, conductive materials, such as Ti, Ta, TiN, TaN, or combinations thereof. In some embodiments, other conductive materials such as Al, Cu doped Si, and alloys including these materials may also be used. In some embodiments, the exemplary materials of the field plates SPF1, SPF2 can be identical or similar with the electrode 20.

FIG. 8 is a vertical cross-sectional view of a semiconductor device 1G according to some embodiments of the present disclosure. The nitride-based semiconductor device 1G is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the nitride-based semiconductor layer 16G has two

portions

167, 168. The bottom portion 167 makes contact with the nitride-based semiconductor layer 14. The bottom portion 167 extends from a position under the electrode 20 to a position under the electrode 22. The top portion 168 is located in the drain region of the semiconductor device 1G. The top portion 168 is disposed on/over/above the bottom portion 167. Thus, such a configuration can regionally thicken thickness of the nitride-based semiconductor layer 16G, so as to induce a 2DEG region with high electron density in the drain region of the semiconductor device 1G.

In some embodiments, the exemplary material of the bottom portion 167 can be the same as that of the top portion 168. In some embodiments, the top portion 168 can have the same III-V compound but different conductivity. For instance, the bottom portion 167 can include undoped AlGaN layer, and the top portion 168 can include n-doped AlGaN. By such a material selection, the nitride-based semiconductor layer 16G can be formed in the following manufacturing steps. Following the step in the FIG. 2B, an implanting process is performed on a top portion of the thicker portion 166 of the nitride-based semiconductor layer 16A with n-type dopants. Thus, a n-type doped top portion 168 in the FIG. 8 can be formed. A bottom portion of the nitride-based semiconductor layer 16A can be maintained to be undoped for serving as the bottom portion 167 in the FIG. 8.

In some embodiments, the exemplary material of the bottom portion 167 can be different from that of the top portion 168. For example, the nitride-based semiconductor layer 167 can include AlGaN, and the top portion 168 can include AlN, AlInN, or combinations thereof. By such a material selection, the bottom portion 167 and the top portion 168 of the nitride-based semiconductor layer 16G are formed in sequence. In some embodiments, the top portion 168 of the nitride-based semiconductor layer 16G is formed by regrowth from the bottom portion 167. In some embodiments, an etching stage can be performed after the growth, so at least one portion of the bottom portion 167 is free from the coverage of the top portion 168. The advantageous of the regrowth is to make the top portion 168 have at least one character different than that of the bottom portion 167. As such, an interface IF can be formed between the bottom and

top portions

167, 168. In other point of view, the nitride-based semiconductor layer 16G can be two-step formed.

Based on the above, in the present disclosure, a patterning process can be performed on an intermediate nitride-based semiconductor layer with a higher band gap (e.g., the barrier layer) , such that the formed barrier layer can have a thicker portion at least one side of the gate electrode, thereby adjusting an electron density of a zone of the 2DEG region thereunder. In some cases, the thicker portion of the barrier layer can be formed at the drain side of the gate electrode. By aforesaid configuration, hot electron effect can be alleviated. The design of the present disclosure can enable the miniaturized semiconductor device to suppress hot electron effect instead of reducing the magnitude of the external power supply voltage. Thus, the design of the present disclosure can be adapted to the miniaturized semiconductor device.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer and having a bandgap greater than that of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction;

a source and a drain electrodes disposed over the second nitride-based semiconductor layer; and

a gate electrode disposed over the second nitride-based semiconductor layer and located between the source and drain electrodes,

wherein the second nitride-based semiconductor layer has a thicker portion located at least one side of the gate electrode.
The nitride-based semiconductor device of any of proceeding claims, wherein the second nitride-based semiconductor layer has the thicker portion at a drain side of the gate electrode and a thinner portion at a source side of the gate electrode.
The nitride-based semiconductor device of any of proceeding claims, wherein the source electrode is disposed over the thinner portion of the second nitride-based semiconductor layer, and the drain electrode is disposed over the thicker portion of the second nitride-based semiconductor layer, such that the source electrode has a bottom surface lower than that of the drain electrode.
The nitride-based semiconductor device of any of proceeding claims, wherein a first zone of the 2DEG region directly under the thicker portion has a greater electron density than that of a second zone of the 2DEG region directly under the thinner portion.
The nitride-based semiconductor device of any of proceeding claims, wherein the second nitride-based semiconductor layer has a thickness variable portion between the thinner and the thicker portions.
The nitride-based semiconductor device of any of proceeding claims, wherein a third zone of the 2DEG region directly under the thickness variable portion has a variable electron density.
The nitride-based semiconductor device of any of proceeding claims, wherein the thickness variable portion is located between the gate and the drain electrodes.
The nitride-based semiconductor device of any of proceeding claims, wherein the thickness variable portion has a top surface facing the gate electrode, and the top surface thereof is connected a top surface of the thinner portion to a top surface of the thicker portion.
The nitride-based semiconductor device of any of proceeding claims, wherein the top side surface of the thickness variable portion is an inclined top surface, a curved top surface, or a combination thereof.
The nitride-based semiconductor device of any of proceeding claims, wherein the second nitride-based semiconductor layer has two thicker portions at a drain side and a source side of the gate electrode, respectively, and a thinner portion located directly under the gate electrode.
The nitride-based semiconductor device of any of proceeding claims, wherein the thicker portion at the drain side has the substantially same thickness as that of the thicker portion at the source side.
The nitride-based semiconductor device of any of proceeding claims, wherein a bottom surface of the source electrode and a bottom surface of the drain electrode are at the substantially same height level.
The nitride-based semiconductor device of any of proceeding claims, wherein the second nitride-based semiconductor layer further has two thickness variable portions at the drain side and the source side of the gate electrode, respectively, wherein the thickness variable portion at the drain side connects the thinner portion to the thicker portion at the drain side, and the thickness variable portion at the source side connects the thinner portion to the thicker portion at the source side.
The nitride-based semiconductor device of any of proceeding claims, further comprising a doped nitride-based semiconductor layer disposed between the second nitride-based semiconductor layer and the gate electrode.
The nitride-based semiconductor device of any of proceeding claims, further comprising a passivation layer covering the source, drain, and gate electrodes.
A manufacturing method of a nitride-based semiconductor device, comprising:

forming a first nitride-based semiconductor layer;

forming an intermediate nitride-based semiconductor layer over the first nitride-based semiconductor layer, wherein the intermediate nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer;

removing at least a portion of the intermediate nitride-based semiconductor layer to form a second nitride-based semiconductor layer having at least one thicker portion; and

forming a gate electrode on the second nitride-based semiconductor layer, wherein the thicker portion of the second nitride-based semiconductor layer is located at a side of the gate electrode.
The manufacturing method of any of proceeding claims, further comprising:

forming a source and a drain electrodes at a source side and a drain side of the gate electrode, respectively.
The manufacturing method of any of proceeding claims, wherein the thicker portion of the second nitride-based semiconductor layer is located at the drain side of the gate electrode.
The manufacturing method of any of proceeding claims, wherein the thicker portion of the second nitride-based semiconductor layer is located at the drain side of the gate electrode.
The manufacturing method of any of proceeding claims, wherein a portion of the intermediate nitride-based semiconductor layer is removed, such that the second nitride-based semiconductor layer has two thicker portions at two opposite sides of the gate electrode.
A semiconductor device, comprising:

a channel layer;

a barrier layer disposed over the channel layer;

a gate structure comprising a doped semiconductor layer disposed on the barrier layer and a gate electrode disposed on the doped semiconductor layer; and

a source and a drain electrodes disposed over the barrier layer and located at two different sides of the gate structure,

wherein the barrier layer has a first protruding portion located in a drain region between the drain electrode and the gate electrode and a thinner portion at least having a part directly under the gate structure,

wherein the first protruding portion has a top surface higher than that of the thinner portion.
The semiconductor device of any of proceeding claims, wherein the thinner portion extends from a first position between the first protruding portion and the gate electrode to a second position under the source electrode.
The semiconductor device of any of proceeding claims, further comprising a second protruding portion located in a source region between the source electrode and the gate electrode, wherein the thinner portion is located between the first protruding portion and the second protruding portion, and the second protruding portion has a top surface higher than that of the thinner portion.
The semiconductor device of any of proceeding claims, wherein the first protruding potion has a top surface with different heights.
The semiconductor device of any of proceeding claims, wherein the barrier layer has an asymmetry profile.