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WO2024103853A1 - 功率器件驱动电路、半导体器件测试电路及系统 - Google Patents

功率器件驱动电路、半导体器件测试电路及系统 Download PDF

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Publication number
WO2024103853A1
WO2024103853A1 PCT/CN2023/111159 CN2023111159W WO2024103853A1 WO 2024103853 A1 WO2024103853 A1 WO 2024103853A1 CN 2023111159 W CN2023111159 W CN 2023111159W WO 2024103853 A1 WO2024103853 A1 WO 2024103853A1
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WO
WIPO (PCT)
Prior art keywords
circuit
power device
tested
gate
buffer circuit
Prior art date
Application number
PCT/CN2023/111159
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English (en)
French (fr)
Inventor
许亚坡
洪燕东
刘成
叶念慈
张建山
Original Assignee
湖南三安半导体有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 湖南三安半导体有限责任公司 filed Critical 湖南三安半导体有限责任公司
Publication of WO2024103853A1 publication Critical patent/WO2024103853A1/zh

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present application generally relates to the field of semiconductor device technology, and more specifically, to a power device driving circuit, a semiconductor device testing circuit, and a semiconductor device testing system.
  • the present application proposes a power device driving circuit, which can delay the initial driving signal of the power device to be tested so that the power device to be tested can be turned on when the drain-source voltage of the power device to be tested oscillates to the bottom, thereby meeting the application requirements of the power device.
  • the present application provides a power device driving circuit, including: a signal source, used to generate an initial driving signal; and a buffer circuit, electrically connected between the signal source and the gate of the power device to be tested, used to receive the initial driving signal, and based on the test conditions of the power device to be tested, delay the initial driving signal and output the delayed gate driving signal, wherein the gate driving signal is used to control the power device to be tested to turn on when the drain-source voltage of the power device to be tested oscillates to the bottom.
  • the present application also provides a semiconductor device test circuit, including a primary circuit and a secondary circuit, wherein the primary circuit includes a primary winding and a primary power device to be tested connected in series, the two ends of the primary circuit are used to connect a test power supply to form a loop, the secondary circuit includes a secondary winding and a secondary transistor to be tested connected in series, the primary winding and the secondary winding form a flyback transformer, the primary circuit and the secondary circuit are connected in parallel and grounded, wherein the primary circuit also includes: a first power device drive circuit connected to the primary power device to be tested, the first power device drive circuit includes: a signal source for generating an initial drive signal; and a buffer circuit electrically connected between the signal source and the gate of the primary power device to be tested, for processing the initial drive signal according to the test condition of the primary power device to be tested, and outputting a first gate drive signal for the primary power device to be tested, so as to control the primary power device to be tested to turn on when the drain-source voltage of the primary power device to be
  • the present application also provides a semiconductor device testing system, comprising: a plurality of primary circuits and secondary circuits, wherein each of the primary circuits comprises a primary winding and a primary power device to be tested connected in series, the two ends of each primary circuit are used to connect a test power supply to form a loop, each of the secondary circuits comprises a secondary winding and a secondary transistor to be tested connected in series, each of the primary windings and each of the secondary windings form a flyback transformer, each of the primary circuits and each of the secondary circuits are connected in parallel and grounded; wherein each of the primary circuits also comprises a first power device driving circuit connected to the primary power device to be tested; and/or the secondary transistor to be tested comprises a secondary power device to be tested, and each of the secondary circuits also comprises a second power device driving circuit connected to the secondary power device to be tested; wherein the first power device driving circuit and/or the second power device driving circuit comprises a power device driving circuit, and the power device driving circuit comprises: a signal source for
  • the power device to be tested it is used to receive the initial drive signal, based on the test conditions of the power device to be tested, the initial drive signal is delayed and the gate drive signal after the delay process is output, wherein the gate drive signal is used to control the power device to be tested to turn on when the drain-source voltage of the power device to be tested oscillates to the bottom of the valley; multiple power device drive circuits generate the same initial drive signal based on their signal sources, wherein each of the power device drive circuits is used to process the initial drive signal according to the test conditions of its corresponding primary power device to be tested or the secondary power device to be tested to obtain a gate drive signal, and output a corresponding gate drive signal to its corresponding primary power device to be tested or the secondary power device to be tested, so as to control its corresponding primary power device to be tested to turn on when the drain-source voltage of the primary power device to be tested oscillates to the bottom of the valley based on the corresponding gate drive signal, or control its corresponding secondary power device to be tested to turn on when
  • the light emitting device, backplane assembly and display panel described in the present application have at least the following beneficial effects:
  • the initial driving signal of the power device to be tested is delayed based on the buffer circuit in the power device driving circuit, so that the power device to be tested can be turned on when the drain-source voltage of the power device to be tested oscillates to the bottom, thereby meeting the application requirements of the power device.
  • the power device driving circuit can be applied to a semiconductor device test circuit to ensure that the simulated circuit operating conditions of the power device are consistent with the actual operating conditions, thereby improving the test accuracy.
  • the power device driving circuit can also be applied to a semiconductor device test system to overcome the problem of inconsistent test conditions and power consumption of the power device to be tested during batch testing, thereby effectively ensuring that each power device to be tested in the semiconductor device test system has consistent operating conditions.
  • FIG1 is a structural diagram showing a power device driving circuit according to a first embodiment of the present application.
  • FIG2 is a structural diagram showing a power device driving circuit according to a second embodiment of the present application.
  • FIG. 3 is a structural diagram showing a power device driving circuit according to a third embodiment of the present application.
  • FIG. 4 is a structural diagram showing a power device driving circuit according to a fourth embodiment of the present application.
  • FIG. 5 is a structural diagram showing a power device driving circuit according to a fifth embodiment of the present application.
  • FIG6 is a structural diagram showing a semiconductor device test circuit according to an embodiment of the present application.
  • FIG. 7 is a structural diagram showing a semiconductor device testing system according to an embodiment of the present application.
  • the inventor has found through research that for power devices such as gallium nitride power transistors, a driving signal is usually used to directly trigger the opening or closing of the power device.
  • power devices are required to work under corresponding working conditions.
  • the power devices to be tested in the system need to work under flyback circuit conditions. At this time, the power devices to be tested need to be turned on when their drain-source voltage meets the minimum resonant voltage (that is, valley voltage).
  • the source-drain voltage resonance period of the power device to be tested may be different, resulting in the turning-on condition of the power device to be tested (for example, the drain-source voltage of the power device to be tested is turned on before it resonates to the valley bottom) not meeting the application requirements.
  • the inventor also found that the driving signal of the power device can be adjusted so that the driving signal can trigger the power device to be turned on in a timely manner to meet the application requirements of the power device.
  • FIG1 is a structural diagram showing a power device driving circuit 100 according to an embodiment of the present application.
  • the power device driving circuit 100 may include a buffer circuit 101 and a signal source 102.
  • a power device to be tested 103 is also shown in FIG1 , and the buffer circuit 101 is electrically connected between the signal source 102 and the power device to be tested 103.
  • the aforementioned signal source can be used to generate an initial drive signal.
  • the signal source may specifically include a signal generator or a pulse generating circuit.
  • the initial drive signal can be generated by a signal generator or a pulse generating circuit, and in some implementation scenarios, the initial drive signal may include a high and low level with a settable duty cycle. It should be noted that the detailed description of the initial drive signal here is only an exemplary description.
  • the aforementioned buffer circuit 101 can receive an initial drive signal, and based on the test conditions of the power device to be tested, can delay the initial drive signal and output a gate drive signal after delay processing.
  • the gate drive signal can be used to control the power device to be tested to turn on when the drain-source voltage of the power device to be tested oscillates to the bottom. Therefore, based on the test conditions of the power device to be tested, the initial drive signal can be adaptively delayed through the buffer circuit to adjust the turn-on time point of the power device to be tested, so that the adjusted drive signal can trigger the power device to turn on in time to meet the application requirements of the power device.
  • the aforementioned power device may include a gallium nitride power device, a silicon carbide power device or other power devices, and the specific type of the power device is not limited here.
  • the aforementioned power device driving circuit may further include a driver.
  • the driver may receive a gate driving signal output from the buffer circuit 101 and output the gate driving signal to the power device to be tested.
  • the aforementioned buffer circuit 101 may be implemented in a variety of forms in specific applications, which will be further described below in conjunction with FIG. 2 to FIG. 5 .
  • FIG2 is a block diagram showing a power device driving circuit 200 according to another embodiment of the present application. It is understood that FIG2 is a specific implementation of the power device driving circuit 100 in FIG1. Therefore, the aforementioned detailed description in conjunction with FIG1 is also used in FIG2.
  • the initial driving signal in FIG2 can be generated by a signal generator or a pulse generating circuit.
  • the driver 104 is also shown in the power driving circuit 200, and the driver 104 can be deleted or retained according to actual application requirements.
  • the power device driving circuit 200 may include a buffer circuit 101 and a signal source 102.
  • the aforementioned buffer circuit 101 may include a first RC buffer circuit, and the first RC buffer circuit may utilize the charging and discharging process of the capacitor therein to perform delay adjustment on the aforementioned initial driving signal.
  • the first RC buffer circuit may include a first resistor R1 and a first capacitor C1. Among them, one end of the first capacitor C1 is connected to the first resistor R1, and the other end of the first capacitor C1 is grounded. The initial driving signal will charge the first capacitor C1 after passing through the first resistor R1.
  • the initial driving signal is adjusted by the charging and discharging time of the first capacitor C1 to obtain a gate driving signal.
  • the gate driving signal can be directly output to the power device 103 to be tested, or output to the power device 103 to be tested via the driver 104.
  • the aforementioned first resistor R1 may include a fixed resistor, and the required fixed resistor may be determined specifically according to the application requirements of the device to be driven, and the power device driving circuit 200 may be adaptively adjusted by replacing fixed resistors of different resistance values to meet the application requirements.
  • the aforementioned first resistor R1 may also include an adjustable resistor.
  • the resistance of the adjustable resistor can be directly adjusted according to the application requirements, without the need for cumbersome resistor replacement operations.
  • the drain-source voltage when the power device to be driven is turned on can be regulated based on the resistance adjustment of the adjustable resistor.
  • the resistance can be adjusted in conjunction with an oscilloscope.
  • the turn-on status of the power device to be driven can be detected by an oscilloscope until it is detected by the oscilloscope that the power device to be driven is turned on when its drain-source voltage is at the bottom, at which time the resistance adjustment is stopped.
  • the description of the resistance adjustment process of the adjustable resistor here is only an exemplary description, and the scheme of the present application is not limited thereto.
  • FIG3 is a block diagram showing a power device driving circuit 300 according to another embodiment of the present application. It can be understood that FIG3 is another specific implementation of the power device driving circuit 100 in FIG1. In addition, FIG3 can also be understood as a further supplement to the function of the power device driving circuit 200 in FIG2. Therefore, the aforementioned related detailed descriptions in combination with FIG1 and FIG2 are also used in FIG3.
  • the initial driving signal in FIG3 can be generated by a signal generator or a pulse generating circuit.
  • the driver 104 is also shown in the power driving circuit 300, and the driver 104 can be deleted or retained according to the actual application requirements.
  • the power device driving circuit 300 may include a buffer circuit 101 and a signal source 102.
  • the buffer circuit includes a second RC buffer circuit and a first logic gate adjustment circuit.
  • the second RC buffer circuit includes a second resistor R2 and a second capacitor C2, one end of the second capacitor C2 is connected to the second resistor R2, and the other end of the second capacitor C2 is grounded. It can be understood that the second RC buffer circuit can have the same circuit structure as the first RC buffer circuit in FIG. 1 .
  • the initial drive signal will charge the second capacitor C2 after passing through the second resistor R2.
  • the initial drive signal is adjusted by the charging and discharging time of the first capacitor C2 to obtain a first drive signal.
  • the first drive signal is subjected to a logic operation through the first logic gate adjustment circuit to obtain a gate drive signal.
  • the gate drive signal can be directly output to the power device 103 to be tested, or output to the power device 103 to be tested via the driver 104.
  • the first logic gate adjustment circuit can specifically adjust the level flipping speed of the first driving signal through a logic operation, wherein the logic operation (such as negation or pass operation) in the first logic gate adjustment circuit needs to be determined according to its specific circuit structure.
  • the buffer circuit includes the second RC buffer circuit, it can also include a first logic gate adjustment circuit. Therefore, for some scenarios that require the turn-off time of the power device to be driven, the first logic gate adjustment circuit in the buffer circuit can further adjust the drive signal to meet the application requirements. In practical applications, the first logic gate adjustment circuit can be implemented in multiple ways.
  • the aforementioned second resistor may further include an adjustable resistor.
  • the resistance of the adjustable resistor may be directly adjusted according to application requirements without the need for cumbersome resistor replacement operations.
  • the first logic gate adjustment circuit may include an AND gate 1011.
  • the AND gate 1011 may be connected to an RC buffer circuit (e.g., the first RC buffer circuit shown in FIG2 or the second RC buffer circuit shown in FIG3 ), wherein the driving signal after delay adjustment by the RC buffer circuit is output to the driver by the AND gate 1011.
  • the RC buffer circuit includes a resistor R and a capacitor C, as shown in FIG4 , and the AND gate 1011 may be connected to one end of the resistor R.
  • the resistor R may be a fixed resistor or an adjustable circuit, and in this embodiment, an adjustable resistor is preferably used.
  • the RC buffer circuit may further include a fixed resistor 1012, which may be connected to a second RC buffer circuit, wherein the initial drive signal is output to the second RC buffer circuit via the fixed resistor 1012, so as to adjust the load capacity of the drive signal by adding the fixed resistor 1012.
  • the first logic gate adjustment circuit is an AND gate circuit 1011, the input end of the AND gate circuit 1011 is connected to the second RC buffer circuit for receiving the first drive signal; the output end of the AND gate circuit 1011 is connected to the power device to be tested 103, for performing an AND operation on the first drive signal output by the second RC buffer circuit to obtain a gate drive signal.
  • the initial driving signal can be connected to one end of the fixed resistor 1012, the other end of the fixed resistor 1012 can be connected to one end of the resistor R, the other end of the resistor R is respectively connected to the capacitor C and the AND gate 1011, and the output end of the AND gate 1011 is connected to the driver 104.
  • the initial driving signal can be connected to one end of the fixed resistor 1012, the other end of the fixed resistor 1012 can be connected to one end of the resistor R, the other end of the resistor R is respectively connected to the capacitor C and the AND gate 1011, and the output end of the AND gate 1011 is connected to the driver 104.
  • FIG5 is a block diagram showing a power device driving circuit 500 according to another embodiment of the present application. It can be understood that FIG5 is another specific implementation of the power device driving circuit 100 in FIG1. In addition, FIG5 can also be understood as a further supplement to the function of the power device driving circuit 300 in FIG3. Therefore, the aforementioned related detailed descriptions in combination with FIG1 and FIG3 are also used in FIG5.
  • the initial driving signal in FIG5 can be generated by a signal generator or a pulse generating circuit.
  • the driver 104 can be retained or deleted according to application requirements.
  • the resistor in the buffer circuit 101 can be a fixed resistor or an adjustable variable resistor, etc.
  • the power device driving circuit 500 may include a buffer circuit 101 and a signal source 102.
  • the buffer circuit may include a first NAND gate circuit 1013, a third RC buffer circuit, and a second NAND gate circuit 1014, and may also include a diode 1015.
  • the input end of the first NAND gate circuit 1013 is connected to the initial driving signal, and the output end thereof is connected to the input end of the third RC buffer circuit.
  • the input end of the second NAND gate 1014 circuit is connected to the output end of the third RC buffer circuit, and the output end thereof is connected to the driver 102.
  • the anode of the diode 1015 is connected to the output end of the first NAND gate 1013, and the cathode thereof is connected to the input end of the second NAND gate 1014. Therefore, for some scenarios where there are requirements for the turn-off time of the power device to be driven, the driving signal can be further adjusted by the logic gate adjustment circuit in the buffer circuit to meet the application requirements.
  • the RC buffer circuit (for example, the first RC buffer circuit shown in FIG. 2 or the second RC buffer circuit shown in FIG. 3 or the third RC buffer circuit shown in FIG. 5) includes a third resistor R3 and a third capacitor C3.
  • the input end of the first NAND gate can be connected to the initial driving signal, and the output end thereof can be connected to one end of the third resistor R3 and the anode of the diode 1015.
  • the cathode of the diode 1015 can be connected to the other end of the third resistor R3, one end of the third capacitor C3, and the input end of the second NAND gate circuit 1014.
  • the output end of the second NAND gate circuit 1014 is connected to the input end of the driver 104, and the output end of the driver 104 is connected to the gate of the power device 103 to be driven.
  • the source of the power device 103 to be driven and the other end of the third capacitor C3 are grounded.
  • the initial signal may include high and low levels whose duty cycle can be set.
  • a high-level driving signal is obtained by inverting the first NAND gate circuit 1013.
  • the diode 1015 is turned on.
  • the third capacitor C3 is charged via the diode 1015, and the voltage of the third capacitor C is rapidly increased from a low level to a high level, and then a low-level signal is obtained by inverting the second NAND gate circuit 1014.
  • the driver 104 of the power device to be tested outputs a low level, and the power device to be tested is turned off.
  • a low-level signal is obtained by inverting the first NAND gate circuit 1013, and at this time, the diode 1015 is reversely cut off, and the first NAND gate circuit 1013 discharges the third capacitor C3 through the third resistor R3.
  • the voltage of the third capacitor C3 drops from a high level to a low level, and the second NAND gate circuit 1014 reverses the low level signal to a high level signal.
  • the driver 104 of the power device to be tested outputs a high level, and the power device to be tested is turned on.
  • the resistance adjustment process of the third resistor R3 can refer to the relevant description in the previous text, and will not be repeated here. It can be seen that in the adjustment process of the entire drive signal, the diode can ensure that the drive signal only adjusts the delay of the power device opening moment through the RC buffer, and does not change the turn-off moment, so that the adjusted drive signal can better meet the actual needs.
  • the third resistor R3 may be an adjustable resistor.
  • the resistance of the adjustable resistor may be directly adjusted according to application requirements without the need for cumbersome resistor replacement operations.
  • the present application adjusts the driving signal through the buffer circuit in the power device driving circuit to drive the power device to turn on in a timely manner.
  • the entire circuit structure is streamlined and the devices used are low-cost, which can effectively reduce the implementation cost of the entire circuit technology.
  • the semiconductor device test circuit 600 may include a primary circuit and a secondary circuit, wherein the primary circuit includes a primary winding and a primary power device to be tested connected in series, the two ends of the primary circuit are used to connect a test power supply to form a loop, the secondary circuit includes a secondary winding and a secondary transistor to be tested connected in series, the primary winding and the secondary winding form a flyback transformer, the primary circuit and the secondary circuit are connected in parallel and grounded, wherein the primary circuit also includes a first power device drive circuit connected to the primary power device to be tested, including a power device drive circuit as shown in FIGS.
  • the buffer circuit in the power device drive circuit is used to process the initial drive signal according to the test condition of the primary power device to be tested, and output a first gate drive signal for the primary power device to be tested, so as to control the primary power device to be tested to turn on when the drain-source voltage of the primary power device to be tested oscillates to the bottom of the valley based on the first gate drive signal.
  • the semiconductor device test circuit 600 may include the power device drive circuit shown in FIG5 .
  • the power device drive circuit in the semiconductor device test circuit 600 includes a first NAND gate Ubu-n, a diode Dbu-n, a first resistor Rbu-n, a capacitor Cbu-n, a second NAND gate Ubu-2n and a driver.
  • FIG6 also shows a primary power device QL-n to be tested, a secondary transistor DH-n to be tested, and a flyback transformer Tn formed by the primary winding and the secondary winding.
  • the secondary circuit of the semiconductor device test circuit is connected to the primary circuit, which is equivalent to a double-pulse circuit of energy storage + energy feedback, and various switch tests such as stress and current can be realized, which can effectively reduce the power consumption of the test circuit.
  • the primary circuit which is equivalent to a double-pulse circuit of energy storage + energy feedback
  • various switch tests such as stress and current can be realized, which can effectively reduce the power consumption of the test circuit.
  • the problem of large differences in drain-source resonant voltage and switching loss when the device under test is turned on due to differences in transformer leakage inductance and power device parasitic capacitance can be solved, and the working conditions of the actual flyback adapter can be simulated to the greatest extent.
  • FIG6 also shows an RCD absorption circuit and an AC absorption circuit (i.e., an active clamp absorption circuit).
  • the RCD absorption circuit can be used to reduce the turn-off voltage spike caused by the leakage inductance of the flyback transformer, and the switching characteristics, reliability and other indicators of the primary side power device to be tested in the RCD absorption circuit can be evaluated and tested.
  • the AC absorption circuit can be used to reduce the turn-off voltage spike caused by the leakage inductance of the flyback transformer, and the switching characteristics, reliability and other indicators of the primary side power device to be tested in the AC absorption circuit can be evaluated and tested.
  • the secondary side transistor to be tested may also include a secondary side power device to be tested (not shown in FIG. 6 ).
  • the secondary side circuit also includes a second power device driving circuit connected to the secondary side power device to be tested, including the power device driving circuit shown in FIG. 1 to FIG. 5 .
  • the buffer circuit in the power device driving circuit is used to process the initial drive signal according to the test condition of the secondary side power device to be tested, and output a second gate drive signal for the secondary side power device to be tested, so as to control the secondary side power device to be tested to be turned on when the drain-source voltage of the secondary side power device to be tested oscillates to the bottom of the valley based on the second gate drive signal.
  • the switching characteristics of the secondary side power device to be tested for synchronous rectification can be evaluated.
  • the adjusted drive signal can be input to the primary side power device to be tested and the secondary side power device to be tested respectively through the power device driving circuit, so that the primary side power device to be tested and the secondary side power device to be tested can be periodically turned on and off according to the drive signal.
  • the drive signals of the primary side power device to be tested and the secondary side power device to be tested can be complementary and a certain dead time can be added.
  • FIG7 is a structural diagram of a semiconductor device test system 700 according to an embodiment of the present application.
  • the semiconductor device test system 700 in this embodiment may include multiple primary circuits and secondary circuits, wherein each primary circuit includes a primary winding and a primary power device to be tested in series, and the two ends of each primary circuit are used to connect the test power supply to form a loop, each secondary circuit includes a secondary winding and a secondary transistor to be tested in series, each primary winding and each secondary winding form a flyback transformer, and each primary circuit and each secondary circuit are connected in parallel and grounded.
  • Each primary circuit also includes a first power device drive circuit connected to the primary power device to be tested; and/or the secondary transistor to be tested includes a secondary power device to be tested, and each secondary circuit also includes a second power device drive circuit connected to the secondary power device to be tested.
  • the first power device driving circuit and/or the second power device driving circuit includes a power device driving circuit as shown in Figures 1 to 5, and multiple power device driving circuits generate the same initial driving signal based on a signal source, wherein each power device driving circuit is used to process the initial driving signal according to the test conditions of its corresponding primary side power device to be tested or the secondary side power device to be tested to obtain a gate driving signal, and output a corresponding gate driving signal to its corresponding primary side power device to be tested or the secondary side power device to be tested, so as to control its corresponding primary side power device to be tested to turn on when the drain-source voltage of the primary side power device to be tested oscillates to the bottom of the valley based on the corresponding gate driving signal, or control its corresponding secondary side power device to be tested to turn on when the drain-source voltage of the secondary side power device to be tested oscillates to the bottom of the valley.
  • the input of all semiconductor device test circuits shares the test power supply and the devices under test share the initial drive signal to form a batch test system.
  • the drive signal is introduced into the power device drive circuit to avoid the problem of inconsistent drain-source voltage when the device under test is turned on due to deviations in transformer leakage inductance and parasitic parameters during the actual system switching process, thereby ensuring the consistency and accuracy of batch testing of the devices under test based on flyback conditions.
  • a fuse is connected in series between the positive pole of the test power supply and the primary circuit of each semiconductor device test circuit, thereby effectively improving the independence of each semiconductor device test circuit and ensuring that when the primary switching element to be tested of a semiconductor device test circuit fails, the aging test of other semiconductor device test circuits is not affected.
  • the test power supply is a DC bus
  • the signal source is used to input an initial drive signal to the power device driving circuit in each semiconductor device test circuit.
  • the first semiconductor device test circuit includes a fuse Fin-1, a capacitor Cin-1, a flyback transformer T1, a diode DH-1, a power device to be tested QL-1, and a power device driving circuit 1 (including a first NAND gate Ubu-1, a diode Dbu-1, a first resistor Rbu-1, a capacitor Cbu-1, a second NAND gate Ubu-21, and a driver), and the second semiconductor device test circuit includes a fuse Fin-2, a capacitor Cin-2, a flyback transformer T2, a diode DH-2, a power device to be tested QL-2, and a power device driving circuit 2 (including a first NAND gate Ubu-2, a diode Dbu-2, a first resistor Rbu-1, a capacitor Cbu-1, a second NAND gate
  • the nth semiconductor device test circuit includes fuse Fin-n, capacitor Cin-n, flyback transformer Tn, diode DH-n, power device to be tested QL-n and power device drive circuit n (including first NAND gate Ubu-n, diode Dbu-n, first resistor Rbu-n, capacitor Cbu-n, second NAND gate Ubu-2n and driver), and the two ends of the primary circuit of each semiconductor device test circuit are respectively connected to the DC bus to form a loop, and at the same time, the power device drive circuit of each semiconductor device test circuit is connected to the signal source. It should be understood that due to the setting of the fuse, each semiconductor device test circuit is independent of each other.
  • test temperature, test voltage, test current, test frequency, test duty cycle, and number of test devices involved in the test system can all be adjusted according to the acceleration conditions to meet the multi-dimensional accelerated testing needs.

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Abstract

本申请公开了一种功率器件驱动电路、半导体器件测试电路及系统。其中功率器件驱动电路包括：信号源，用于产生初始驱动信号；以及缓冲电路，电连接于所述信号源与待测功率器件的栅极之间，用于接收初始驱动信号，且基于待测功率器件的测试工况，对初始驱动信号进行延时处理并输出经延时处理的栅极驱动信号，其中，栅极驱动信号用于控制待测功率器件在待测功率器件漏源极电压振荡到谷底时开通。通过本申请的方案，可对待测功率器件的驱动信号进行延时调整，使得待测功率器件能够在该待测功率器件漏源极电压振荡到谷底时开通，以满足对功率器件的应用需求。

Description

功率器件驱动电路、半导体器件测试电路及系统 技术领域
本申请一般地涉及半导体器件技术领域。更具体地，本申请涉及一种功率器件驱动电路、一种半导体器件测试电路和半导体器件测试系统。
 背景技术
近年来，采用氮化镓功率晶体管等功率器件的手机快充适配器市场需求越来越大，特别是基于反激电路的氮化镓适配器更是得到广泛应用。为了保证产品的可靠性，通常需要对适配器所采用的相应功率器件进行老化等性能测试。相关技术中采用模拟反激电路工况的方式来对功率器件进行测试。然而在实际应用时，由于测试电路中非线性器件（例如变压器漏感和开关管寄生电容等）存在偏差而导致被测功率器件没在其漏源极电压谐振到谷底时开通，使得模拟电路工况脱离被测功率器件的实际工况，从而导致测试结果不精确。
 技术问题
为了至少解决上述背景技术部分所描述的技术问题，本申请提出了一种功率器件驱动电路，可通过对待功率器件的初始驱动信号进行延时调整，使得待测动功率器件能够在待测功率器件的漏源极电压振荡到谷底时开通，以满足对功率器件的应用需求。
 技术解决方案
为了实现上述目的及其他相关目的，本申请提供一种功率器件驱动电路，包括：信号源，用于产生初始驱动信号；以及缓冲电路，电连接于所述信号源与待测功率器件的栅极之间，用于接收所述初始驱动信号，基于所述待测功率器件的测试工况，对所述初始驱动信号进行延时处理并输出经延时处理的栅极驱动信号，其中，所述栅极驱动信号用于控制所述待测功率器件在所述待测功率器件的漏源极电压振荡到谷底时开通。
本申请还提供一种半导体器件测试电路，包括原边电路和副边电路，其中所述原边电路包括串联的原边绕组和原边待测功率器件，所述原边电路的两端用于连接测试电源以形成回路，所述副边电路包括串联的副边绕组和副边待测晶体管，所述原边绕组和所述副边绕组形成反激变压器，所述原边电路和所述副边电路并联且接地，其中所述原边电路还包括：第一功率器件驱动电路，连接至所述原边待测功率器件，所述第一功率器件驱动电路包括：信号源，用于产生初始驱动信号；以及缓冲电路，电连接于所述信号源与所述原边待测功率器件的栅极之间，用于根据所述原边待测功率器件的测试工况对所述初始驱动信号进行处理，并输出针对所述原边待测功率器件的第一栅极驱动信号，以基于所述第一栅极驱动信号控制所述原边待测功率器件在所述原边待测功率器件的漏源极电压振荡到谷底时开通。
本申请还提供一种半导体器件测试系统，包括：多个原边电路和副边电路，其中每个所述原边电路包括串联的原边绕组和原边待测功率器件，每个所述原边电路的两端用于连接测试电源以形成回路，每个所述副边电路包括串联的副边绕组和副边待测晶体管，每个所述原边绕组和每个所述副边绕组形成反激变压器，每个所述原边电路和每个所述副边电路并联且接地；其中每个所述原边电路还包括第一功率器件驱动电路，连接至所述原边待测功率器件；和/或所述副边待测晶体管包括副边待测功率器件，每个所述副边电路还包括连接至所述副边待测功率器件的第二功率器件驱动电路；其中所述第一功率器件驱动电路和/或所述第二功率器件驱动电路包括功率器件驱动电路，所述功率器件驱动电路包括：信号源，用于产生初始驱动信号；以及缓冲电路，电连接于所述信号源与待测功率器件的栅极之间，用于接收所述初始驱动信号，基于所述待测功率器件的测试工况，对所述初始驱动信号进行延时处理并输出经延时处理的栅极驱动信号，其中，所述栅极驱动信号用于控制所述待测功率器件在所述待测功率器件的漏源极电压振荡到谷底时开通；多个所述功率器件驱动电路基于其信号源产生同一初始驱动信号，其中每个所述功率器件驱动电路用于根据其对应的原边待测功率器件或者副边待测功率器件的测试工况对所述初始驱动信号进行处理以得到栅极驱动信号，并向其对应的原边待测功率器件或者副边待测功率器件输出对应的栅极驱动信号，以基于对应的栅极驱动信号控制其对应的原边待测功率器件在所述原边待测功率器件的漏源极电压振荡到谷底时开通，或者控制其对应的副边待测功率器件在所述副边待测功率器件的漏源极电压振荡到谷底时开通。
 有益效果
与现有技术相比，本申请所述的发光器件、背板组件及显示面板至少具备如下有益效果：
利用本申请所提供的方案，基于功率器件驱动电路中的缓冲电路对待测功率器件的初始驱动信号进行延时处理， 以使待测动功率器件能够在该待测功率器件的漏源极电压振荡到谷底时开通，从而满足功率器件的应用需求。在一些实施例中，可将该功率器件驱动电路应用于半导体器件测试电路中，以确保对功率器件的模拟电路工况符合实际工况，从而提高测试精准度。另外，在又一些实施例中，还可以将该功率器件驱动电路应用于半导体器件测试系统中，以克服批量化测试过程中被测功率器件测试条件以及功耗不一致的问题，从而有效确保半导体器件测试系统中的每个被测功率器件工况一致。
 附图说明
图1是示出根据本申请第一个实施例的功率器件驱动电路的结构图；
图2是示出根据本申请第二个实施例的功率器件驱动电路的结构图；
图3是示出根据本申请第三个实施例的功率器件驱动电路的结构图；
图4是示出根据本申请第四个实施例的功率器件驱动电路的结构图；
图5是示出根据本申请第五个实施例的功率器件驱动电路的结构图；
图6是示出根据本申请实施例的半导体器件测试电路的结构图；以及
图7是示出根据本申请实施例的半导体器件测试系统的结构图。
 本发明的最佳实施方式
在此处键入本发明的最佳实施方式描述段落。
本发明的实施方式
以下由特定的具体实施例说明本申请的实施方式，熟悉此技术的人士可由本说明书所揭露的内容轻易地了解本申请的其他优点及功效。本申请还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本申请的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
须知，本申请实施例中所提供的图示仅以示意方式说明本申请的基本构想，虽图示中仅显示与本申请中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的形态、数量及比例可随意的改变，且其组件布局形态也可能更为复杂。说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本申请可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本申请所能产生的功效及所能达成的目的下，均应仍落在本申请所揭示的技术内容得能涵盖的范围内。
发明人经研究发现，针对氮化镓功率晶体管等功率器件，通常会采用驱动信号直接触发功率器件的开通或关断。然而，随着氮化镓功率晶体管等功率器件的广泛应用，需要功率器件在相应的工况下工作。特别是，针对基于反激电路和能量回馈的批量测试电路系统，系统中的待测功率器件需要工作在反激电路工况下，此时待测功率器件需要在其漏源极电压满足最低谐振电压（也即谷底电压）时开通。然而在实际应用中，由于反激电路中一些非线性器件存在偏差（例如变压器漏感偏差等），使得待测功率器件的源漏极电压谐振周期可能不同，从而造成待测功率器件开通条件（例如待测功率器件漏源极电压未谐振至谷底即开通）不满足应用需求。为此，发明人还发现可以通过调整功率器件的驱动信号，以使驱动信号能够适时触发功率器件开通，以满足功率器件的应用需求。
下面结合附图来详细描述本申请的具体实施方式。
图1是示出根据本申请一个实施例的功率器件驱动电路100的结构图。如图1所述，功率器件驱动电路100可以包括缓冲电路101和信号源102。同时，为了能够更清楚说明功率器件驱动电路100的工作原理，在图1中还示出待测功率器件103，缓冲电路101电连接于信号源102和待测功率器件103之间。
其中，前述的信号源可以用于产生初始驱动信号。在一些实施例中，该信号源具体可以包括信号发生器或者脉冲发生电路等。具体地，可以通过信号发生器或者脉冲发生电路来产生初始驱动信号，且在一些实施场景下，该初始驱动信号可以包括占空比可设置的高低电平。需要说明的是，这里对初始驱动信号的细节性描述仅是示例性说明。
前述的缓冲电路101可以接收初始驱动信号，并且可以基于待测功率器件的测试工况，对初始驱动信号进行延时处理并输出经延时处理的栅极驱动信号。其中，该栅极驱动信号可以用于控制待测功率器件在待测功率器件的漏源极电压振荡到谷底时开通。由此，可以基于待测功率器件的测试工况通过缓冲电路适应性地对初始驱动信号进行延时处理，调整待测功率器件的开通时刻点，以使调整后的驱动信号能够适时触发功率器件开通，以满足功率器件的应用需求。需要说明的是，前述的功率器件可以包括氮化镓功率器件、碳化硅功率器件或者其他功率器件，这里对功率器件的具体类型不作限定。
在一些实施例中，前述的功率器件驱动电路还可以包括驱动器。该驱动器可以接收从缓冲电路101输出的栅极驱动信号，并将该栅极驱动信号输出至待测功率器件。
前述的缓冲电路101在具体应用中可以有多种实现形式，以下结合图2至图5进行进一步说明。
图2是示出根据本申请另一个实施例的功率器件驱动电路200的结构图。可以理解的是，图2是图1中功率器件驱动电路100的一种具体实现。因此，前述结合图1中的相关细节性描述同样也使用于图2。例如，图2中的初始驱动信号可以通过信号发生器或脉冲发生电路来产生。此外，在功率驱动电路200中同时示出了驱动器104，该驱动器104可以根据实际应用需求进行删减或保留。
具体参见图2，功率器件驱动电路200可以包括缓冲电路101和信号源102。其中，前述的缓冲电路101可以包括第一RC缓冲电路，该第一RC缓冲电路可以利用其中的电容的充放电过程对前述的初始驱动信号进行延时调节。具体地，在一些实施例中，该第一RC缓冲电路可以包括第一电阻器R1和第一电容C1。其中该第一电容C1的一端连接至第一电阻器R1，所述第一电容C1的另一端接地。初始驱动信号经过第一电阻器R1之后会给第一电容C1充电。对于第一电容C1后续的电路来说，初始驱动信号经第一电容C1的充放电时长的调节后得到栅极驱动信号。该栅极驱动信号可以直接输出待测功率器件103，或者经由驱动器104输出至待测功率器件103。
进一步地，在一些实施例中，前述的第一电阻器R1可以包括固定电阻器，具体可以根据待驱动器件的应用需求来确定所需的固定电阻器，通过调换不同阻值的固定电阻器来适应性调整功率器件驱动电路200，使其满足应用需求。
又例如，在另一些实施例中，前述的第一电阻器R1还可以包括可调电阻器。在该场景下，可以根据应用需求直接调整可调电阻器的电阻，无需繁琐的进行电阻器的更换操作。例如，可以基于可调电阻器的阻值调整以调控待驱动功率器件开通时的漏源极电压。在实际应用中，可配合示波器来进行阻值的调整。具体地，在调整可调电阻器的阻值过程中，可以通过示波器来检测待驱动功率器件的开通情况，直至在通过示波器检测到待驱动功率器件在其漏源极电压在谷底时开通，此时停止阻值的调整。需要说明的是，这里对可调电阻器的阻值调整过程的描述仅是示例性说明，本申请的方案并不受此限制。
图3是示出根据本申请再一个实施例的功率器件驱动电路300的结构图。可以理解的是，图3是图1中功率器件驱动电路100的另一种具体实现。此外，图3还可以理解为是对图2中功率器件驱动电路200功能的进一步补充。因此，前述结合图1和图2中的相关细节性描述同样也使用于图3。例如，图3中的初始驱动信号可以通过信号发生器或脉冲发生电路来产生。此外，在功率驱动电路300中同时示出了驱动器104，该驱动器104可以根据实际应用需求进行删减或保留。
具体参加图3，功率器件驱动电路300可以包括缓冲电路101和信号源102。其中，该缓冲电路包括第二RC缓冲电路和第一逻辑门调整电路。该第二RC缓冲电路包括第二电阻器R2和第二电容C2，第二电容C2的一端连接第二电阻器R2，第二电容C2的另一端接地，可以理解的是，该第二RC缓冲电路可以具备与图1中第一RC缓冲电路相同的电路结构。初始驱动信号经过第二电阻器R2之后会给第二电容C2充电。对于第一电容C2后续的电路来说，初始驱动信号经第一电容C2的充放电时长的调节后得到第一驱动信号。该第一驱动信号经过第一逻辑门调整电路进行逻辑运算得到栅极驱动信号。该栅极驱动信号可以直接输出待测功率器件103，或者经由驱动器104输出至待测功率器件103。
在一些实施例中，该第一逻辑门调整电路具体可以通过逻辑运算来调整第一驱动信号的电平翻转速度。其中第一逻辑门调整电路中逻辑运算（例如取反或取通等运算）需根据其具体电路结构确定。
在缓冲电路包括第二RC缓冲电路的基础上，还可以包括第一逻辑门调整电路。由此，对于一些对待驱动功率器件的关断时间有要求的场景，可以通过缓冲电路中的第一逻辑门调整电路对驱动信号的进一步调整来满足应用需求。在实际应用中，第一逻辑门调整电路可以有多种实现方式。
在另一些实施例中，前述的第二电阻器还可以包括可调电阻器。在该场景下，可以根据应用需求直接调整可调电阻器的电阻，无需繁琐的进行电阻器的更换操作。
例如，在图4中，该第一逻辑门调整电路可以包括与门1011。该与门1011可以连接至RC缓冲电路（例如图2所示的第一RC缓冲电路或图3所示的第二RC缓冲电路），其中经该RC缓冲电路延时调节后的驱动信号由与门1011输出至驱动器。在一些实施例中， RC缓冲电路包括电阻R和电容C，如图4所示，此时与门1011可以连接至电阻R的一端。其中，该电阻R可以为固定电阻或可调电路，本实施例中，优选地采用可调电阻。
进一步地，如图4所示，在一些实施例中，RC缓冲电路还可以包括固定电阻1012，该固定电阻1012可连接于第二RC缓冲电路，其中初始驱动信号经由固定电阻1012输出至第二RC缓冲电路，以通过增设固定电阻1012来调整驱动信号的负载能力。
如图4所示，在一些实施例中，第一逻辑门调整电路为与门电路1011，该与门电路1011的输入端与第二RC缓冲电路连接，用于接收第一驱动信号；该与门电路1011的输出端与待测功率器件103连接，用于将第二RC缓冲电路输出的第一驱动信号进行与运算得到栅极驱动信号。
再如图4所示，在一些实施例中，初始驱动信号可以连接至固定电阻1012的一端，固定电阻1012的另一端可以连接至电阻R的一端，电阻R的另一端分别连接至电容C和与门1011，与门1011输出端连接至驱动器104。由此，不仅能确保待测功率器件能够适时开通，还能满足待测功率器件的关断时间需求。
图5是示出根据本申请又一个实施例的功率器件驱动电路500的结构图。可以理解的是，图5是图1中功率器件驱动电路100的又一种具体实现。此外，图5还可以理解为是对图3中功率器件驱动电路300功能的进一步补充。因此，前述结合图1和图3中的相关细节性描述同样也使用于图5。例如，图5中的初始驱动信号可以通过信号发生器或脉冲发生电路来产生。而驱动器104可以根据应用需求保留或删减。还例如，缓冲电路101中的电阻器可以是固定电阻器或可调式变阻器等。
具体参加图5，功率器件驱动电路500可以包括缓冲电路101和信号源102。其中，缓冲电路可以包括第一与非门电路1013、第三RC缓冲电路和第二与非门电路1014还可以包括二极管1015。其中，该第一与非门电路1013的输入端连接至初始驱动信号，其输出端连接至第三RC缓冲电路的输入端。第二与非门1014电路的输入端连接至第三RC缓冲电路的输出端，且其输出端连接至驱动器102。而二极管1015的阳极连接至第一与非门1013的输出端，其阴极连接至第二与非门1014的输入端。由此，对于一些对待驱动功率器件的关断时间有要求的场景，可以通过缓冲电路中的逻辑门调整电路对驱动信号的进一步调整来满足应用需求。
在一些实施例中，RC缓冲电路（例如图2所示的第一RC缓冲电路或图3所示的第二RC缓冲电路或图5所示的第三RC缓冲电路包括第三电阻R3和第三电容C3。此时功率器件驱动电路中各个器件间的连接关系，如图5所示，第一与非门的输入端可以连接至初始驱动信号，其输出端可以连接至第三电阻R3的一端和二极管1015的阳极。二极管1015的阴极可以连接至第三电阻R3的另一端、第三电容C3的一端和第二与非门电路1014的输入端。第二与非门电路1014的输出端连接至驱动器104的输入端，驱动器104的输出端连接至待驱动功率器件103的栅极。待驱动功率器件103的源极和第三电容C3的另一端共地。需要说明的是，这里对功率器件驱动电路中器件的连接关系的描述仅是示例性说明。
进一步地，结合图5所示的电路结构对功率器件驱动电路的工作原理进行说明。在该场景下，初始信号可以包括占空比可设定的高低电平。当输入低电平信号时，经由第一与非门电路1013反转得到高电平驱动信号。在该高电平驱动信号作用下，二极管1015开通。此时经由二极管1015对第三电容C3进行充电，第三电容C的电压迅速从低电平升至高电平后，再经由第二与非门电路1014反转后得到低电平信号，此时待测功率器件的驱动器104输出低电平，待测功率器件关断。当输入为高电平信号时，经第一与非门电路1013反转后得到低电平信号，此时二极管1015反向截止，第一与非门电路1013通过第三电阻R3对第三电容C3进行放电。经过一定放电时间后第三电容C3的电压从高电平降至低电平，第二与非门电路1014将低电平信号反转为高电平信号，此时待测功率器件的驱动器104输出高电平，待测功率器件开通。另外，功率器件驱动电路中的第三电阻R3的阻值经预先调整后，在使用时无需再调整，即可确保待驱动功率器件在其漏源极电压谐振到谷底电压时开通。其中，第三电阻R3的阻值调整过程可参考前文相关描述，这里不再进行赘述。可以看出，在整个驱动信号的调整过程中，二极管能够确保驱动信号只通过RC缓冲调整功率器件开通时刻的延时，不改变关断时刻，使得经调整后的驱动信号更满足实际需求。
在另一些实施例中，前述的第三电阻器R3可以为可调电阻器。在该场景下，可以根据应用需求直接调整可调电阻器的电阻，无需繁琐的进行电阻器的更换操作。
可以看出，本申请通过功率器件驱动电路中的缓冲电路对驱动信号进行调整以驱动功率器件适时开通，整个电路结构精简且使用的器件成本低廉，可有效降低整个电路技术实现成本。
以下结合图6和图7对上述功率器件驱动电路的应用场景进行说明。
图6是示出根据本申请实施例的半导体器件测试电路500的结构图。该半导体器件测试电路600可以包括原边电路和副边电路，其中原边电路包括串联的原边绕组和原边待测功率器件，原边电路的两端用于连接测试电源以形成回路，副边电路包括串联的副边绕组和副边待测晶体管，原边绕组和副边绕组形成反激变压器，原边电路和所述副边电路并联且接地，其中原边电路还包括第一功率器件驱动电路，连接至所述原边待测功率器件，包括如图1至图5中所示的功率器件驱动电路，其中功率器件驱动电路中的缓冲电路用于根据原边待测功率器件的测试工况对初始驱动信号进行处理，并输出针对原边待测功率器件的第一栅极驱动信号，以基于第一栅极驱动信号控制原边待测功率器件在原边待测功率器件在其漏源极电压振荡到谷底时开通。
具体地，如图6所示，该半导体器件测试电路600可以包括图5所示的功率器件驱动电路。其中，半导体器件测试电路600中的功率器件驱动电路包括第一与非门Ubu-n、二极管Dbu-n、第一电阻器Rbu-n、电容Cbu-n、第二与非门Ubu-2n以及驱动器。另外，图6还示出了待测原边待测功率器件QL-n、副边待测晶体管DH-n以及原边绕组和副边绕组形成反激变压Tn。
通过结合反激电路和能量回馈，将半导体器件测试电路的副边电路接至原边电路，等效于储能+能馈的双脉冲电路，实现应力和电流等多种开关测试，可以有效降低测试电路功耗。同时，通过增设功率器件驱动电路对驱动信号进行调整， 可解决因变压器漏感和功率器件寄生电容等差异导致被测器件开通时的漏源极谐振电压和开关损耗存在较大差异的问题，能够最大程度模拟实际反激适配器的工况。
进一步地，图6还展示了RCD吸收电路和AC吸收电路（也即有源箝位吸收电路）。由此，可以利用RCD吸收电路减少对于反激变压器漏感导致的关断电压尖峰，以及能够对原边待测功率器件在RCD吸收电路中的开关特性、可靠性等指标进行评估测试。另外，利用AC吸收电路可以减少对于反激变压器漏感导致的关断电压尖峰，以及同时能够对原边待测功率器件在AC吸收电路中的开关特性、可靠性等指标进行评估测试。
进一步地，在一些实施例中，副边待测晶体管还可以包括副边待测功率器件（图6中未示出）。副边电路还包括第二功率器件驱动电路，连接至副边待测功率器件，包括图1至图5中所示的功率器件驱动电路。其中功率器件驱动电路中的缓冲电路用于根据副边待测功率器件的测试工况对初始驱动信号进行处理，并输出针对副边待测功率器件的第二栅极驱动信号，以基于第二栅极驱动信号控制副边待测功率器件在副边待测功率器件的漏源极电压振荡到谷底时开通。由此可以评估测试副边待测功率器件用于同步整流的开关特性。在实际测试时，可以通过功率器件驱动电路分别向原边待测功率器件和副边待测功率器件输入经调整后的驱动信号，使得原边待测功率器件和副边待测功率器件都能够根据驱动信号周期性的开通和关断。例如：原边待测功率器件和副边待测功率器件的驱动信号可以是互补并加入一定的死区时间。
图7是示出根据本申请实施例的半导体器件测试系统700的结构图。不同于传统的反激适配器老化测试系统存在负载设备多、老化功耗大、批量测试系统复杂庞大以及不利于器件大批量测试筛选等缺点和问题。本实施例中的半导体器件测试系统700可以包括多个原边电路和副边电路，其中每个原边电路包括串联的原边绕组和原边待测功率器件，每个原边电路的两端用于连接测试电源以形成回路，每个副边电路包括串联的副边绕组和副边待测晶体管，每个原边绕组和每个副边绕组形成反激变压器，每个原边电路和每个副边电路并联且接地。其中每个原边电路还包括第一功率器件驱动电路，连接至原边待测功率器件；和/或副边待测晶体管包括副边待测功率器件，每个副边电路还包括连接至副边待测功率器件的第二功率器件驱动电路。
在一些实施例中，第一功率器件驱动电路和/或第二功率器件驱动电路包括如图1至图5中所示的功率器件驱动电路，多个功率器件驱动电路基于一个信号源产生同一初始驱动信号，其中每个功率器件驱动电路用于根据其对应的原边待测功率器件或者副边待测功率器件的测试工况对初始驱动信号进行处理以得到栅极驱动信号，并向其对应的原边待测功率器件或者副边待测功率器件输出对应的栅极驱动信号，以基于对应的栅极驱动信号控制其对应的原边待测功率器件在原边待测功率器件的漏源极电压振荡到谷底时开通，或者控制其对应的副边待测功率器件在副边待测功率器件的漏源极电压振荡到谷底时开通。
由此，所有半导体器件测试电路的输入共用测试电源、待测器件共用初始驱动信号以组成批量测试系统。其中驱动信号引入功率器件驱动电路，避免实际系统开关过程中变压器漏感和寄生参数存在偏差而导致被测器件开通时漏源电压不一致的问题，从而确保实现待测器件基于反激工况批量测试的一致性和准确性。
在一些实施方式中，如图6所示，在测试电源的正极和每个半导体器件测试电路的原边电路之间还串联有熔断器，从而能够有效提高每个半导体器件测试电路的独立性，在某个半导体器件测试电路的原边待测开关元件失效时不影响其他半导体器件测试电路的老化测试。
在一些实施方式中，如图6所示，测试电源为直流母线，信号源用于向每一个半导体器件测试电路中的功率器件驱动电路输入初始驱动信号。在实际连接时，第一个半导体器件测试电路中包括熔断器Fin-1、电容Cin-1、反激变压器T1、二极管DH-1、待测功率器件QL-1和功率器件驱动电路1（包括第一与非门Ubu-1、二极管Dbu-1、第一电阻器Rbu-1、电容Cbu-1、第二与非门Ubu-21以及驱动器），第二个半导体器件测试电路中包括熔断器Fin-2、电容Cin-2、反激变压器T2、二极管DH-2、待测功率器件QL-2和功率器件驱动电路2（包括第一与非门Ubu-2、二极管Dbu-2、第一电阻器Rbu-2、电容Cbu-2、第二与非门Ubu-22以及驱动器）······第n个半导体器件测试电路中包括熔断器Fin-n、电容Cin-n、反激变压器Tn、二极管DH-n、待测功率器件QL-n和功率器件驱动电路n（包括第一与非门Ubu-n、二极管Dbu-n、第一电阻器Rbu-n、电容Cbu-n、第二与非门Ubu-2n以及驱动器），将每一个半导体器件测试电路的原边电路的两端分别连接至直流母线上，以形成回路，同时，将每一个半导体器件测试电路的功率器件驱动电路与信号源连接。应当理解的是，由于熔断器的设置，每一个半导体器件测试电路均各自独立。
因此，不仅可以有效降低测试系统的整体功耗，还可以有效解决在批量测试过程中被测器件测试条件、损耗不一致的问题，从而最大限度的模拟实际反激适配器的工况。而且测试系统所涉及的测试温度、测试电压、测试电流、测试频率、测试占空比、测试器件数量均可以根据加速条件进行调节，以满足多维度的加速测试需求。
上述实施例仅例示性说明本申请的原理及其功效，而非用于限制本申请。任何熟悉此技术的人士皆可在不违背本申请的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本申请所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本申请的权利要求所涵盖。
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Claims (20)

  1. 一种功率器件驱动电路，包括：
    信号源，用于产生初始驱动信号；以及
    缓冲电路，电连接于所述信号源与待测功率器件的栅极之间，用于接收所述初始驱动信号，基于所述待测功率器件的测试工况，对所述初始驱动信号进行延时处理并输出经延时处理的栅极驱动信号，其中，所述栅极驱动信号用于控制所述待测功率器件在所述待测功率器件的漏源极电压振荡到谷底时开通。
  2. 根据权利要求1所述的功率器件驱动电路，其中，所述缓冲电路包括：
    第一RC缓冲电路，包括第一电阻器和第一电容，所述第一电容的一端连接所述第一电阻器，所述第一电容的另一端接地；所述第一RC缓冲电路用于利用所述第一电容的充放电过程对所述初始驱动信号进行延时处理得到所述栅极驱动信号。
  3. 根据权利要求1所述的功率器件驱动电路，其中，所述缓冲电路包括：
    第二RC缓冲电路，电连接于所述信号源，包括第二电阻器和第二电容，所述第二电容的一端连接所述第二电阻器，所述第二电容的另一端接地；所述第二RC缓冲电路用于利用所述第二电容的充放电过程对所述初始驱动信号进行延时处理得到第一驱动信号；
    第一逻辑门调整电路，电连接至所述第二RC缓冲电路与所述待测功率器件之间，用于将所述第二RC缓冲电路输出的第一驱动信号进行逻辑运算得到所述栅极驱动信号。
  4. 根据权利要求3所述的功率器件驱动电路，其中，所述第一逻辑门调整电路为与门电路，所述与门电路的输入端与所述第二RC缓冲电路连接，用于接收第一驱动信号；所述与门电路的输出端与所述待测功率器件连接，用于将所述第二RC缓冲电路输出的第一驱动信号进行与运算得到所述栅极驱动信号。
  5. 根据权利要求1所述的功率器件驱动电路，其中，所述缓冲电路还包括：
    第一与非门电路，所述第一与非门电路的输入端连接所述信号源，用于接收所述信号源发出的第一初始驱动信号，且输出所述第一初始驱动信号经由与非运算后得到第二初始驱动信号；
    第三RC缓冲电路，电连接所述第一与非门电路，所述第三RC缓冲电路包括第三电阻器和第三电容，所述第三电容的一端连接所述第三电阻器，所述第三电容的另一端接地；所述第三RC缓冲电路用于利用所述第三电容的充放电过程对所述第二初始驱动信号进行延时处理得到第二驱动信号；
    第二与非门电路，所述第二与非门电路的输入端连接所述第三RC缓冲电路，用于接收所述第二驱动信号，所述第二与非门的输出端连接于所述待测功率器件，用于将接收到的所述第二驱动信号进行与非运算得到所述栅极驱动信号。
  6. 根据权利要求5所述的功率器件驱动电路，其中，所述缓冲电路还包括：
    二极管，所述二极管的阳极连接至所述第一与非门电路的输出端，所述二极管的阴极连接至所述第二与非门电路的输入端。
  7. 根据权利要求5所述的功率器件驱动电路，其中，所述第三电阻器包括可调电阻器，所述可调电阻器用于调节所述第三RC缓冲电路中的电阻值，以将所述第二初始驱动信号延时至所述待测功率器件的漏源极电压振荡到谷底的时刻。
  8. 一种半导体器件测试电路，包括原边电路和副边电路，其中所述原边电路包括串联的原边绕组和原边待测功率器件，所述原边电路的两端用于连接测试电源以形成回路，所述副边电路包括串联的副边绕组和副边待测晶体管，所述原边绕组和所述副边绕组形成反激变压器，所述原边电路和所述副边电路并联且接地，其中所述原边电路还包括：
    第一功率器件驱动电路，连接至所述原边待测功率器件，所述第一功率器件驱动电路包括：信号源，用于产生初始驱动信号；以及缓冲电路，电连接于所述信号源与所述原边待测功率器件的栅极之间，用于根据所述原边待测功率器件的测试工况对所述初始驱动信号进行处理，并输出针对所述原边待测功率器件的第一栅极驱动信号，以基于所述第一栅极驱动信号控制所述原边待测功率器件在所述原边待测功率器件的漏源极电压振荡到谷底时开通。
  9. 根据权利要求8所述的半导体器件测试电路，其中，所述副边待测晶体管包括副边待测功率器件，所述副边电路还包括：
    第二功率器件驱动电路，连接至所述副边待测功率器件，所述第二功率器件驱动电路包括：信号源，用于产生初始驱动信号；以及缓冲电路，电连接于所述信号源与所述副边待测功率器件的栅极之间，用于根据所述副边待测功率器件的测试工况对所述初始驱动信号进行处理，并输出针对所述副边待测功率器件的第二栅极驱动信号，以基于所述第二栅极驱动信号控制所述副边待测功率器件在所述副边待测功率器件的漏源极电压振荡到谷底时开通。
  10. 根据权利要求8或9所述的半导体器件测试电路，其中，所述缓冲电路包括：
    第一RC缓冲电路，包括第一电阻器和第一电容，所述第一电容的一端连接所述第一电阻器，所述第一电容的另一端接地；所述第一RC缓冲电路用于利用所述第一电容的充放电过程对所述初始驱动信号进行延时处理得到所述栅极驱动信号。
  11. 根据权利要求8或9所述的半导体器件测试电路，其中，所述缓冲电路包括：
    第二RC缓冲电路，电连接于所述信号源，包括第二电阻器和第二电容，所述第二电容的一端连接所述第二电阻器，所述第二电容的另一端接地；所述第二RC缓冲电路用于利用所述第二电容的充放电过程对所述初始驱动信号进行延时处理得到第一驱动信号；
    第一逻辑门调整电路，电连接至所述第二RC缓冲电路，与所述待测功率器件之间，用于将所述第二RC缓冲电路输出的第一驱动信号进行逻辑运算得到所述栅极驱动信号。
  12. 根据权利要求11所述的半导体器件测试电路，其中，所述第一逻辑门调整电路为与门电路，所述与门电路的输入端与所述第二RC缓冲电路连接，用于接收第一驱动信号；所述与门电路的输出端与所述待测功率器件连接，用于将所述第二RC缓冲电路输出的第一驱动信号进行与运算得到所述栅极驱动信号。
  13. 根据权利要求8或9所述的半导体器件测试电路，其中，所述缓冲电路包括：
    第一与非门电路，所述第一与非门电路的输入端连接所述信号源，用于接收所述信号源发出的第一初始驱动信号，且输出所述第一初始驱动信号经由与非运算后得到第二初始驱动信号；
    第三RC缓冲电路，电连接所述第一与非门电路，所述第三RC缓冲电路包括第三电阻器和第三电容，所述第三电容的一端连接所述第三电阻器，所述第三电容的另一端接地；所述第三RC缓冲电路用于利用所述第三电容的充放电过程对所述第二初始驱动信号进行延时处理得到第二驱动信号；
    第二与非门电路，所述第二与非门电路的输入端连接所述第三RC缓冲电路，用于接收所述第二驱动信号，所述第二与非门的输出端连接于所述待测功率器件，用于将接收到的所述第二驱动信号进行与非运算得到所述栅极驱动信号。
  14. 根据权利要求13所述的半导体器件测试电路，其中，所述缓冲电路还包括：
    二极管，所述二极管的阳极连接至所述第一与非门电路的输出端，所述二极管的阴极连接至所述第二与非门电路的输入端。
  15. 一种半导体器件测试系统，包括：
    多个原边电路和副边电路，其中每个所述原边电路包括串联的原边绕组和原边待测功率器件，每个所述原边电路的两端用于连接测试电源以形成回路，每个所述副边电路包括串联的副边绕组和副边待测晶体管，每个所述原边绕组和每个所述副边绕组形成反激变压器，每个所述原边电路和每个所述副边电路并联且接地；
    其中每个所述原边电路还包括第一功率器件驱动电路，连接至所述原边待测功率器件；和/或所述副边待测晶体管包括副边待测功率器件，每个所述副边电路还包括连接至所述副边待测功率器件的第二功率器件驱动电路；
    其中所述第一功率器件驱动电路和/或所述第二功率器件驱动电路包括功率器件驱动电路，所述功率器件驱动电路包括：
    信号源，用于产生初始驱动信号；以及
    缓冲电路，电连接于所述信号源与待测功率器件的栅极之间，用于接收所述初始驱动信号，基于所述待测功率器件的测试工况，对所述初始驱动信号进行延时处理并输出经延时处理的栅极驱动信号，其中，所述栅极驱动信号用于控制所述待测功率器件在所述待测功率器件的漏源极电压振荡到谷底时开通；
    多个所述功率器件驱动电路基于其信号源产生同一初始驱动信号，其中每个所述功率器件驱动电路用于根据其对应的原边待测功率器件或者副边待测功率器件的测试工况对所述初始驱动信号进行处理以得到栅极驱动信号，并向其对应的原边待测功率器件或者副边待测功率器件输出对应的栅极驱动信号，以基于对应的栅极驱动信号控制其对应的原边待测功率器件在所述原边待测功率器件的漏源极电压振荡到谷底时开通，或者控制其对应的副边待测功率器件在所述副边待测功率器件的漏源极电压振荡到谷底时开通。
  16. 根据权利要求15所述的半导体器件测试系统，其中，所述缓冲电路包括：
    第一RC缓冲电路，包括第一电阻器和第一电容，所述第一电容的一端连接所述第一电阻器，所述第一电容的另一端接地；所述第一RC缓冲电路用于利用所述第一电容的充放电过程对所述初始驱动信号进行延时处理得到所述栅极驱动信号。
  17. 根据权利要求15所述的半导体器件测试系统，其中，所述缓冲电路包括：
    第二RC缓冲电路，电连接于所述信号源，包括第二电阻器和第二电容，所述第二电容的一端连接所述第二电阻器，所述第二电容的另一端接地；所述第二RC缓冲电路用于利用所述第二电容的充放电过程对所述初始驱动信号进行延时处理得到第一驱动信号；
    第一逻辑门调整电路，电连接至所述第二RC缓冲电路与所述待测功率器件之间，用于将所述第二RC缓冲电路输出的第一驱动信号进行逻辑运算得到所述栅极驱动信号。
  18. 根据权利要求17所述的半导体器件测试系统，其中，所述第一逻辑门调整电路为第一与门电路，所述与门电路的输入端与所述第二RC缓冲电路连接，用于接收第一驱动信号；所述与门电路的输出端与所述待测功率器件连接，用于将所述第二RC缓冲电路输出的第一驱动信号进行与运算得到所述栅极驱动信号。
  19. 根据权利要求15所述的半导体器件测试系统，其中，所述缓冲电路包括：
    第一与非门电路，所述第一与非门电路的输入端连接所述信号源，用于接收所述信号源发出的第一初始驱动信号，且输出所述第一初始驱动信号经由与非运算后得到第二初始驱动信号；
    第三RC缓冲电路，电连接所述第一与非门电路，所述第三RC缓冲电路包括第三电阻器和第三电容，所述第三电容的一端连接所述第三电阻器，所述第三电容的另一端接地；所述第三RC缓冲电路用于利用所述第三电容的充放电过程对所述第二初始驱动信号进行延时处理得到第二驱动信号；
    第二与非门电路，所述第二与非门电路的输入端连接所述第三RC缓冲电路，用于接收所述第二驱动信号，所述第二与非门的输出端连接于所述待测功率器件，用于将接收到的所述第二驱动信号进行与非运算得到所述栅极驱动信号。
  20. 根据权利要求19所述的半导体器件测试系统，其中，所述缓冲电路还包括：
    二极管，所述二极管的阳极连接至所述第一与非门电路的第一输出端，所述二极管的阴极连接至所述第二与非门电路的输入端。
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