WO2024197716A1

WO2024197716A1 - Magnetoresistive memory unit, preparation method, array circuit, and binary neural network chip

Info

Publication number: WO2024197716A1
Application number: PCT/CN2023/085143
Authority: WO
Inventors: 邢国忠; 刘龙; 许晓欣; 刘明
Original assignee: 中国科学院微电子研究所
Priority date: 2023-03-30
Filing date: 2023-03-30
Publication date: 2024-10-03

Abstract

A magnetoresistive memory unit, a preparation method, an array circuit, and a binary neural network chip. The magnetoresistive memory unit comprises a heavy metal layer configured to input a write current; a first magnetic tunnel junction, arranged on one side of a bottom surface of the heavy metal layer, a first preset included angle being formed between the easy axis of the first magnetic tunnel junction and an input direction of the write current; and a second magnetic tunnel junction, arranged on the other side of the bottom surface of the heavy metal layer, a second preset included angle being formed between the easy axis of the second magnetic tunnel junction and the input direction of the write current. The first magnetic tunnel junction and the second magnetic tunnel junction are configured to input a read current.

Description

Magnetoresistive memory unit, preparation method, array circuit and binary neural network chip

Technical Field

本公开涉及磁阻存储器技术领域，更具体地，涉及一种磁阻存储器单元、磁阻存储器单元的制备方法、基于磁阻存储器单元的阵列电路和二值神经网络芯片。The present disclosure relates to the technical field of magnetoresistive memory, and more specifically, to a magnetoresistive memory unit, a method for preparing a magnetoresistive memory unit, an array circuit based on the magnetoresistive memory unit, and a binary neural network chip.

Background Art

卷积神经网络(Convolutional Neural Networks，CNN)被大量应用于图片识别、语音识别、自然语言处理等多种领域，显示出优异的性能。然而大量的向量矩阵乘加运算导致的巨大的存储和计算资源开销，限制了大规模卷积神经网络的硬件实现。因此，近年来二值神经网络(Binary Neural Network，BNN)受到了越来越多的关注。Convolutional Neural Networks (CNN) have been widely used in many fields such as image recognition, speech recognition, and natural language processing, showing excellent performance. However, the huge storage and computing resource overhead caused by a large number of vector-matrix multiplication and addition operations limits the hardware implementation of large-scale convolutional neural networks. Therefore, Binary Neural Networks (BNN) have received more and more attention in recent years.

二值神经网络通过将卷积神经网络的突触权值、神经元输出二值化，用点积代替高精度的乘加运算，简化计算任务。在达到减少存储资源开销和计算资源负担目标的同时，在各种大规模数据集上实现与卷积神经网络相当的精确度。基于传统的冯·诺依曼架构的硬件神经网络，由于存储墙和功耗墙问题，难以大规模集成和应用。为了克服冯·诺依曼瓶颈，存内计算(In-Memory Computing，IMC)作为一种新的计算范式开始兴起。近年来，基于新型非易失存储器的存内计算平台的发展，将硬件神经网络带入新的发展时期。在各种新型非易失存储器中，SOT-MRAM(Spin-Orbit Torque Magnetic Random Access Memory，自旋轨道矩磁随机存储器)由于高读写速度、无限次擦写次数、高数据保持时间、低写入功耗与CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)工艺兼容等优点，成为存内计算和硬件神经网络实现的理想载体。Binary neural networks simplify computational tasks by binarizing the synaptic weights and neuron outputs of convolutional neural networks and replacing high-precision multiplication and addition operations with dot products. While achieving the goal of reducing storage resource overhead and computing resource burden, it achieves accuracy comparable to that of convolutional neural networks on various large-scale data sets. Hardware neural networks based on traditional von Neumann architecture are difficult to integrate and apply on a large scale due to storage wall and power wall problems. In order to overcome the von Neumann bottleneck, in-memory computing (IMC) has begun to emerge as a new computing paradigm. In recent years, the development of in-memory computing platforms based on new non-volatile memories has brought hardware neural networks into a new development period. Among various new types of non-volatile memories, SOT-MRAM (Spin-Orbit Torque Magnetic Random Access Memory) has become an ideal carrier for in-memory computing and hardware neural network implementation due to its advantages such as high read and write speed, unlimited erase and write times, high data retention time, low write power consumption and compatibility with CMOS (Complementary Metal Oxide Semiconductor) process.

然而，目前SOT-MRAM存在着如下问题：However, SOT-MRAM currently has the following problems:

(1)隧道磁电阻较小(Tunneling magnetoresistance，TMR)；(1) Small tunneling magnetoresistance (TMR);

(2)type x和type z型SOT-MRAM需要外加磁场辅助实现电控磁化翻转的问题。(2) Type x and type z SOT-MRAM require external magnetic field assistance to achieve electrically controlled magnetization reversal.

隧道磁电阻小限制SOT-MRAM的读性能，会导致较高的度错误率，而外加磁场不利于大规模集成。The small tunnel magnetoresistance limits the read performance of SOT-MRAM, resulting in a higher error rate, while the external magnetic field is not conducive to large-scale integration.

发明内容Summary of the invention

有鉴于此，本公开实施例提供了一种磁阻存储器单元、磁阻存储器单元的制备方法、基于磁阻存储器单元的阵列电路和二值神经网络芯片。In view of this, the embodiments of the present disclosure provide a magnetoresistive memory unit, a method for preparing the magnetoresistive memory unit, an array circuit based on the magnetoresistive memory unit, and a binary neural network chip.

本公开实施例的一个方面提供了一种磁阻存储器单元，包括： One aspect of an embodiment of the present disclosure provides a magnetoresistive memory cell, comprising:

重金属层，上述重金属层被构造成输入写电流；A heavy metal layer, wherein the heavy metal layer is configured to input a write current;

第一磁隧道结，设置于上述重金属层底面一侧，其中，上述第一磁隧道结所在的易轴与上述写电流的输入方向呈第一预设夹角；A first magnetic tunnel junction is disposed on one side of the bottom surface of the heavy metal layer, wherein the easy axis of the first magnetic tunnel junction forms a first preset angle with the input direction of the write current;

第二磁隧道结，设置于上述重金属层底面的另一侧，其中，上述第二磁隧道结所在的易轴与上述写电流的输入方向呈第二预设夹角；A second magnetic tunnel junction is disposed on the other side of the bottom surface of the heavy metal layer, wherein the easy axis of the second magnetic tunnel junction forms a second preset angle with the input direction of the write current;

其中，上述第一磁隧道结和上述第二磁隧道结被构造成输入读电流。The first magnetic tunnel junction and the second magnetic tunnel junction are configured to input a read current.

根据本公开的实施例，上述第一预设夹角与上述第二预设夹角互补，上述第一预设夹角的范围为10°～60°。According to an embodiment of the present disclosure, the first preset angle is complementary to the second preset angle, and the first preset angle is in the range of 10° to 60°.

根据本公开的实施例，上述第一磁隧道结和上述第二磁隧道结中任一磁隧道结均包括：According to an embodiment of the present disclosure, any one of the first magnetic tunnel junction and the second magnetic tunnel junction includes:

底电极；bottom electrode;

钉扎层，设置在上述底电极的顶面，其中，上述钉扎层被构造成固定铁磁参考层的磁化方向；A pinning layer, disposed on the top surface of the bottom electrode, wherein the pinning layer is configured to fix the magnetization direction of the ferromagnetic reference layer;

上述铁磁参考层，设置在上述钉扎层的顶面；The ferromagnetic reference layer is arranged on the top surface of the pinned layer;

势垒层，设置在上述铁磁参考层的顶面；A barrier layer, arranged on the top surface of the ferromagnetic reference layer;

铁磁自由层，设置在上述势垒层的顶面；A ferromagnetic free layer is arranged on the top surface of the barrier layer;

根据本公开的实施例，上述钉扎层包括：According to an embodiment of the present disclosure, the pinning layer includes:

反铁磁层或合成亚铁磁层或合成反铁磁层，设置在上述底电极的顶面；An antiferromagnetic layer or a synthetic ferrimagnetic layer or a synthetic antiferromagnetic layer is arranged on the top surface of the bottom electrode;

空间层，设置在上述反铁磁层或合成亚铁磁层或合成反铁磁层的顶面，其中，上述空间层被构造成对上述铁磁参考层和上述反铁磁层或合成亚铁磁层或合成反铁磁层的磁化方向进行耦合。A space layer is arranged on the top surface of the above-mentioned antiferromagnetic layer or synthetic ferrimagnetic layer or synthetic antiferromagnetic layer, wherein the above-mentioned space layer is constructed to couple the magnetization directions of the above-mentioned ferromagnetic reference layer and the above-mentioned antiferromagnetic layer or synthetic ferrimagnetic layer or synthetic antiferromagnetic layer.

本公开实施例的另一个方面提供了一种磁阻存储器单元的制备方法，包括：Another aspect of the embodiments of the present disclosure provides a method for preparing a magnetoresistive memory cell, comprising:

对硬掩膜后的初始薄膜进行图形化处理，得到图形化后的薄膜，其中，上述初始薄膜用于生成第一磁隧道结和第二磁隧道结；Performing patterning on the initial thin film behind the hard mask to obtain a patterned thin film, wherein the initial thin film is used to generate a first magnetic tunnel junction and a second magnetic tunnel junction;

对上述图形化后的薄膜进行刻蚀，得到初始的存储器单元，其中，上述初始的存储器单元包括上述第一磁隧道结和上述第二磁隧道结，上述第一磁隧道结和上述第二磁隧道结分别与上述初始薄膜呈第一预设夹角和第二预设夹角；Etching the patterned thin film to obtain an initial memory cell, wherein the initial memory cell includes the first magnetic tunnel junction and the second magnetic tunnel junction, and the first magnetic tunnel junction and the second magnetic tunnel junction are respectively at a first preset angle and a second preset angle with the initial thin film;

在上述初始的存储器单元的顶面生长重金属层；growing a heavy metal layer on the top surface of the initial memory cell;

分别在上述重金属层的顶面和上述初始的存储器单元的底面生长顶电极和底电极，得到上述磁阻存储器单元。A top electrode and a bottom electrode are grown on the top surface of the heavy metal layer and the bottom surface of the initial memory unit respectively, so as to obtain the magnetoresistive memory unit.

根据本公开的实施例，上述初始薄膜是根据将钉扎层、铁磁参考层、势垒层和铁磁自由层生成的； According to an embodiment of the present disclosure, the initial thin film is generated by forming a pinned layer, a ferromagnetic reference layer, a barrier layer and a ferromagnetic free layer;

根据本公开的实施例，上述对上述图形化后的薄膜进行刻蚀，得到初始的存储器单元，包括：According to an embodiment of the present disclosure, etching the patterned thin film to obtain an initial memory cell includes:

对上述图形化后的薄膜进行第一次刻蚀，刻蚀至绝缘衬底，得到有效器件区域；Performing a first etching on the patterned thin film to the insulating substrate to obtain an effective device area;

对上述有效器件区域进行第二次刻蚀，刻蚀至所述底电极处，得到磁隧道结，上述磁隧道结包括第一磁隧道结和第二磁隧道结，上述初始的存储器单元包括上述磁隧道结。The effective device region is etched a second time, and the etching is performed to the bottom electrode to obtain a magnetic tunnel junction, wherein the magnetic tunnel junction includes a first magnetic tunnel junction and a second magnetic tunnel junction, and the initial memory unit includes the magnetic tunnel junction.

根据本公开的实施例，上述对上述图形化后的薄膜进行刻蚀，得到初始的存储器单元，还包括：According to an embodiment of the present disclosure, the above-mentioned etching of the patterned thin film to obtain an initial memory cell also includes:

在上述有效器件区域上生长绝缘保护层，得到绝缘的磁隧道结；Growing an insulating protective layer on the effective device region to obtain an insulating magnetic tunnel junction;

对上述绝缘的磁隧道结进行抛光处理，得到抛光后的磁隧道结；Polishing the insulated magnetic tunnel junction to obtain a polished magnetic tunnel junction;

对上述抛光后的磁隧道结进行硬掩膜图形化处理，得到图形化后的磁隧道结，以对上述图形化后的磁隧道结进行第二次刻蚀，得到过渡的存储器单元；Performing hard mask patterning on the polished magnetic tunnel junction to obtain a patterned magnetic tunnel junction, and performing a second etching on the patterned magnetic tunnel junction to obtain a transitional memory unit;

在上述过渡的存储器单元上生长绝缘保护层，得到绝缘的存储器单元；growing an insulating protective layer on the transitional memory cell to obtain an insulating memory cell;

对上述绝缘的存储器单元进行抛光处理，得到上述初始的存储器单元。The insulated memory cell is polished to obtain the initial memory cell.

本公开实施例的另一个方面提供了一种基于磁阻存储器单元的阵列电路，包括：Another aspect of the disclosed embodiments provides an array circuit based on a magnetoresistive memory cell, comprising:

竖直间隔排列的多个线组，每个线组包括写字线、间隔一预设距离的第一读字线和第二读字线以及源线；A plurality of line groups arranged vertically and spaced apart, each line group comprising a write word line, a first read word line and a second read word line spaced apart by a preset distance, and a source line;

水平间隔排列的多个位线组，其中，上述位线组包括从上到下水平排列的写控制位线和读控制位线，一个上述位线组中的写控制位线和读控制位线、每个上述线组内的上述第一读字线和上述第二读字线围成一放置区域；A plurality of bit line groups arranged horizontally at intervals, wherein the bit line groups include write control bit lines and read control bit lines arranged horizontally from top to bottom, and the write control bit lines and read control bit lines in one of the bit line groups, the first read word lines and the second read word lines in each of the line groups form a placement area;

多个磁阻存储器单元，每个上述放置区域中设置一个上述磁阻存储器单元；A plurality of magnetoresistive memory units, one magnetoresistive memory unit is arranged in each of the placement areas;

其中，上述磁阻存储器单元和对应于上述放置区域的上述线组和上述位线的连接方式包括：The connection method of the magnetoresistive memory unit, the line group corresponding to the placement area, and the bit line includes:

重金属层的一端通过第一晶体管分别与上述写控制位线和上述写字线连接，另一端与上述源线连接；One end of the heavy metal layer is connected to the write control bit line and the write word line respectively through the first transistor, and the other end is connected to the source line;

第一磁隧道结通过第二晶体管分别与上述第一读字线和上述读控制位线连接，第二磁隧道结通过第三晶体管分别与上述第二读字线和上述读控制位线连接。The first magnetic tunnel junction is connected to the first read word line and the read control bit line respectively through the second transistor, and the second magnetic tunnel junction is connected to the second read word line and the read control bit line respectively through the third transistor.

根据本公开的实施例，上述第一晶体管的源极和漏极分别与上述重金属层、上述写字线连接，上述第一晶体管的栅极与上述写控制位线连接；According to an embodiment of the present disclosure, the source and drain of the first transistor are respectively connected to the heavy metal layer and the write word line, and the gate of the first transistor is connected to the write control bit line;

上述第二晶体管的源极和漏极分别与上述第一磁隧道结、上述第一读字线连接，上述第二晶体管的栅极与上述读控制位线连接；The source and drain of the second transistor are connected to the first magnetic tunnel junction and the first read word line respectively, and the gate of the second transistor is connected to the read control bit line;

上述第三晶体管的源极和漏极分别与上述第二磁隧道结、上述第二读字线连接，上述第三晶体管的栅极与上述读控制位线连接。The source and drain of the third transistor are connected to the second magnetic tunnel junction and the second read word line respectively. The gates of the three transistors are connected to the above-mentioned read control bit line.

本公开实施例的另一个方面提供了一种二值神经网络芯片，包括：解码单元、缓存单元、指令存储单元、存算单元、数据处理单元和时钟单元；Another aspect of the disclosed embodiment provides a binary neural network chip, including: a decoding unit, a cache unit, an instruction storage unit, a storage and calculation unit, a data processing unit, and a clock unit;

其中，上述存算单元包括阵列电路构建的突触阵列，上述阵列电路包括多列磁阻存储器单元组，每列上述磁阻存储器单元组包括多个磁阻存储器单元，每列上述磁阻存储器单元组被构造成存储一个神经元的突触权值。Among them, the above-mentioned storage and computing unit includes a synaptic array constructed by an array circuit, the above-mentioned array circuit includes multiple columns of magnetoresistive memory unit groups, each column of the above-mentioned magnetoresistive memory unit group includes multiple magnetoresistive memory units, and each column of the above-mentioned magnetoresistive memory unit group is constructed to store the synaptic weight of a neuron.

根据本公开的实施例，针对每列上述磁阻存储器单元组，在上述磁阻存储器单元的第一磁隧道结的读电流大于上述磁阻存储器单元的的读电流的情况下，确定上述磁阻存储器单元的突触权值为正的目标数值；According to an embodiment of the present disclosure, for each column of the magnetoresistive memory cell group, when the read current of the first magnetic tunnel junction of the magnetoresistive memory cell is greater than the read current of the magnetoresistive memory cell, the synaptic weight of the magnetoresistive memory cell is determined to be a positive target value;

在上述磁阻存储器单元的第一磁隧道结的读电流小于上述磁阻存储器单元的的读电流的情况下，确定上述磁阻存储器单元的突触权值为负的目标数值；When the read current of the first magnetic tunnel junction of the magnetoresistive memory unit is less than the read current of the magnetoresistive memory unit, determining a negative target value of the synaptic weight of the magnetoresistive memory unit;

在多个上述磁阻存储器单元的突触权值之和为正数的情况下，上述神经元输出第一数值；When the sum of the synaptic weights of the plurality of magnetoresistive memory units is a positive number, the neuron outputs a first value;

在多个上述磁阻存储器单元的突触权值之和为负数的情况下，上述神经元输出第二数值。When the sum of the synaptic weights of the plurality of magnetoresistive memory units is a negative number, the neuron outputs a second value.

本公开的磁阻存储器单元、制备方法、阵列电路和二值神经网络芯片具有如下效果：The magnetoresistive memory unit, preparation method, array circuit and binary neural network chip disclosed in the present invention have the following effects:

(1)磁阻储器单元中由于第一磁隧道结和第二磁隧道结设置在金属层下侧，并分别偏转了第一预设夹角与第二预设夹角，可实现无外加磁场辅助的超快磁化翻转，有利于大规模集成。(1) In the magnetoresistive storage unit, since the first magnetic tunnel junction and the second magnetic tunnel junction are arranged at the lower side of the metal layer and are deflected by the first preset angle and the second preset angle respectively, ultrafast magnetization reversal without external magnetic field assistance can be achieved, which is conducive to large-scale integration.

(2)磁阻存储器单元采用1HM2SOT-MTJ(1个重金属层，2个自旋轨道矩的磁隧道结)结构，通过第一磁隧道结和第二磁隧道结在反转后实现阻态总是相反，构成互补结构存一位比特。在读取信息时可通过自参考机制实现读取，提高读取裕度，进而增强读可靠性，降低读延时。并且其工作时无需外加磁场实现翻转。(2) The magnetoresistive memory unit adopts a 1HM2SOT-MTJ (1 heavy metal layer, 2 spin-orbit moment magnetic tunnel junctions) structure. The resistance states of the first and second magnetic tunnel junctions are always opposite after inversion, forming a complementary structure to store one bit. When reading information, it can be read through a self-reference mechanism, which improves the reading margin, thereby enhancing the reading reliability and reducing the reading delay. In addition, no external magnetic field is required to achieve flipping during operation.

(3)磁阻存储器单元采用钉扎层作为底钉扎结构，利于后续对重金属层、重金属层\铁磁自由层界面的调控，优化读性能。(3) The magnetoresistive memory unit uses a pinned layer as the bottom pinned structure, which is beneficial to the subsequent regulation of the heavy metal layer and the heavy metal layer\ferromagnetic free layer interface to optimize the read performance.

(4)磁阻存储器单元可实现基于3T2SOT-MTJ(3个晶体管，2个自旋轨道矩的磁隧道结)的1R1W(一读一写)双端口存储阵列，可以分块同时读写，极大改善读写效率，提高存储单元并行度。(4) Magnetoresistive memory cells can realize a 1R1W (one read and one write) dual-port storage array based on 3T2SOT-MTJ (three transistors, two spin-orbit moment magnetic tunnel junctions), which can read and write in blocks simultaneously, greatly improving the read and write efficiency and increasing the parallelism of storage cells.

(5)二值神经网络芯片的存算单元在读取时可以整列读取，读取的同时实现突触权值加和，存算单元的输出可以直接作为二值神经元的输出，极大提高了二值神经网络的并行度。(5) The storage and computing unit of the binary neural network chip can read the entire column when reading, and realize the summation of synaptic weights while reading. The output of the storage and computing unit can be directly used as the output of the binary neuron, which greatly improves the parallelism of the binary neural network.

BRIEF DESCRIPTION OF THE DRAWINGS

通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：The above and other objects, features and advantages of the present disclosure will be described in detail below with reference to the accompanying drawings. To make it clearer, in the attached figure:

图1示意性示出了根据本公开实施例的磁阻存储器单元的结构示意图；FIG1 schematically shows a schematic structural diagram of a magnetoresistive memory unit according to an embodiment of the present disclosure;

图2示意性示出了根据本公开实施例的第一预设夹角与第二预设夹角的关系示意图；FIG2 schematically shows a schematic diagram of the relationship between the first preset angle and the second preset angle according to an embodiment of the present disclosure;

图3示意性示出了根据本公开实施例的磁阻存储器单元的制备流程示意图；FIG3 schematically shows a schematic diagram of a preparation process of a magnetoresistive memory unit according to an embodiment of the present disclosure;

图4示意性示出了根据本公开实施例的阵列电路的结构示意图；FIG4 schematically shows a schematic diagram of the structure of an array circuit according to an embodiment of the present disclosure;

图5示意性示出了根据本公开实施例的3T2SOT-MTJ单元结构的结构示意图；FIG5 schematically shows a schematic structural diagram of a 3T2SOT-MTJ unit structure according to an embodiment of the present disclosure;

图6示意性示出了根据本公开实施例的阵列电路的仿真结果示意图；FIG6 schematically shows a simulation result diagram of an array circuit according to an embodiment of the present disclosure;

图7示意性示出了根据本公开实施例的二值神经网络芯片的结构示意图；以及FIG7 schematically shows a schematic diagram of the structure of a binary neural network chip according to an embodiment of the present disclosure; and

图8示意性示出了根据本公开实施例的磁阻存储器单元的存储状态和突触权值的对应关系示意图。FIG8 schematically shows a schematic diagram of the correspondence between the storage state of a magnetoresistive memory unit and the synaptic weight according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本公开实施例的全面理解。然而，明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

在此使用的术语仅仅是为了描述具体实施例，而并非意在限制本公开。在此使用的术语“包括”、“包含”等表明了所述特征、步骤、操作和/或部件的存在，但是并不排除存在或添加一个或多个其他特征、步骤、操作或部件。The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "include", "comprising", etc. used herein indicate the existence of the features, steps, operations and/or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

在此使用的所有术语(包括技术和科学术语)具有本领域技术人员通常所理解的含义，除非另外定义。应注意，这里使用的术语应解释为具有与本说明书的上下文相一致的含义，而不应以理想化或过于刻板的方式来解释。All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

在本公开的上下文中，当将一层/元件称作位于另一层/元件“顶面”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“顶面”，那么当调转朝向时，该层/元件可以位于该另一层/元件“底面”。In the context of the present disclosure, when a layer/element is referred to as being "on top" of another layer/element, the layer/element can be directly on the other layer/element, or there can be an intervening layer/element between them. Additionally, if a layer/element is "on top" of another layer/element in one orientation, the layer/element can be "under" the other layer/element when the orientation is reversed.

在使用类似于“A、B和C等中至少一个”这样的表述的情况下，一般来说应该按照本领域技术人员通常理解该表述的含义来予以解释(例如，“具有A、B和C中至少一个的系统”应包括但不限于单独具有A、单独具有B、单独具有C、具有A和B、具有A和C、具有B和C、和/或具有A、B、C的系统等)。 When using expressions such as "at least one of A, B, and C", they should generally be interpreted according to the meaning of the expression commonly understood by technical personnel in this field (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and/or A, B, C, etc.).

本公开的实施例提供了一种磁阻存储器单元、磁阻存储器单元的制备方法、基于磁阻存储器单元的阵列电路和二值神经网络芯片。该磁阻存储器单元包括重金属层，重金属层被构造成输入写电流；第一磁隧道结，设置于重金属层底面一侧，其中，第一磁隧道结所在的易轴与写电流的输入方向呈第一预设夹角；第二磁隧道结，设置于重金属层底面的另一侧，其中，第二磁隧道结所在的易轴与写电流的输入方向呈第二预设夹角；其中，第一磁隧道结和第二磁隧道结被构造成输入读电流。The embodiments of the present disclosure provide a magnetoresistive memory unit, a method for preparing the magnetoresistive memory unit, an array circuit based on the magnetoresistive memory unit, and a binary neural network chip. The magnetoresistive memory unit includes a heavy metal layer, which is configured to input a write current; a first magnetic tunnel junction, which is arranged on one side of the bottom surface of the heavy metal layer, wherein the easy axis of the first magnetic tunnel junction and the input direction of the write current form a first preset angle; a second magnetic tunnel junction, which is arranged on the other side of the bottom surface of the heavy metal layer, wherein the easy axis of the second magnetic tunnel junction and the input direction of the write current form a second preset angle; wherein the first magnetic tunnel junction and the second magnetic tunnel junction are configured to input a read current.

图1示意性示出了根据本公开实施例的磁阻存储器单元的结构示意图。图2示意性示出了根据本公开实施例的第一预设夹角与第二预设夹角的关系示意图。Fig. 1 schematically shows a schematic diagram of the structure of a magnetoresistive memory unit according to an embodiment of the present disclosure. Fig. 2 schematically shows a schematic diagram of the relationship between a first preset angle and a second preset angle according to an embodiment of the present disclosure.

如图1所示，磁阻存储器单元包括：As shown in FIG1 , the magnetoresistive memory cell includes:

重金属层，所述重金属层被构造成输入写电流；a heavy metal layer configured to input a write current;

第一磁隧道结，设置于所述重金属层底面一侧，其中，所述第一磁隧道结所在的易轴与所述写电流的输入方向呈第一预设夹角；A first magnetic tunnel junction is disposed on one side of the bottom surface of the heavy metal layer, wherein the easy axis of the first magnetic tunnel junction forms a first preset angle with the input direction of the write current;

第二磁隧道结，设置于所述重金属层底面的另一侧，其中，所述第二磁隧道结所在的易轴与所述写电流的输入方向呈第二预设夹角；A second magnetic tunnel junction is disposed on the other side of the bottom surface of the heavy metal layer, wherein the easy axis of the second magnetic tunnel junction forms a second preset angle with the input direction of the write current;

其中，所述第一磁隧道结和所述第二磁隧道结被构造成输入读电流。The first magnetic tunnel junction and the second magnetic tunnel junction are configured to input a read current.

根据本公开的实施例，预设夹角是指易轴在重金属层所在平面的投影与写电流的输入方向之间的夹角。所述第一预设夹角与所述第二预设夹角相对于所述写电流所在方向的偏转方向相反，大小相等。According to an embodiment of the present disclosure, the preset angle refers to the angle between the projection of the easy axis on the plane where the heavy metal layer is located and the input direction of the write current. The first preset angle and the second preset angle are opposite in deflection direction relative to the direction where the write current is located and are equal in magnitude.

在一种可能的实现方式中，第一磁隧道结和第二磁隧道结的横截面均为椭圆形。需要说明的是，本实施例中的椭圆形最优可为严格的椭圆形；但是由于工艺等限制，椭圆形也可指大致呈椭圆形。第一磁隧道结和第二磁隧道结整体可呈椭圆柱体。采用该种形状的磁隧道结其铁磁层易轴方向由于形状各向异性将沿着椭圆长轴方向。In a possible implementation, the cross-sections of the first magnetic tunnel junction and the second magnetic tunnel junction are both elliptical. It should be noted that the ellipse in this embodiment can be a strict ellipse at best; however, due to limitations such as process, the ellipse may also refer to a substantially elliptical shape. The first magnetic tunnel junction and the second magnetic tunnel junction may be an elliptical cylinder as a whole. The easy axis direction of the ferromagnetic layer of the magnetic tunnel junction adopting this shape will be along the direction of the major axis of the ellipse due to shape anisotropy.

在一种可能的实现方式中，如图2所示，第一预设夹角与所述第二预设夹角的大小应当相等，以保证第一磁隧道结和第二磁隧道结写入特性相同。并且，第一预设夹角与所述第二预设夹角的大小范围可确定为：10°～60°，可保证合适的阈值电流，当仅通过电流时就可使磁隧道结发生翻转。In a possible implementation, as shown in FIG2 , the first preset angle The second preset angle The sizes of should be equal to ensure that the first magnetic tunnel junction and the second magnetic tunnel junction have the same writing characteristics. In addition, the size range of the first preset angle and the second preset angle can be determined as: 10° to 60°, which can ensure a suitable threshold current, and the magnetic tunnel junction can be flipped when only current passes.

需要说明的是，磁隧道结的横截面不仅仅可以是上述示例中的椭圆形，也可以是其他形状，例如矩形等。It should be noted that the cross-section of the magnetic tunnel junction can be not only an ellipse as in the above example, but can also be other shapes, such as a rectangle.

根据本公开的实施例，磁阻储器单元中由于第一磁隧道结和第二磁隧道结设置在金属层下侧，并分别偏转了第一预设夹角与第二预设夹角，可实现无外加磁场辅助的超快磁化翻转，有利于大规模集成。According to the embodiments of the present disclosure, in the magnetoresistive storage unit, since the first magnetic tunnel junction and the second magnetic tunnel junction are arranged at the lower side of the metal layer and are deflected by the first preset angle and the second preset angle respectively, ultrafast magnetization switching without the assistance of an external magnetic field can be achieved. Facilitates large-scale integration.

根据本公开的实施例，所述第一磁隧道结和所述第二磁隧道结中任一磁隧道结(Magnetic Tunnel Junction，MTJ)均包括：According to an embodiment of the present disclosure, any one of the first magnetic tunnel junction and the second magnetic tunnel junction (Magnetic Tunnel Junction, MTJ) includes:

底电极；bottom electrode;

钉扎层，设置在所述底电极的顶面，其中，所述钉扎层被构造成固定铁磁参考层的磁化方向；a pinning layer disposed on a top surface of the bottom electrode, wherein the pinning layer is configured to fix a magnetization direction of the ferromagnetic reference layer;

所述铁磁参考层，设置在所述钉扎层的顶面；The ferromagnetic reference layer is disposed on the top surface of the pinned layer;

势垒层，设置在所述铁磁参考层的顶面；A barrier layer, disposed on the top surface of the ferromagnetic reference layer;

铁磁自由层，设置在所述势垒层的顶面；A ferromagnetic free layer, disposed on the top surface of the barrier layer;

根据本公开的实施例，所述钉扎层包括：According to an embodiment of the present disclosure, the pinning layer includes:

反铁磁层或合成亚铁磁层或合成反铁磁层，设置在所述底电极的顶面；an antiferromagnetic layer or a synthetic ferrimagnetic layer or a synthetic antiferromagnetic layer, arranged on the top surface of the bottom electrode;

空间层，设置在所述反铁磁层或合成亚铁磁层或合成反铁磁层的顶面，其中，所述空间层被构造成对所述铁磁参考层和所述反铁磁层或合成亚铁磁层或合成反铁磁层的磁化方向进行耦合。A space layer is arranged on the top surface of the antiferromagnetic layer or the synthetic ferrimagnetic layer or the synthetic antiferromagnetic layer, wherein the space layer is constructed to couple the magnetization directions of the ferromagnetic reference layer and the antiferromagnetic layer or the synthetic ferrimagnetic layer or the synthetic antiferromagnetic layer.

根据本公开的实施例，所述第一磁隧道结和所述第二磁隧道结中的铁磁参考层的磁化方向沿写电流方向分量相同。According to an embodiment of the present disclosure, the magnetization directions of the ferromagnetic reference layers in the first magnetic tunnel junction and the second magnetic tunnel junction are the same along the direction of the write current.

根据本公开的实施例，钉扎层为叠加的多层结构，可为反铁磁、合成反铁磁、合成亚铁磁等。铁磁参考层和铁磁自由层可为钴(Co)、硼化钴(CoB)、硼化铁(FeB)、钴铁硼(CoFeB)、坡莫合金(NiFe)、范德华二维材料、拓扑材料等其中之一或其组合。势垒层可为氧化镁(MgO)、氧化铝(Al₂O₃)等。重金属(SOC)层可由重金属材料组成。例如，可采用铂(Pt)、钽(Ta)和钨(W)中的任一种或合金。According to an embodiment of the present disclosure, the pinned layer is a stacked multilayer structure, which may be antiferromagnetic, synthetic antiferromagnetic, synthetic ferrimagnetic, etc. The ferromagnetic reference layer and the ferromagnetic free layer may be one of cobalt (Co), cobalt boride (CoB), iron boride (FeB), cobalt iron boron (CoFeB), Permalloy (NiFe), van der Waals two-dimensional materials, topological materials, etc., or a combination thereof. The barrier layer may be magnesium oxide (MgO), aluminum oxide (Al ₂ O ₃ ), etc. The heavy metal (SOC) layer may be composed of a heavy metal material. For example, any one of platinum (Pt), tantalum (Ta) and tungsten (W) or an alloy may be used.

根据本公开的实施例，由于第一磁隧道结和第二磁隧道结呈反对称状态；此时，当在重金属层中通过写电流时，第一磁隧道结和第二磁隧道结中铁磁自由层的磁化方向总是相反，可使得两个磁隧道结的阻态总是相反，二者呈互补状态。这样在通过不同的方向的写电流后，就可使第一磁隧道结和第二磁隧道结分别表现高阻状态或低阻状态，在向第一磁隧道结和第二磁隧道结通过读电流时，通过比较两个磁隧道结的读电流大小就可得到存储的阻态。在整个读写过程中，可由写电流实现亚纳秒级别的超快磁化翻转，无需外加磁场辅助。According to the embodiments of the present disclosure, since the first magnetic tunnel junction and the second magnetic tunnel junction are in an antisymmetric state, when a write current is passed through the heavy metal layer, the magnetization directions of the ferromagnetic free layers in the first magnetic tunnel junction and the second magnetic tunnel junction are always opposite, so that the resistance states of the two magnetic tunnel junctions are always opposite, and the two are in a complementary state. In this way, after passing write currents in different directions, the first magnetic tunnel junction and the second magnetic tunnel junction can be made to exhibit a high resistance state or a low resistance state respectively. When a read current is passed through the first magnetic tunnel junction and the second magnetic tunnel junction, the stored resistance state can be obtained by comparing the read currents of the two magnetic tunnel junctions. In the entire read and write process, the write current can achieve ultrafast magnetization reversal at the sub-nanosecond level without the assistance of an external magnetic field.

根据本公开的实施例，磁阻存储器单元采用钉扎层作为底钉扎结构，利于后续对重金属层、重金属层\铁磁自由层界面的调控，优化读性能。According to the embodiments of the present disclosure, the magnetoresistive memory unit adopts a pinning layer as a bottom pinning structure, which is beneficial to the subsequent regulation of the heavy metal layer and the heavy metal layer\ferromagnetic free layer interface and optimizes the read performance.

根据本公开的实施例，对磁阻存储器单元进行写操作时，过程如下：According to an embodiment of the present disclosure, when a write operation is performed on a magnetoresistive memory cell, the process is as follows:

对重金属层通过沿第一方向的写电流，以使磁阻存储器单元呈第一存储状态；第一存储状态为：第一磁隧道结呈高电阻状态，第二磁隧道结呈低电阻状态。例如，当第一磁隧道结和第二磁隧道结的铁磁参考层磁化方向均沿+x方向(即铁磁参考层磁化沿x轴分量为正)时，且第一方向为+x方向时，第一磁隧道结的磁化方向为沿-x方向，第二磁隧道结的磁化方向为沿+x方向。此时，第一磁隧道结中，铁磁自由层与铁磁参考层的磁化方向反平行，第一磁隧道结呈高电阻状态；第二磁隧道结中，铁磁自由层与铁磁参考层的磁化方向平行，第二磁隧道结呈低电阻状态。A write current along a first direction is passed through the heavy metal layer to make the magnetoresistive memory cell present a first storage state; the first storage The state is: the first magnetic tunnel junction is in a high resistance state, and the second magnetic tunnel junction is in a low resistance state. For example, when the magnetization directions of the ferromagnetic reference layers of the first magnetic tunnel junction and the second magnetic tunnel junction are both along the +x direction (that is, the magnetization component of the ferromagnetic reference layer along the x-axis is positive), and the first direction is the +x direction, the magnetization direction of the first magnetic tunnel junction is along the -x direction, and the magnetization direction of the second magnetic tunnel junction is along the +x direction. At this time, in the first magnetic tunnel junction, the magnetization directions of the ferromagnetic free layer and the ferromagnetic reference layer are antiparallel, and the first magnetic tunnel junction is in a high resistance state; in the second magnetic tunnel junction, the magnetization directions of the ferromagnetic free layer and the ferromagnetic reference layer are parallel, and the second magnetic tunnel junction is in a low resistance state.

或者，对重金属层通过沿第二方向的写电流，以使磁阻存储器单元呈第二存储状态；第二存储状态为：第一磁隧道结呈低电阻状态，第二磁隧道结呈高电阻状态；其中，第一方向和所述第二方向相反。Alternatively, a write current is passed through the heavy metal layer along a second direction so that the magnetoresistive memory unit is in a second storage state; the second storage state is: the first magnetic tunnel junction is in a low resistance state, and the second magnetic tunnel junction is in a high resistance state; wherein the first direction is opposite to the second direction.

例如，当第一磁隧道结和第二磁隧道结的铁磁参考层方向均沿+x方向时，且第一方向为-x方向时，第一磁隧道结的磁化方向为沿+x方向，第二磁隧道结的磁化方向为沿-x方向。此时，第一磁隧道结中，铁磁自由层与铁磁参考层的磁化方向平行，第一磁隧道结呈低电阻状态；第二磁隧道结中，铁磁自由层与铁磁参考层的磁化方向反平行，第二磁隧道结呈高电阻状态。For example, when the directions of the ferromagnetic reference layers of the first magnetic tunnel junction and the second magnetic tunnel junction are both along the +x direction, and the first direction is the -x direction, the magnetization direction of the first magnetic tunnel junction is along the +x direction, and the magnetization direction of the second magnetic tunnel junction is along the -x direction. At this time, in the first magnetic tunnel junction, the magnetization directions of the ferromagnetic free layer and the ferromagnetic reference layer are parallel, and the first magnetic tunnel junction is in a low resistance state; in the second magnetic tunnel junction, the magnetization directions of the ferromagnetic free layer and the ferromagnetic reference layer are antiparallel, and the second magnetic tunnel junction is in a high resistance state.

根据本公开的实施例，通过多个晶体管和磁阻存储器单元制备的3T2SOT-MTJ单元结构，通过多个晶体管使得磁阻存储器单元的读操作的电路和写操作的电路实现独立调控，基于该特性可以实现1R1W(一读一写)双端口存储阵列，可极大改善读写效率，提高磁阻存储器单元并行度。According to the embodiments of the present disclosure, a 3T2SOT-MTJ unit structure is prepared by multiple transistors and magnetoresistive memory units. The multiple transistors enable the read operation circuit and the write operation circuit of the magnetoresistive memory unit to be independently regulated. Based on this characteristic, a 1R1W (one read and one write) dual-port storage array can be realized, which can greatly improve the read and write efficiency and increase the parallelism of the magnetoresistive memory units.

图3示意性示出了根据本公开实施例的磁阻存储器单元的制备流程示意图。FIG. 3 schematically shows a schematic diagram of a preparation process of a magnetoresistive memory unit according to an embodiment of the present disclosure.

如图3所示，磁阻存储器单元的制备方法包括：As shown in FIG3 , the method for preparing a magnetoresistive memory unit includes:

对硬掩膜后的初始薄膜进行图形化处理，得到图形化后的薄膜，其中，所述初始薄膜用于生成第一磁隧道结和第二磁隧道结；Performing patterning on the initial thin film behind the hard mask to obtain a patterned thin film, wherein the initial thin film is used to generate a first magnetic tunnel junction and a second magnetic tunnel junction;

对所述图形化后的薄膜进行刻蚀，得到初始的存储器单元，其中，所述初始的存储器单元包括所述第一磁隧道结和所述第二磁隧道结，所述第一磁隧道结和所述第二磁隧道结分别与所述初始薄膜呈第一预设夹角和第二预设夹角；Etching the patterned thin film to obtain an initial memory cell, wherein the initial memory cell includes the first magnetic tunnel junction and the second magnetic tunnel junction, and the first magnetic tunnel junction and the second magnetic tunnel junction are respectively at a first preset angle and a second preset angle with the initial thin film;

在所述初始的存储器单元的顶面生长重金属层；growing a heavy metal layer on a top surface of the initial memory cell;

分别在所述重金属层的顶面和所述初始的存储器单元的底面生长顶电极和底电极，得到所述磁阻存储器单元。A top electrode and a bottom electrode are grown on the top surface of the heavy metal layer and the bottom surface of the initial memory cell respectively to obtain the magnetoresistive memory cell.

根据本公开的实施例，所述初始薄膜是将钉扎层、铁磁参考层、势垒层和铁磁自由层依次进行堆叠生成的；According to an embodiment of the present disclosure, the initial film is generated by stacking a pinned layer, a ferromagnetic reference layer, a barrier layer and a ferromagnetic free layer in sequence;

根据本公开的实施例，如图3所示，所述对所述图形化后的薄膜进行刻蚀，得到初始的存储器单元，包括：According to an embodiment of the present disclosure, as shown in FIG3, the patterned film is etched to obtain an initial A memory unit comprising:

对所述图形化后的薄膜进行第一次刻蚀，刻蚀至绝缘衬底，得到有效器件区域；Performing a first etching on the patterned thin film, etching to the insulating substrate, to obtain an effective device area;

对上述有效器件区域进行第二次刻蚀，刻蚀至底电极处，得到磁隧道结，上述磁隧道结包括第一磁隧道结和第二磁隧道结，所述初始的存储器单元包括所述磁隧道结。The effective device region is etched a second time, and the etching is performed to the bottom electrode to obtain a magnetic tunnel junction, wherein the magnetic tunnel junction includes a first magnetic tunnel junction and a second magnetic tunnel junction, and the initial memory unit includes the magnetic tunnel junction.

根据本公开的实施例，如图3所示，所述对所述图形化后的薄膜进行刻蚀，得到初始的存储器单元，还包括：According to an embodiment of the present disclosure, as shown in FIG3 , etching the patterned thin film to obtain an initial memory cell further includes:

在所述有效器件区域上生长绝缘保护层，得到绝缘的磁隧道结；Growing an insulating protective layer on the effective device region to obtain an insulating magnetic tunnel junction;

对所述绝缘的磁隧道结进行抛光处理，得到抛光后的磁隧道结；Polishing the insulated magnetic tunnel junction to obtain a polished magnetic tunnel junction;

对所述抛光后的磁隧道结进行硬掩膜图形化处理，得到图形化后的磁隧道结，以对所述图形化后的磁隧道结进行第二次刻蚀，得到过渡的存储器单元；Performing hard mask patterning on the polished magnetic tunnel junction to obtain a patterned magnetic tunnel junction, and performing a second etching on the patterned magnetic tunnel junction to obtain a transitional memory unit;

在所述过渡的存储器单元上生长绝缘保护层，得到绝缘的存储器单元；growing an insulating protection layer on the transitional memory cell to obtain an insulating memory cell;

对所述绝缘的存储器单元进行抛光处理，得到所述初始的存储器单元。The insulated memory cell is polished to obtain the initial memory cell.

图4示意性示出了根据本公开实施例的阵列电路的结构示意图。图5示意性示出了根据本公开实施例的3T2SOT-MTJ单元结构的结构示意图。Fig. 4 schematically shows a schematic diagram of the structure of an array circuit according to an embodiment of the present disclosure. Fig. 5 schematically shows a schematic diagram of the structure of a 3T2SOT-MTJ unit structure according to an embodiment of the present disclosure.

如图4所示，基于磁阻存储器单元的阵列电路，包括：As shown in FIG4 , the array circuit based on the magnetoresistive memory cell includes:

竖直间隔排列的多个线组，每个线组包括写字线WBLn、间隔一预设距离的第一读字线RBLn和第二读字线/RBLn以及源线SLn；A plurality of line groups arranged vertically and spaced apart, each line group comprising a write word line WBLn, a first read word line RBLn and a second read word line /RBLn spaced apart by a preset distance, and a source line SLn;

水平间隔排列的多个位线组，其中，所述位线组包括从上到下水平排列的写控制位线WWLn和读控制位线RWLn，一个所述位线组中的写控制位线和读控制位线、每个所述线组内的所述第一读字线和所述第二读字线围成一放置区域；A plurality of bit line groups arranged horizontally at intervals, wherein the bit line groups include write control bit lines WWLn and read control bit lines RWLn arranged horizontally from top to bottom, and the write control bit lines and read control bit lines in one bit line group, the first read word lines and the second read word lines in each line group form a placement area;

多个磁阻存储器单元，每个所述放置区域中设置一个所述磁阻存储器单元；A plurality of magnetoresistive memory cells, one magnetoresistive memory cell being arranged in each of the placement areas;

其中，所述磁阻存储器单元和对应于所述放置区域的所述线组和所述位线的连接方式包括：The connection method of the magnetoresistive memory unit, the line group corresponding to the placement area, and the bit line includes:

重金属层的一端通过第一晶体管分别与所述写控制位线和所述写字线连接，另一端与所述源线连接；One end of the heavy metal layer is connected to the write control bit line and the write word line respectively through the first transistor, and the other end is connected to the source line;

第一磁隧道结通过第二晶体管分别与所述第一读字线和所述读控制位线连接，第二磁隧道结通过第三晶体管分别与所述第二读字线和所述读控制位线连接。The first magnetic tunnel junction is connected to the first read word line and the read control bit line respectively through the second transistor, and the second magnetic tunnel junction is connected to the second read word line and the read control bit line respectively through the third transistor.

根据本公开的实施例，所述第一晶体管的源极和漏极分别与所述重金属层、所述写字线连接，所述第一晶体管的栅极与所述写控制位线连接；According to an embodiment of the present disclosure, the source and drain of the first transistor are connected to the heavy metal layer and the write word line respectively, and the gate of the first transistor is connected to the write control bit line;

所述第二晶体管的源极和漏极分别与所述第一磁隧道结、所述第一读字线连接，所述第二晶体管的栅极与所述读控制位线连接； The source and drain of the second transistor are connected to the first magnetic tunnel junction and the first read word line respectively, and the gate of the second transistor is connected to the read control bit line;

所述第三晶体管的源极和漏极分别与所述第二磁隧道结、所述第二读字线连接，所述第三晶体管的栅极与所述读控制位线连接。A source and a drain of the third transistor are connected to the second magnetic tunnel junction and the second read word line respectively, and a gate of the third transistor is connected to the read control bit line.

根据本公开的实施例，阵列电路是根据多个如图5所示的3T2SOT-MTJ单元结构构建的，3T2SOT-MTJ单元结构包括第一晶体管T1、第二晶体管T2、第三晶体管T3和磁阻存储器单元。第一晶体管T1连接重金属层横向上的第一端，重金属层横向上的第二端作为输入端或输出端。第二晶体管T2连接第一磁隧道结远离重金属层的一侧，第三晶体管T3连接第二磁隧道结远离重金属层的一侧。第二晶体管T2和第三晶体管T3的漏极还分别连接到第一读字线RBL和第二读字线/RBL，字线用于提供读电流。According to an embodiment of the present disclosure, an array circuit is constructed based on a plurality of 3T2SOT-MTJ unit structures as shown in FIG5, and the 3T2SOT-MTJ unit structure includes a first transistor T1, a second transistor T2, a third transistor T3 and a magnetoresistive memory unit. The first transistor T1 is connected to the first end of the heavy metal layer in the lateral direction, and the second end of the heavy metal layer in the lateral direction is used as an input end or an output end. The second transistor T2 is connected to the side of the first magnetic tunnel junction away from the heavy metal layer, and the third transistor T3 is connected to the side of the second magnetic tunnel junction away from the heavy metal layer. The drains of the second transistor T2 and the third transistor T3 are also connected to the first read word line RBL and the second read word line /RBL, respectively, and the word lines are used to provide a read current.

第二晶体管T2和第三晶体管T3的栅极连接到读控制位线RWL。读控制位线用于提供控制第二晶体管T2和第三晶体管T3导通或截止的信号。第一晶体管T1漏极连接到写字线WBL上。第一晶体管T1的栅极接写控制位线WWL。写控制位线用于提供控制第一晶体管T1导通或截止的信号。重金属层的第二端作为输入或输出端可通过连接源线SL实现。The gates of the second transistor T2 and the third transistor T3 are connected to the read control bit line RWL. The read control bit line is used to provide a signal for controlling the second transistor T2 and the third transistor T3 to be turned on or off. The drain of the first transistor T1 is connected to the write word line WBL. The gate of the first transistor T1 is connected to the write control bit line WWL. The write control bit line is used to provide a signal for controlling the first transistor T1 to be turned on or off. The second end of the heavy metal layer can be realized as an input or output end by connecting to the source line SL.

根据本公开的实施例，磁阻存储器单元可实现基于3T2SOT-MTJ(3个晶体管，2个自旋轨道矩的磁隧道结)的1R1W(一读一写)双端口存储阵列，可以分块同时读写，极大改善读写效率，提高存储单元并行度。According to the embodiments of the present disclosure, the magnetoresistive memory unit can realize a 1R1W (one read and one write) dual-port storage array based on 3T2SOT-MTJ (3 transistors, 2 spin-orbit moment magnetic tunnel junctions), which can read and write simultaneously in blocks, greatly improving the read and write efficiency and increasing the parallelism of the storage unit.

图6示意性示出了根据本公开实施例的阵列电路的仿真结果示意图。FIG. 6 schematically shows a simulation result diagram of an array circuit according to an embodiment of the present disclosure.

根据本公开的实施例，构建的如图4所示的阵列电路在同一个时钟周期内，可以实现对第一行第一列(1，1)3T2SOT-MTJ单元结构的写操作和对第n行第2列(n，2)3T2SOT-MTJ单元结构的读操作，其仿真结果如图6所示。由图4和图6可知，通过第一晶体管T1、第二晶体管T2和第三晶体管T3，可使磁阻存储器单元的读操作的电路和写操作的电路实现独立调控，基于该特性可以实现1R1W(一读一写)双端口存储阵列，可极大改善读写效率，提高磁阻存储器单元并行度。According to the embodiment of the present disclosure, the array circuit as shown in FIG4 can realize the write operation of the first row and first column (1, 1) 3T2SOT-MTJ cell structure and the read operation of the nth row and second column (n, 2) 3T2SOT-MTJ cell structure in the same clock cycle, and the simulation results are shown in FIG6. As can be seen from FIG4 and FIG6, the circuit of the read operation and the circuit of the write operation of the magnetoresistive memory cell can be independently regulated by the first transistor T1, the second transistor T2 and the third transistor T3. Based on this characteristic, a 1R1W (one read and one write) dual-port memory array can be realized, which can greatly improve the read and write efficiency and increase the parallelism of the magnetoresistive memory cell.

表1
Table 1

根据本公开的实施例，如表1中的操作表所示：在进行写入时，可将写控制位线的电平拉高，读控制位线的电平拉低，使得第二晶体管T2和第三晶体管T1关断，第一晶体管T1导通。然后，根据需要写入的信息(0/1)，将写字线的电平拉升至V_write(0)，源线电平相应设置为0(V_write)，在第一晶体管T1漏极和源线之间形成流经重金属层的电流通路，重金属层通过自旋霍尔效应或Rashaba-Edelstein效应将沿x轴的电流转化为自旋沿y轴极化的自旋流。自旋流沿z轴注入铁磁自由层产生自旋轨道矩使铁磁自由层磁化翻转，实现信息写入；写入过程仅需一步即可完成，写入效率高、速度快。According to an embodiment of the present disclosure, as shown in the operation table in Table 1: when writing, the level of the write control bit line can be The voltage level of the read control bit line is pulled high, and the voltage level of the read control bit line is pulled low, so that the second transistor T2 and the third transistor T1 are turned off, and the first transistor T1 is turned on. Then, according to the information to be written (0/1), the voltage level of the write word line is pulled up to V _write (0), and the voltage level of the source line is correspondingly set to 0 (V _write ), and a current path flowing through the heavy metal layer is formed between the drain and the source line of the first transistor T1. The heavy metal layer converts the current along the x-axis into a spin current polarized along the y-axis through the spin Hall effect or the Rashaba-Edelstein effect. The spin current is injected into the ferromagnetic free layer along the z-axis to generate a spin-orbit torque to flip the magnetization of the ferromagnetic free layer, thereby realizing information writing; the writing process can be completed in only one step, with high writing efficiency and fast speed.

根据本公开的实施例，对磁阻存储器单元进行读操作时，可控制写控制位线的电平拉低，读控制位线的电平拉高，使得第二晶体管T2和第三晶体管T3导通，第一晶体管T1关断；同时，将源线接低电平。于是，在第一读字线与源线之间形成流经第一磁隧道结的电流通路，在第二读字线与源线之间形成流经第二磁隧道结的电流通路，第一读字线和第二读字线上的电流可送入电流型灵敏放大器中比较读出存储单元存储状态。According to the embodiments of the present disclosure, when performing a read operation on a magnetoresistive memory cell, the level of the write control bit line can be controlled to be pulled low, and the level of the read control bit line can be pulled high, so that the second transistor T2 and the third transistor T3 are turned on, and the first transistor T1 is turned off; at the same time, the source line is connected to a low level. Thus, a current path flowing through the first magnetic tunnel junction is formed between the first read word line and the source line, and a current path flowing through the second magnetic tunnel junction is formed between the second read word line and the source line. The currents on the first read word line and the second read word line can be sent to a current-type sense amplifier to compare and read out the storage state of the storage cell.

图7示意性示出了根据本公开实施例的二值神经网络芯片的结构示意图。FIG7 schematically shows a schematic diagram of the structure of a binary neural network chip according to an embodiment of the present disclosure.

如图7所示，二值神经网络芯片包括：解码单元、缓存单元、指令存储单元、存算单元、数据处理单元和时钟单元；As shown in FIG7 , the binary neural network chip includes: a decoding unit, a cache unit, an instruction storage unit, a storage and calculation unit, a data processing unit and a clock unit;

其中，所述存算单元包括由阵列电路构建的突触阵列，所述阵列电路包括多列磁阻存储器单元组，每列所述磁阻存储器单元组包括多个磁阻存储器单元，每列所述磁阻存储器单元组被构造成存储一个神经元的突触权值。Wherein, the storage and computing unit includes a synaptic array constructed by an array circuit, the array circuit includes multiple columns of magnetoresistive memory cell groups, each column of the magnetoresistive memory cell group includes multiple magnetoresistive memory cells, and each column of the magnetoresistive memory cell group is constructed to store the synaptic weight of a neuron.

根据本公开的实施例，图7展示了一种基于磁阻存储器单元的3T2SOT-MTJ存算单元的二值神经网络芯片，该芯片可用于语音识别，3T2SOT-MTJ存算单元中的突触阵列能够实现突触权值存储、更新以及逐位运算。每列灵敏放大器的输出作为该层神经元的输出，送入下一层。According to an embodiment of the present disclosure, FIG7 shows a binary neural network chip based on a 3T2SOT-MTJ storage unit of a magnetoresistive memory unit, which can be used for speech recognition. The synaptic array in the 3T2SOT-MTJ storage unit can realize synaptic weight storage, update and bit-by-bit operation. The output of each column of sensitive amplifiers is used as the output of the neurons in this layer and sent to the next layer.

图8示意性示出了根据本公开实施例的磁阻存储器单元的存储状态和突触权值的对应关系示意图。FIG. 8 schematically shows a schematic diagram of the correspondence between the storage state of a magnetoresistive memory unit and a synaptic weight according to an embodiment of the present disclosure.

根据本公开的实施例，针对每列所述磁阻存储器单元组，在所述磁阻存储器单元的第一磁隧道结的读电流大于所述磁阻存储器单元的的读电流的情况下，确定所述磁阻存储器单元的突触权值为正的目标数值；According to an embodiment of the present disclosure, for each column of the magnetoresistive memory cell group, when the read current of the first magnetic tunnel junction of the magnetoresistive memory cell is greater than the read current of the magnetoresistive memory cell, the synaptic weight of the magnetoresistive memory cell is determined to be a positive target value;

在所述磁阻存储器单元的第一磁隧道结的读电流小于所述磁阻存储器单元的的读电流的情况下，确定所述磁阻存储器单元的突触权值为负的目标数值；When the read current of the first magnetic tunnel junction of the magnetoresistive memory cell is less than the read current of the magnetoresistive memory cell, determining a target value of a negative synaptic weight of the magnetoresistive memory cell;

在多个所述磁阻存储器单元的突触权值之和为正数的情况下，所述神经元输出第一数值；When the sum of the synaptic weights of the plurality of magnetoresistive memory units is a positive number, the neuron outputs a first value;

在多个所述磁阻存储器单元的突触权值之和为负数的情况下，所述神经元输出第二数值。When the sum of the synaptic weights of the plurality of magnetoresistive memory cells is a negative number, the neuron outputs a second value.

根据本公开的实施例，目标数值可以根据实际需求具体设置，例如可以为1。 According to an embodiment of the present disclosure, the target value may be specifically set according to actual needs, for example, it may be 1.

根据本公开的实施例，二值神经网络芯片的存算单元在读取时可以整列读取，读取的同时实现突触权值加和，存算单元的输出可以直接作为二值神经元的输出，极大提高了二值神经网络的并行度。According to the embodiments of the present disclosure, the storage and computing unit of the binary neural network chip can read the entire column when reading, and realize the addition of synaptic weights while reading. The output of the storage and computing unit can be directly used as the output of the binary neuron, which greatly improves the parallelism of the binary neural network.

根据本公开的实施例，图8展示了磁阻存储器单元的存储状态和突触权值的对应关系，可进行如下算法定义：当输入信号为0时，第二晶体管和第三晶体管截止，没有电流流过磁隧道结，此时无论第一磁隧道结和第二磁隧道结电阻如何配置，位线上的电流都为0。当输入信号为1时，第二晶体管和第三晶体管导通。规定第一磁隧道结为低电阻，第二磁隧道结为高电阻时突触权值1，对应读电流IBL>IBL_bar。规定第一磁隧道结为高电阻，第二磁隧道结为低电阻时突触权值为“-1”，对应读电流IBL<IBL_bar。According to an embodiment of the present disclosure, FIG8 shows the corresponding relationship between the storage state and the synaptic weight of the magnetoresistive memory cell, and the following algorithm definition can be performed: when the input signal is 0, the second transistor and the third transistor are turned off, and no current flows through the magnetic tunnel junction. At this time, no matter how the resistance of the first magnetic tunnel junction and the second magnetic tunnel junction is configured, the current on the bit line is 0. When the input signal is 1, the second transistor and the third transistor are turned on. When the first magnetic tunnel junction is low resistance and the second magnetic tunnel junction is high resistance, the synaptic weight is 1, corresponding to the read current IBL>IBL_bar. When the first magnetic tunnel junction is high resistance and the second magnetic tunnel junction is low resistance, the synaptic weight is "-1", corresponding to the read current IBL<IBL_bar.

在一种可替换的实施例中，可进行其他定义，例如，IBL>IBL_bar对应突触权值为“-1”，IBL<IBL_bar时对应突触权值为“1”，不作限制。读取时多行读控制线同时激活，整列读取。在阵列结构中，每列磁阻存储器单元共用一条源线和一个灵敏放大器，进行读操作时，以列为单位读取。第一读字线或第二读字线上的读电流主要由低阻状态的磁阻存储器单元产生的读电流为主。因此，第一读字线的电流IBL_bar与第二读字线的电流/IBL_bar的差，反映出两列字线中低阻状态的磁阻存储器单元数量的差值。也即，对应于一列上磁阻存储器单元对应突触权值的加和。对于每个神经元而言，灵敏放大器的输出可直接作为二值神经元的输出，可定义权值加和为正时输出“1”，反之为负时输出“0”。In an alternative embodiment, other definitions can be made, for example, when IBL>IBL_bar, the corresponding synaptic weight is "-1", and when IBL<IBL_bar, the corresponding synaptic weight is "1", without limitation. When reading, multiple rows of read control lines are activated at the same time, and the entire column is read. In the array structure, each column of magnetoresistive memory cells shares a source line and a sense amplifier, and when performing a read operation, the reading is performed in columns. The read current on the first read word line or the second read word line is mainly composed of the read current generated by the magnetoresistive memory cells in the low resistance state. Therefore, the difference between the current IBL_bar of the first read word line and the current /IBL_bar of the second read word line reflects the difference in the number of magnetoresistive memory cells in the low resistance state in the two columns of word lines. That is, it corresponds to the sum of the synaptic weights corresponding to the magnetoresistive memory cells on one column. For each neuron, the output of the sense amplifier can be directly used as the output of the binary neuron, and it can be defined that when the sum of the weights is positive, the output is "1", and when it is negative, the output is "0".

以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。本公开的范围由所附权利要求及其等同物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。 The embodiments of the present disclosure are described above. However, these embodiments are only for the purpose of illustration and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

A magnetoresistive memory cell, comprising:

a heavy metal layer configured to input a write current;

A first magnetic tunnel junction is disposed on one side of the bottom surface of the heavy metal layer, wherein the easy axis of the first magnetic tunnel junction forms a first preset angle with the input direction of the write current;

A second magnetic tunnel junction is disposed on the other side of the bottom surface of the heavy metal layer, wherein the easy axis of the second magnetic tunnel junction forms a second preset angle with the input direction of the write current;

The first magnetic tunnel junction and the second magnetic tunnel junction are configured to input a read current.

The magnetoresistive memory cell according to claim 1, wherein the first preset angle is complementary to the second preset angle, and the first preset angle ranges from 10° to 60°.

The magnetoresistive memory cell according to claim 1, wherein any one of the first magnetic tunnel junction and the second magnetic tunnel junction comprises:

bottom electrode;

a pinning layer disposed on a top surface of the bottom electrode, wherein the pinning layer is configured to fix a magnetization direction of the ferromagnetic reference layer;

The ferromagnetic reference layer is disposed on the top surface of the pinned layer;

A barrier layer, disposed on the top surface of the ferromagnetic reference layer;

A ferromagnetic free layer, disposed on the top surface of the barrier layer;

Wherein, the pinning layer comprises:

an antiferromagnetic layer or a synthetic ferrimagnetic layer or a synthetic antiferromagnetic layer, arranged on the top surface of the bottom electrode;

A space layer is arranged on the top surface of the antiferromagnetic layer or the synthetic ferrimagnetic layer or the synthetic antiferromagnetic layer, wherein the space layer is constructed to couple the magnetization directions of the ferromagnetic reference layer and the antiferromagnetic layer or the synthetic ferrimagnetic layer or the synthetic antiferromagnetic layer.

A method for preparing a magnetoresistive memory unit, comprising:

Performing patterning on the initial thin film behind the hard mask to obtain a patterned thin film, wherein the initial thin film is used to generate a first magnetic tunnel junction and a second magnetic tunnel junction;

Etching the patterned thin film to obtain an initial memory cell, wherein the initial memory cell includes the first magnetic tunnel junction and the second magnetic tunnel junction, and the first magnetic tunnel junction and the second magnetic tunnel junction are respectively at a first preset angle and a second preset angle with the initial thin film;

growing a heavy metal layer on a top surface of the initial memory cell;

A top electrode and a bottom electrode are grown on the top surface of the heavy metal layer and the bottom surface of the initial memory cell respectively to obtain the magnetoresistive memory cell.

The preparation method according to claim 4, wherein the initial film is generated based on a pinned layer, a ferromagnetic reference layer, a barrier layer and a ferromagnetic free layer;

The etching of the patterned thin film to obtain an initial memory cell includes:

Performing a first etching on the patterned thin film, etching to the insulating substrate, to obtain an effective device area;

The effective device region is etched for the second time, and the etching is performed to the bottom electrode to obtain a magnetic tunnel junction, wherein the magnetic tunnel junction includes a first magnetic tunnel junction and a second magnetic tunnel junction, and the initial memory unit includes the magnetic tunnel junction.

The preparation method according to claim 5, wherein the etching of the patterned thin film to obtain an initial memory cell further comprises:

Growing an insulating protective layer on the effective device region to obtain an insulating magnetic tunnel junction;

Polishing the insulated magnetic tunnel junction to obtain a polished magnetic tunnel junction;

Performing hard mask patterning on the polished magnetic tunnel junction to obtain a patterned magnetic tunnel junction, and performing a second etching on the patterned magnetic tunnel junction to obtain a transitional memory unit;

growing an insulating protection layer on the transitional memory cell to obtain an insulating memory cell;

The insulated memory cell is polished to obtain the initial memory cell.

An array circuit based on a magnetoresistive memory cell, comprising:

A plurality of line groups arranged vertically and spaced apart, each line group comprising a write word line, a first read word line and a second read word line spaced apart by a preset distance, and a source line;

A plurality of bit line groups arranged horizontally and spaced apart, wherein the bit line groups include write control bit lines and read control bit lines arranged horizontally from top to bottom, and the write control bit lines and read control bit lines in one of the bit line groups, the first read word lines and the second read word lines in each of the line groups form a placement area;

A plurality of magnetoresistive memory units according to any one of claims 1 to 3 or a plurality of magnetoresistive memory units prepared by the preparation method according to any one of claims 4 to 6, wherein one magnetoresistive memory unit is arranged in each of the placement areas;

Wherein, the connection method of the magnetoresistive memory unit and the line group corresponding to the placement area and the bit line includes:

One end of the heavy metal layer is connected to the write control bit line and the write word line respectively through the first transistor, and the other end is connected to the source line;

The first magnetic tunnel junction is connected to the first read word line and the read control bit line respectively through the second transistor, and the second magnetic tunnel junction is connected to the second read word line and the read control bit line respectively through the third transistor.

The array circuit according to claim 7, wherein the source and drain of the first transistor are respectively connected to the heavy The metal layer and the write word line are connected, and the gate of the first transistor is connected to the write control bit line;

The source and drain of the second transistor are connected to the first magnetic tunnel junction and the first read word line respectively, and the gate of the second transistor is connected to the read control bit line;

A source and a drain of the third transistor are connected to the second magnetic tunnel junction and the second read word line respectively, and a gate of the third transistor is connected to the read control bit line.

A binary neural network chip, comprising: a decoding unit, a cache unit, an instruction storage unit, a storage and calculation unit, a data processing unit and a clock unit;

Wherein, the storage and computing unit includes a synaptic array constructed by the array circuit described in claim 7 or 8, and the array circuit includes multiple columns of magnetoresistive memory cell groups, each column of the magnetoresistive memory cell group includes multiple magnetoresistive memory cells, and each column of the magnetoresistive memory cell group is constructed to store the synaptic weight of a neuron.

The binary neural network chip according to claim 9, wherein, for each column of the magnetoresistive memory cell group, when the read current of the first magnetic tunnel junction of the magnetoresistive memory cell is greater than the read current of the magnetoresistive memory cell, the synaptic weight of the magnetoresistive memory cell is determined to be a positive target value;

When the read current of the first magnetic tunnel junction of the magnetoresistive memory cell is less than the read current of the magnetoresistive memory cell, determining a target value of a negative synaptic weight of the magnetoresistive memory cell;

When the sum of the synaptic weights of the plurality of magnetoresistive memory units is a positive number, the neuron outputs a first value;

When the sum of the synaptic weights of the plurality of magnetoresistive memory cells is a negative number, the neuron outputs a second value.