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WO2024197772A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2024197772A1
WO2024197772A1 PCT/CN2023/085346 CN2023085346W WO2024197772A1 WO 2024197772 A1 WO2024197772 A1 WO 2024197772A1 CN 2023085346 W CN2023085346 W CN 2023085346W WO 2024197772 A1 WO2024197772 A1 WO 2024197772A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
light
scanning
emitting
signal line
Prior art date
Application number
PCT/CN2023/085346
Other languages
English (en)
French (fr)
Inventor
徐元杰
谢涛峰
柳皓笛
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2023/085346 priority Critical patent/WO2024197772A1/zh
Publication of WO2024197772A1 publication Critical patent/WO2024197772A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a display substrate, comprising: a substrate and a driving structure layer disposed on the substrate, wherein the substrate comprises a display area and a non-display area, the driving structure layer comprises: a plurality of pixel circuits located in the display area and a gate driving circuit and an electrostatic discharge circuit located in the non-display area, the gate driving circuit being configured to provide a driving signal to the pixel circuit, the gate driving circuit comprising a plurality of driving circuits, the plurality of driving circuits and the electrostatic discharge circuit being arranged in a direction close to the display area;
  • the electrostatic discharge circuit is arranged between two adjacent driving circuits and is electrically connected to at least one signal line of any one of the two adjacent driving circuits.
  • the electrostatic discharge circuit includes at least: a first release transistor and a second release transistor;
  • the gate electrode and the second electrode of the first release transistor are connected to the first signal terminal, and the first electrode of the first release transistor is connected to the second signal terminal;
  • the gate electrode and the first electrode of the second release transistor are connected to the third signal terminal, and the second electrode of the second release transistor is connected to the first signal terminal.
  • the plurality of driving circuits include: a light emitting driving circuit and a scanning driving circuit, wherein the scanning driving circuit is located on a side of the light emitting driving circuit close to the display area;
  • the driving structure layer further includes: a light-emitting initial signal line, a first light-emitting clock signal line, a second light-emitting clock signal line, a first light-emitting power line, a second light-emitting power line, a scanning initial signal line, a first scanning clock signal line, a second scanning clock signal line, a first scanning power line, and a second scanning power line located in the non-display area; any one of the light-emitting initial signal line, the first light-emitting clock signal line, the second light-emitting clock signal line, the first light-emitting power line, the second light-emitting power line, the scanning initial signal line, the first scanning clock signal line, the second scanning clock signal line, the first scanning power line, and the second scanning power line extends along the first direction;
  • the light-emitting driving circuit is electrically connected to the light-emitting initial signal line, the first light-emitting clock signal line, the second light-emitting clock signal line, the first light-emitting power line and the second light-emitting power line respectively;
  • the scanning driving circuit is electrically connected to the scanning initial signal line, the second scanning clock signal line, the first scanning clock signal line, the first scanning power line and the second scanning power line respectively;
  • the light-emission initial signal line, the first light-emission clock signal line, the second light-emission clock signal line, the A light-emitting power line, the second light-emitting power line, the first scanning power line, the first scanning clock signal line, the second scanning clock signal line, the scanning initial signal line and the second scanning power line are arranged in sequence along a direction close to the display area.
  • an orthographic projection of the electrostatic discharge circuit on the substrate partially overlaps the first scanning power line and the second light emitting power line, and at least a portion of the electrostatic discharge circuit is located between the second light emitting power line and the first scanning power line.
  • the driving structure layer further includes: a light emitting output signal line and a scanning output signal line located in the non-display area, and a light emitting signal line and a scanning signal line at least partially located in the display area; any one of the scanning output signal line, the light emitting signal line and the scanning signal line at least partially extends along a second direction, and the first direction intersects the second direction; the pixel circuit is connected to the light emitting signal line and the scanning signal line, respectively;
  • the light-emitting driving circuit comprises: a plurality of cascaded light-emitting shift registers, and the scanning driving circuit comprises: a plurality of cascaded scanning shift registers;
  • the light-emitting output signal line is electrically connected to the light-emitting shift register and at least one light-emitting signal line respectively;
  • the scan output signal lines are electrically connected to the scan shift register and the scan signal lines respectively.
  • the first signal terminal of the electrostatic discharge circuit is electrically connected to the light output signal line
  • the second signal terminal of the electrostatic discharge circuit is electrically connected to the second light power line
  • the third signal terminal of the electrostatic discharge circuit is electrically connected to the first scanning power line.
  • a distance between the second light emitting power line and the first scanning power line is about 8 micrometers to 15 micrometers.
  • the light emitting shift register includes a plurality of light emitting transistors and a plurality of light emitting capacitors
  • the scanning shift register includes a plurality of scanning transistors and a plurality of scanning capacitors
  • the light emitting capacitors and the scanning capacitors each include a first electrode plate and a second electrode plate
  • the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence
  • the first scanning clock signal line includes: a first sub-clock signal line and a second sub-clock signal line electrically connected to each other
  • the second scanning clock signal line includes: a third sub-clock signal line and a fourth sub-clock signal line electrically connected to each other;
  • the semiconductor layer includes at least: an active layer of a plurality of light emitting transistors, an active layer of a plurality of scanning transistors, an active layer of a first release transistor, and an active layer of a second release transistor;
  • the first conductive layer at least includes: a light-emitting signal line, a scanning signal line, gate electrodes of a plurality of light-emitting transistors, first plates of a plurality of light-emitting capacitors, gate electrodes of a plurality of scanning transistors, first plates of a plurality of scanning capacitors, a gate electrode of a first release transistor, and a gate electrode of a second release transistor;
  • the second conductive layer at least includes: a plurality of second plates of light-emitting capacitors, a plurality of second plates of scanning capacitors, a scanning output signal line and a light-emitting output signal line;
  • the third conductive layer at least includes: a light-emitting initial signal line, a first light-emitting clock signal line, a second light-emitting clock signal line, a first light-emitting power line, a second light-emitting power line, a scan initial signal line, a first sub-clock signal line of the first scan clock signal line, a third sub-clock signal line of the second scan clock signal line, a first scan power line and a second scan power line, first electrodes and second electrodes of a plurality of light-emitting transistors, first electrodes and second electrodes of a plurality of scan transistors, first electrodes and second electrodes of a first release transistor, and first electrodes and second electrodes of a second release transistor;
  • the fourth conductive layer includes at least: a second sub-clock signal line of the first scanning clock signal line and a fourth sub-clock signal line of the second scanning clock signal line.
  • the first and second electrodes of the plurality of light emitting transistors are located between the first light emitting power line and the second light emitting power line, and the first and second electrodes of the first release transistor are connected to the first and second electrodes of the second release transistor.
  • the first and second electrodes of some scanning transistors are located between the scanning initial signal line and the second scanning power line, and the first and second electrodes of another part of the scanning transistors can be located on the side of the second scanning power line close to the display area.
  • At least one of the light emitting output signal lines comprises: an output connection portion and at least one output line, the output connection portion extending along a first direction, and the at least one output line arranged along the first direction;
  • the output connection part is electrically connected to the light emitting shift register and at least one output line respectively.
  • the output line corresponds to the light emitting signal line connected to the light emitting output signal line one by one and is electrically connected to the corresponding light emitting signal line.
  • the output line includes: an output main body portion extending at least partially along the second direction and an output connection portion extending along the first direction, the output main body portion being electrically connected to the output connection portion;
  • the second electrode of the first release transistor and the second electrode of the second release transistor are an integrated structure, and the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the output connection portion on the substrate, and the integrated structure of the second electrode of the first release transistor and the second electrode of the second release transistor is electrically connected to the output connection portion.
  • the active layer of the first release transistor and the active layer of the second release transistor are an integral structure and extend along the second direction;
  • An orthographic projection of the output connection portion on the substrate does not overlap with an orthographic projection of an integrated structure of an active layer of the first release transistor and an active layer of the second release transistor on the substrate.
  • the active layer of the first release transistor and the active layer of the second release transistor are an integrated structure and include: an active body portion and an active connection portion, the active body portion and the active connection portion are electrically connected, and the active body portion and the active connection portion are arranged along a first direction;
  • the active main body portion extends along the second direction, and the active connecting portion at least partially extends along the first direction;
  • the active connection portion is in a zigzag shape.
  • the output line at least partially extends along the second direction; the second electrode of the first release transistor and the second electrode of the second release transistor are an integral structure;
  • the orthographic projection of the active connecting portion on the substrate at least partially overlaps with the orthographic projection of the second electrode of the first release transistor and the second electrode of the second release transistor and the output line on the substrate, and is electrically connected to the second electrode of the first release transistor and the second electrode of the second release transistor and the output line respectively.
  • the width of the active connection portion is smaller than the width of the active body portion.
  • the scan shift register includes: a first scan capacitor, a second electrode plate of the first scan capacitor is electrically connected to the first scan power line, and the second electrode plate of the first scan capacitor extends along the second direction;
  • the orthographic projection of the second electrode plate of the first scanning capacitor on the substrate at least partially overlaps with the orthographic projections of the first scanning power line, the second scanning power line, the first scanning clock signal line, the second scanning clock signal line and the scanning initial signal line on the substrate.
  • the display area includes: a first display area and a second display area located at least on one side of the first display area, the display substrate further includes: a light-emitting device and an anode connection line located in the display area, and the pixel circuit is electrically connected to the light-emitting device;
  • the pixel circuit includes: a first pixel circuit and a second pixel circuit located in the second display area, the light-emitting device includes: a first light-emitting device located in the first display area and a second light-emitting device located in the second display area, the first pixel circuit is electrically connected to the first light-emitting device, and the second pixel circuit is electrically connected to the second light-emitting device;
  • the orthographic projection of the first pixel circuit on the substrate at least partially overlaps with the orthographic projection of the first light-emitting device connected to the first pixel circuit on the substrate;
  • the anode connection line is electrically connected to the second light emitting device and the second pixel circuit connected to the second light emitting device respectively.
  • the driving structure layer further includes: a first power line, a data signal line, and a data connection line at least partially located in the display area; the first power line and the data signal line at least partially extend along the first direction, and the data connection line at least partially extends along the second direction;
  • the driving structure layer further includes: a fourth conductive layer and a fifth conductive layer sequentially stacked on the third conductive layer;
  • the third conductive layer at least includes: a data connection line
  • the fourth conductive layer at least includes: a first power line and a data signal line;
  • the fifth conductive layer at least includes: an anode connection line;
  • the fifth conductive layer is a transparent conductive layer.
  • the driving structure layer further includes: a flat layer located between the third conductive layer and the fourth conductive layer, the flat layer being provided with a groove;
  • the orthographic projection of the electrostatic discharge circuit on the substrate at least partially overlaps with the orthographic projection of the groove on the substrate.
  • the driving structure layer further includes: at least one initial power supply line located in the non-display area and at least one initial signal line at least partially located in the display area; the initial power supply line is located on a side of the scan driving circuit close to the display area, the initial power supply line at least partially extends along the first direction, and the initial signal line at least partially extends along the second direction; the initial power supply line includes a first sub-initial power supply line and a second sub-initial power supply line electrically connected to each other;
  • At least one initial signal line corresponds to at least one initial power supply line one by one, and the initial signal line is electrically connected to the pixel circuit and the corresponding initial power supply line respectively;
  • the second conductive layer at least includes: an initial signal line
  • the third conductive layer at least includes: a first sub-initial power supply line of the initial power supply line;
  • the fourth conductive layer at least includes: a second sub-initial power supply line of the initial power supply line.
  • the present disclosure further provides a display device, comprising: the above-mentioned display substrate and a photosensitive sensor, wherein the photosensitive sensor is located inside the display substrate.
  • FIG1 is a schematic structural diagram of a display substrate
  • FIG. 2 is another schematic diagram of a display substrate
  • FIG3A is a schematic diagram of an equivalent circuit of a pixel circuit
  • FIG3B is a working timing diagram of the pixel circuit provided in FIG3A ;
  • FIG4 is a schematic structural diagram of a display substrate
  • FIG5A is a partial schematic diagram of a display substrate provided in an embodiment of the present disclosure.
  • FIG5B is a cross-sectional view of the display substrate provided in FIG5A along the AA direction;
  • FIG6A is another partial schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG6B is a cross-sectional view of the display substrate provided in FIG6A along the A-A direction;
  • FIG7A is a schematic structural diagram of a pixel circuit
  • FIG7B is a schematic structural diagram of another pixel circuit
  • FIG7C is a schematic structural diagram of yet another pixel circuit
  • FIG8 is an equivalent circuit diagram of an electrostatic discharge circuit
  • FIG9A is an equivalent circuit diagram of a scan shift register
  • FIG9B is a timing diagram of the scan shift register provided in FIG9A ;
  • FIG10A is an equivalent circuit diagram of a light emitting shift register
  • FIG10B is a timing diagram of the light emitting shift register provided in FIG10A;
  • FIG11 is a schematic structural diagram of the semiconductor layer and the second conductive layer in FIG5A ;
  • FIG12 is a schematic structural diagram of the semiconductor layer and the second conductive layer in FIG6A;
  • FIG13 is another schematic diagram showing the structure of a display substrate
  • FIG14 is a schematic diagram of FIG5A after the semiconductor layer pattern is formed
  • FIG15 is a schematic diagram of FIG6A after the semiconductor layer pattern is formed
  • FIG16 is a schematic diagram of the first conductive layer pattern of FIG5A and FIG6A;
  • FIG17 is a schematic diagram of FIG5A after the first conductive layer pattern is formed
  • FIG18 is a schematic diagram of FIG6A after forming a first conductive layer pattern
  • FIG19 is a schematic diagram of FIG6A after forming a second insulating layer pattern
  • FIG20 is a schematic diagram of a second conductive layer pattern of FIG5A ;
  • FIG21 is a schematic diagram of FIG5A after forming a second conductive layer pattern
  • FIG22 is a schematic diagram of a second conductive layer pattern of FIG6A ;
  • FIG23 is a schematic diagram of FIG6A after forming a second conductive layer pattern
  • FIG24 is a schematic diagram of FIG5A after forming a third insulating layer pattern
  • FIG25 is a schematic diagram of FIG6A after forming a third insulating layer pattern
  • FIG26 is a schematic diagram of a third conductive layer pattern of FIG5A and FIG6A;
  • FIG27 is a schematic diagram of FIG5A after forming a third conductive layer pattern
  • FIG28 is a schematic diagram of FIG6A after forming a third conductive layer pattern
  • FIG29 is a schematic diagram of FIG5A after a planar layer pattern is formed
  • FIG30 is a schematic diagram of FIG6A after a flat layer pattern is formed
  • FIG31 is a schematic diagram of a fourth conductive layer pattern of FIG5A and FIG6A;
  • FIG32 is a schematic diagram of FIG5A after forming a fourth conductive layer pattern
  • FIG33 is a schematic diagram of FIG6A after forming a fourth conductive layer pattern
  • FIG34 is a schematic diagram of FIG7B after the semiconductor layer pattern is formed
  • FIG35 is a schematic diagram of FIG7C after the semiconductor layer pattern is formed
  • FIG36 is a schematic diagram of the first conductive layer pattern of FIG7B ;
  • FIG37 is a schematic diagram of FIG7B after the first conductive layer pattern is formed
  • FIG38 is a schematic diagram of the first conductive layer pattern of FIG7C ;
  • FIG39 is a schematic diagram of FIG7C after the first conductive layer pattern is formed
  • FIG40 is a schematic diagram of the second conductive layer pattern of FIG7B ;
  • FIG41 is a schematic diagram of FIG7B after forming a second conductive layer pattern
  • FIG42 is a schematic diagram of the second conductive layer pattern of FIG7C ;
  • FIG43 is a schematic diagram of FIG7C after forming a second conductive layer pattern
  • FIG44 is a schematic diagram of FIG7B after forming a third insulating layer pattern
  • FIG45 is a schematic diagram of FIG7C after forming a third insulating layer pattern
  • FIG46 is a schematic diagram of a third conductive layer pattern of FIG7B ;
  • FIG47 is a schematic diagram of FIG7B after forming a third conductive layer pattern
  • FIG48 is a schematic diagram of a third conductive layer pattern of 7C.
  • FIG49 is a schematic diagram of FIG7C after forming a third conductive layer pattern
  • FIG50 is a schematic diagram of FIG7B after forming a fourth insulating layer pattern
  • FIG51 is a schematic diagram of FIG7C after forming a fourth insulating layer pattern
  • FIG52 is a schematic diagram of a fourth conductive layer pattern of FIG7B ;
  • FIG53 is a schematic diagram of FIG7B after forming a fourth conductive layer pattern
  • FIG54 is a schematic diagram of the fourth conductive layer pattern of FIG7C.
  • FIG. 55 is a schematic diagram of forming a fourth conductive layer pattern in FIG. 7C .
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different.
  • the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.
  • the display substrate has the advantages of high resolution, high response speed, high brightness, high aperture ratio, etc., and has a wide range of application prospects.
  • a driving circuit is provided in the display substrate to drive the pixel circuit to emit light, thereby realizing display.
  • the shape of the display substrate is generally a rounded rectangle, and the four corners of the rounded rectangle are called the rounded corner area.
  • the driving circuit is placed in the rounded corner area according to the arc trend of the rounded corner area, which will cause some blank areas between the driving circuits. If the blank area is too large, it will cause uneven etching, affecting the stability of the output signal transmission of the driving circuit and affecting the display effect.
  • FIG. 1 is a schematic diagram of the structure of a display substrate
  • FIG. 2 is another schematic diagram of the display substrate.
  • the display substrate may include: a display area 100 and a non-display area 200.
  • the display area 100 of the display substrate may include: a first display area A1 and a second display area A2 located on at least one side of the first display area A1.
  • the first display area A1 is a light-transmitting display area
  • the first display area A1 may also be referred to as an under-screen camera (UDC, Under Display Camera) area.
  • UDC Under Display Camera
  • the second display area A2 is a non-light-transmitting display area, and the second display area A2 may also be referred to as a normal display area.
  • the orthographic projection of hardware such as a photosensitive sensor (such as a camera, an infrared sensor) on the display substrate may be located in the first display area A1 of the display substrate.
  • the first display area A1 may be circular, and the size of the orthographic projection of the light sensor on the display substrate may be less than or equal to the size of the first display area A1.
  • this embodiment is not limited to this.
  • the first display area A1 may be rectangular, and the size of the orthographic projection of the light sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area.
  • the first display area A1 may be located at the top center of the display area 100.
  • the second display area A2 may surround the first display area A1.
  • this embodiment is not limited to this.
  • the first display area A1 may be located at the upper left corner or the upper right corner of the display area 100 or other positions.
  • the display area may be a rectangle, such as a rounded rectangle.
  • the first display area A1 may be a circle or an ellipse.
  • this embodiment is not limited thereto.
  • the first display area may be a rectangle, a pentagon, a hexagon or other shapes.
  • the display substrate provided by the present disclosure can realize the large-angle bending function of the four sides, improve the module fitting wrinkle problem, and improve the product yield.
  • the display area may include: pixel units arranged in an array, at least one pixel unit includes at least three sub-pixels P, and at least one sub-pixel includes: a pixel circuit and a light-emitting device.
  • the pixel circuit located in the same sub-pixel is electrically connected to the light-emitting device and is configured to drive the light-emitting device to emit light.
  • a pixel unit may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which is not limited in the present disclosure.
  • the shape of the sub-pixels in the pixel unit may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a triangular pattern.
  • the four sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a square pattern, which is not limited in the present disclosure.
  • the light emitting device may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED), wherein the OLED may include a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • EML emitting layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the electron injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be a common layer connected together
  • the electron transport layers of all sub-pixels may be a common layer connected together
  • the hole blocking layers of all sub-pixels may be a common layer connected together
  • the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated
  • the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • the non-display area 200 may include a binding area located on one side of the display area 100 and a frame area located on the other side of the display area 100 .
  • the binding area may include a lead area, a bending area and a composite circuit area arranged in sequence along a direction away from the display area, the lead area is connected to the display area 100, the bending area is connected to the lead area, and the composite circuit area is connected to the bending area.
  • the lead area may be provided with a plurality of lead lines, one end of a portion of the plurality of lead lines is connected to a plurality of data fan-out lines in the display area 100, one end of another portion of the plurality of lead lines is connected to a plurality of data lines in the display area 100, and the other end of the plurality of lead lines crosses the bending area to connect to the integrated circuit of the composite circuit area, so that The integrated circuit applies data signals to the data lines through the lead-out lines and the data fan-out lines.
  • the bending area can be bent at a curvature, and the surface of the composite circuit area can be reversed, that is, the surface of the composite circuit area facing upward can be converted to face downward by bending the bending area.
  • the composite circuit area when the bending area is bent, can overlap with the display area 100.
  • the composite circuit area may include an anti-static area, a driving chip area and a binding pin area, an integrated circuit (IC) may be bound and connected to the driving chip area, and a flexible printed circuit (FPC) may be bound and connected to the binding pin area.
  • IC integrated circuit
  • FPC flexible printed circuit
  • the integrated circuit may generate a driving signal required for driving the sub-pixel, and may provide the driving signal to the sub-pixel in the display area 100.
  • the driving signal may be a data signal for driving the sub-pixel to emit light at a brightness.
  • the integrated circuit may be bound and connected to the driver chip area through an anisotropic conductive film or other means.
  • the binding pin area may be provided with a pad including a plurality of pins (PINs), and the flexible circuit board may be bound and connected to the pad.
  • the display substrate may include a timing controller, a data driving circuit, a gate driving circuit, and a pixel array, wherein the timing controller is connected to the data driving circuit and the gate driving circuit, respectively, the data driving circuit is connected to the data signal line Data, respectively, the gate driving circuit is connected to the gate line, and the gate line may include one or more of the light emitting signal line EM and the scanning signal line Gate.
  • the pixel circuit is connected to the gate line and the data signal line, respectively.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driving circuit to the data driving circuit, may provide a clock signal, a start signal, etc. suitable for the specifications of the gate driving circuit to the gate driving circuit, and may provide a clock signal, an emission stop signal, etc. suitable for the specifications of the light emitting driving circuit to the light emitting driving circuit.
  • the data driving circuit may generate a data voltage to be provided to the data signal line using the grayscale value and the control signal received from the timing controller. For example, the data driving circuit may sample the grayscale value using the clock signal, and apply a data voltage corresponding to the grayscale value to the data signal line in units of pixel rows.
  • the gate drive circuit can generate a scan signal to be provided to the gate line by receiving a clock signal, a start signal, etc. from a timing controller.
  • the gate drive circuit can sequentially provide a signal with a conduction level pulse to the gate line.
  • the gate drive circuit can be configured in the form of a shift register, and can sequentially transmit the start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal to generate a scan signal.
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.
  • FIG3A is a schematic diagram of an equivalent circuit of a pixel circuit.
  • the pixel circuit may include 7 transistors (first transistor M1 to seventh transistor M7), 1 capacitor C, and 8 signal lines (data signal line Data, scan signal line Gate, reset signal line Reset, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, high level power line VDD, and low level power line VSS).
  • a first plate of the capacitor C is connected to a high-level power supply line VDD, and a second plate of the capacitor C is connected to a first node N1.
  • a gate electrode of the first transistor M1 is connected to a reset signal line Reset, a first electrode of the first transistor M1 is connected to a first initial signal line INIT1, and a second electrode of the first transistor is connected to a first node N1;
  • a gate electrode of the second transistor M2 is connected to a scan signal line Gate, a first electrode of the second transistor M2 is connected to a first node N1, and a second electrode of the second transistor M2 is connected to a second node N2.
  • a gate electrode of the third transistor M3 is connected to the first node N1, a first electrode of the third transistor M3 is connected to a second node N2, and a second electrode of the third transistor M3 is connected to a third node N3.
  • a gate electrode of the fourth transistor M4 is connected to a scan signal line Gate, a first electrode of the fourth transistor M4 is connected to a data signal line Data, and a second electrode of the fourth transistor M4 is connected to a second node N2.
  • a gate electrode of the fifth transistor M5 is connected to a light-emitting signal line EM, and a first electrode of the fifth transistor M5 is connected to a The high-level power line VDD is connected, the second electrode of the fifth transistor M5 is connected to the second node N2; the gate electrode of the sixth transistor M6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the third node N3, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light-emitting device L.
  • the gate electrode of the seventh transistor M7 is connected to the reset signal line Reset or the scan signal line Gate, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light-emitting device L, and the second electrode of the light-emitting device is connected to the low-level power line VSS.
  • FIG. 3A is described by taking the gate electrode of the seventh transistor M7 and the reset signal line Reset as an example.
  • the first transistor M1 may be referred to as a node reset transistor, and when the reset signal line Reset inputs an active level signal, the first transistor M1 transmits an initialization voltage to the first node N1 to initialize the charge amount of the first node N1.
  • the second transistor M2 may be referred to as a compensation transistor, and when the control signal line SL inputs an active level signal, the second transistor M2 transmits a signal of the second node N2 to the first node N1 to compensate for the signal of the first node N1.
  • the third transistor M3 may be referred to as a driving transistor, and the third transistor M3 determines a driving current flowing between the high-level power line VDD and the low-level power line VSS according to a potential difference between the gate electrode and the first electrode.
  • the fourth transistor M4 may be referred to as a write transistor or the like, and when the scan signal line Gate inputs an active level signal, the fourth transistor M4 inputs a data voltage of the data signal line Data to the third node N3 .
  • the fifth transistor M5 and the sixth transistor M6 may be referred to as light emitting transistors.
  • the fifth transistor M5 and the sixth transistor M6 enable the light emitting device to emit light by forming a driving current path between the high level power line VDD and the low level power line VSS.
  • the seventh transistor M7 can be called an anode reset transistor.
  • the reset signal line Reset or the scan signal line Gate inputs a valid level signal
  • the seventh transistor M7 transmits an initialization voltage to the first electrode of the light emitting device L to initialize the charge amount of the first electrode of the light emitting device L.
  • the signal of the high-level power line VDD is a continuously provided high-level signal
  • the signal of the low-level power line VSS is a low-level signal
  • the transistor can be divided into an N-type transistor and a P-type transistor.
  • the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages).
  • the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).
  • the first transistor M1 to the seventh transistor M7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor M1 to the seventh transistor M7 may include a P-type transistor and an N-type transistor.
  • the first transistor M1 to the seventh transistor M7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (Low Temperature Poly-Silicon, referred to as LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • Oxide oxide semiconductor
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, referred to as LTPO) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • the first transistor T1 and the second transistor T2 may be N-type transistors, and the remaining transistors may be P-type transistors.
  • the first transistor M1 to the seventh transistor M7 may be P-type transistors.
  • FIG3B is a timing diagram of the operation of the pixel circuit provided in FIG3A.
  • FIG3B is illustrated by taking the transistors in FIG3A as an example that all the transistors are P-type transistors.
  • the following is an exemplary embodiment of the present disclosure described by the operation process of the pixel circuit illustrated in FIG3B.
  • the operation process of the pixel circuit may include:
  • the first stage A1 is called the reset stage.
  • the signals of the scanning signal line Gate and the light-emitting signal line EM are both high-level signals, and the signal of the reset signal line Reset is a low-level signal.
  • the signal of the reset signal line Reset is a high-level signal, the first transistor M1 is turned on, the signal of the first initial signal line INIT1 is provided to the first node N1, the capacitor C is initialized, and the original data voltage in the capacitor C is cleared, the seventh transistor M7 is turned on, and the initial voltage of the second initial signal line INIT2 is provided to the first electrode of the light-emitting device L, the first electrode of the light-emitting device L is initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization.
  • the signals of the scanning signal line Gate and the light-emitting signal line EM are high-level signals, the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are turned off, and the light-emitting device L does not emit light in this stage.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the scanning signal line Gate is a low-level signal
  • the signals of the light-emitting signal line EM and the reset signal line Reset are high-level signals
  • the data signal line Data outputs a data voltage.
  • the third transistor M3 is turned on.
  • the signal of the scanning signal line Gate is a low-level signal, the second transistor T2 and the fourth transistor M4 are turned on, and the second transistor M2 and the fourth transistor M4 are turned on so that the data voltage output by the data signal line Data passes through the second node N, the turned-on third transistor M3, the third node N3 and the turned-on second transistor M2 to provide to the first node N1, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vd-
  • the signal of the reset signal line Reset is a high-level signal, and the first transistor M1 is turned off.
  • the signal of the light emitting signal line EM is a high level signal, and the fifth transistor M5 and the sixth transistor M6 are turned off
  • the third stage A3 is called the light-emitting stage, the signals of the scanning signal line Gate and the reset signal line Reset are high-level signals, and the signal of the light-emitting signal line EM is a low-level signal.
  • the signal of the light-emitting signal line EM is a low-level signal, the fifth transistor M5 and the sixth transistor M6 are turned on, and the power supply voltage output by the high-level power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, driving the light-emitting device L to emit light.
  • the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-
  • )-Vth]2 K*[(Vdd-Vd]2
  • I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3
  • Vth is the threshold voltage of the third transistor M3
  • Vd is the data voltage output by the data signal line Data
  • Vdd is the power supply voltage output by the high-level power supply line VDD.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the display substrate may be an LTPO display substrate or an LTPS display substrate.
  • the gate driving circuits in the display substrate may be of two, three or more types, depending on the structure of the display substrate, which is not limited in the present disclosure.
  • Some metal conductive layers in FDC display products include multiple isolated block structures, which makes the metal conductive layer's ability to conduct static electricity poor. The inability to release static electricity will cause some transistors to burn, thereby affecting the display effect and reducing the reliability of the display substrate.
  • FIG4 is a schematic diagram of the structure of a display substrate
  • FIG5A is a partial schematic diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG5B is a cross-sectional view of FIG5A along the A-A direction
  • FIG6A is another partial schematic diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG6B is a cross-sectional view of FIG6A along the A-A direction.
  • the display substrate provided by an embodiment of the present disclosure may include: a substrate 10 and a driving structure layer arranged on the substrate 10, the substrate includes a display area 100 and a non-display area 200, the driving structure layer includes: a plurality of pixel circuits located in the display area and a gate driving circuit and an electrostatic discharge circuit ER located in the non-display area, the gate driving circuit is configured to provide a driving signal to the pixel circuit, and the gate driving circuit includes a plurality of driving circuits.
  • the plurality of driving circuits and the electrostatic discharge circuit are arranged in a direction close to the display area, the electrostatic discharge circuit ER is arranged between two adjacent driving circuits, and is electrically connected to at least one signal line of any one of the two adjacent driving circuits.
  • the display substrate may further include: a light emitting structure layer disposed on a side of the driving structure layer away from the substrate and an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate.
  • the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the driving structure layer of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel circuit, and the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode, the anode is connected to the pixel circuit through a via, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode.
  • the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.
  • the touch structure layer may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer 43 covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer.
  • the first touch metal layer may include a plurality of bridging electrodes
  • the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes
  • the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.
  • the present invention can release static electricity in the gate driving circuit by disposing the static electricity release circuit between adjacent driving circuits and electrically connected to the adjacent driving circuits, thereby improving the static electricity conduction capability of the display substrate, and improving the display effect and the reliability of the display substrate.
  • the plurality of driving circuits may include: a light-emitting driving circuit, a control driving circuit, and a scanning driving circuit arranged in sequence near the display area.
  • the control driving circuit is connected to the N-type transistor in the pixel circuit
  • the scanning driving circuit is connected to the P-type transistor in the pixel circuit.
  • the electrostatic discharge circuit may be located between the light-emitting driving circuit and the control driving circuit, and electrically connected to at least one signal line of either the light-emitting driving circuit or the control driving circuit, or the electrostatic discharge circuit may be located between the control driving circuit and the scanning driving circuit, and electrically connected to at least one signal line of either the control driving circuit or the scanning driving circuit.
  • the plurality of driving circuits may include: a light emitting driving circuit and a scanning driving circuit, and the scanning driving circuit is located on a side of the light emitting driving circuit close to the display area 100 .
  • the driving structure layer may also include: a light-emitting initial signal line ESTV, a first light-emitting clock signal line ECK1, a second light-emitting clock signal line ECK2, a first light-emitting power line EVGH, a second light-emitting power line EVGL, a scanning initial signal line GSTV, a first scanning clock signal line GCK1, a second scanning clock signal line GCK2, a first scanning power line GVGH and a second scanning power line GVGL located in a non-display area.
  • a light-emitting initial signal line ESTV a first light-emitting clock signal line ECK1, a second light-emitting clock signal line ECK2, a first light-emitting power line EVGH, a second light-emitting power line EVGL, a scanning initial signal line GSTV, a first scanning clock signal line GCK1, a second scanning clock signal line GCK2, a first scanning power line GVGH and a second scanning power line GV
  • any one of the light-emitting initial signal line ESTV, the first light-emitting clock signal line ECK1, the second light-emitting clock signal line ECK2, the first light-emitting power line EVGH, the second light-emitting power line EVGL, the scan initial signal line GSTV, the first scan clock signal line GCK1, the second scan clock signal line GCK2, the first scan power line GVGH and the second scan power line GVGL extends along the first direction D1.
  • the light emitting driving circuit may be electrically connected to a light emitting start signal line ESTV, a first light emitting clock signal line ECK1 , a second light emitting clock signal line ECK2 , a first light emitting power line EVGH, and a second light emitting power line EVGL, respectively.
  • the scan driving circuit may be electrically connected to the scan initialization signal line GSTV, the second scan clock signal line GCK2 , the first scan clock signal line GCK1 , the first scan power line GVGH, and the second scan power line GVGL, respectively.
  • At least one of the first scan clock signal line GCK1 and the second scan clock signal line GCK2 may have a double-layer structure.
  • the first scan clock signal line may include a first sub-clock signal line and a second sub-clock signal line electrically connected to each other.
  • the first sub-clock signal line and the second sub-clock signal line may be arranged in different layers.
  • the second scan clock signal line may include a third sub-clock signal line and a fourth sub-clock signal line electrically connected to each other.
  • the third sub-clock signal line and the fourth sub-clock signal line may be arranged in different layers.
  • the light-emitting initial signal line ESTV, the first light-emitting clock signal line ECK1, the second light-emitting clock signal line ECK2, the first light-emitting power line EVGH, the second light-emitting power line EVGL, the first scanning power line GVGH, the first scanning clock signal line GCK1, the second scanning clock signal line GCK2, the scanning initial signal line GSTV and the second scanning power line GVGL are arranged in sequence along the direction close to the display area.
  • signals of the first light emitting power line EVGH and the first scanning power line GVGH are high level signals
  • signals of the second light emitting power line EVGL and the second scanning power line GVGL are low level signals.
  • the positive projection of the electrostatic discharge circuit ER on the substrate partially overlaps with the first scanning power line GVGH and the second light emitting power line EVGL, and at least part of the electrostatic discharge circuit is located between the second light emitting power line EVGL and the first scanning power line GVGH.
  • FIG. 7A is a schematic diagram of a structure of a pixel circuit
  • FIG. 7B is another schematic diagram of a structure of a pixel circuit
  • FIG. 7C is another schematic diagram of a structure of a pixel circuit.
  • the driving structure layer may further include: a light output signal line EOL and a scan output signal line GOL located in a non-display area, and a light signal line EM and a scan signal line Gate located at least partially in a display area. Any one of the scan output signal line GOL, the light signal line EM, and the scan signal line Gate at least partially extends along the second direction D2, and the first direction D1 intersects the second direction D2.
  • the pixel circuits are connected to the emission signal line EM and the scanning signal line Gate, respectively.
  • the light emitting driving circuit may include: a plurality of cascaded light emitting shift registers EM-GOA
  • the scanning driving circuit may include: a plurality of cascaded scanning shift registers Gate-GOA.
  • the light output signal line EOL is electrically connected to the light shift register EM-GOA and at least one light signal line.
  • FIG5A and FIG6A illustrate the light output signal line and two light signal lines as examples.
  • the scan output signal line GOL is electrically connected to the scan shift register Gate-GOA and the scan signal line, respectively.
  • FIG8 is an equivalent circuit diagram of an electrostatic discharge circuit.
  • the electrostatic discharge circuit may include at least: a first release transistor R1 and a second release transistor R2.
  • the gate electrode and the second electrode of the first release transistor R1 are connected to the first signal terminal S1, and the first electrode of the first release transistor R1 is connected to the second signal terminal S2; the gate electrode and the first electrode of the second release transistor R2 are connected to the third signal terminal S3, and the second electrode of the second release transistor R2 is connected to the first signal terminal S1.
  • the signal at the second signal terminal S2 may be a low level signal
  • the signal at the third signal terminal S3 may be a high level signal
  • the first release transistor R1 and the second release transistor R2 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the electrostatic release circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product.
  • the first release transistor R1 and the second release transistor R2 may include a P-type transistor and an N-type transistor.
  • the first release transistor R1 and the second release transistor R2 may employ a low temperature polysilicon thin film transistor, or may employ an oxide thin film transistor, or may employ a low temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the working principle of the electrostatic discharge circuit is as follows: when the voltage value of the signal at the first signal terminal S1 is too high (for example, higher than the voltage value of the signal at the third signal terminal S3), the second release transistor R2 is turned on, and at this time, the voltage value of the signal at the first signal terminal S1 will approach the voltage value of the signal at the third signal terminal S3, and will not be too high.
  • the first release transistor R1 is turned on, and at this time, the voltage value of the signal at the first signal terminal S1 will approach the voltage value of the signal at the second signal terminal S2, and will not be too low.
  • the first signal terminal of the electrostatic discharge circuit can be electrically connected to the light output signal line EOL
  • the second signal terminal of the electrostatic discharge circuit can be electrically connected to the second light power line EVGL
  • the third signal terminal of the electrostatic discharge circuit can be electrically connected to the first scanning power line GVGH.
  • the distance between the second light emitting power line EVGL and the first scanning power line GVGH is about 8 micrometers to 15 micrometers.
  • the distance between the second light emitting power line EVGL and the first scanning power line GVGH may be 10 micrometers.
  • the pixel circuit includes: a plurality of transistors and capacitors
  • the light emitting shift register includes a plurality of light emitting transistors and a plurality of light emitting capacitors
  • the scanning shift register includes a plurality of scanning transistors and a plurality of scanning capacitors
  • the light emitting capacitors and the scanning capacitors each include a first electrode plate and a second electrode plate
  • the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence
  • the semiconductor layer may include at least active layers of a plurality of transistors, an active layer of a plurality of light emitting transistors, an active layer of a plurality of scanning transistors, an active layer of a first release transistor, and an active layer of a second release transistor.
  • the first conductive layer may include at least: a light emitting signal line, a scan signal line, gate electrodes of a plurality of transistors, gate electrodes of a plurality of light emitting transistors, a first plate of a capacitor, a first plate of a plurality of light emitting capacitors, gate electrodes of a plurality of scan transistors, a first plate of a plurality of scan capacitors, a gate electrode of a first release transistor, and a second release transistor.
  • the gate electrode of the transistor is a light emitting signal line, a scan signal line, gate electrodes of a plurality of transistors, gate electrodes of a plurality of light emitting transistors, a first plate of a capacitor, a first plate of a plurality of scan capacitors, a gate electrode of a first release transistor, and a second release transistor.
  • the second conductive layer may include at least: a second plate of a capacitor, second plates of a plurality of light emitting capacitors, second plates of a plurality of scanning capacitors, a scanning output signal line, and a light emitting output signal line.
  • the third conductive layer may include at least: a light-emitting initial signal line, a first light-emitting clock signal line, a second light-emitting clock signal line, a first light-emitting power line, a second light-emitting power line, a scan initial signal line, a first sub-clock signal line of the first scan clock signal line, a third sub-clock signal line of the second scan clock signal line, a first scan power line, a second scan power line, first and second electrodes of multiple transistors, first and second electrodes of multiple light-emitting transistors, first and second electrodes of multiple scan transistors, first and second electrodes of a first release transistor, and first and second electrodes of a second release transistor.
  • the fourth conductive layer may include at least a second sub clock signal line of the first scan clock signal line and a fourth sub clock signal line of the second scan clock signal line.
  • the first and second electrodes of a plurality of light emitting transistors are located between the first light emitting power line EVGH and the second light emitting power line EVGL
  • the first and second electrodes of the first release transistor to the first and second electrodes of the second release transistor are located between the second light emitting power line EVGL and the first scanning power line GVGH
  • the first and second electrodes of some scanning transistors are located between the scanning initial signal line GSTV and the second scanning power line GVGL
  • the first and second electrodes of another part of the scanning transistors may be located on the side of the second scanning power line GVGL close to the display area.
  • the scanning shift register may be an 8T2C circuit structure
  • the light emitting shift register may be a 10T3C or 12T3C circuit structure, which is not limited in the present disclosure.
  • Fig. 9A is an equivalent circuit diagram of a scan shift register.
  • the scan shift register may include: first to eighth scan transistors GT1 to GT8, a first scan capacitor GC1 and a second scan capacitor GC2.
  • a gate electrode of the first scanning transistor GT1 is electrically connected to the first clock signal terminal CK1, a first electrode of the first scanning transistor GT1 is electrically connected to the input terminal GIN, and a second electrode of the first scanning transistor GT1 is electrically connected to the first node N1;
  • a gate electrode of the second scanning transistor GT2 is electrically connected to the first node N1, a first electrode of the second scanning transistor GT2 is electrically connected to the first clock signal terminal CK1, and a second electrode of the second scanning transistor GT2 is electrically connected to the second node N2;
  • a gate electrode of the third scanning transistor GT3 is electrically connected to the first clock signal terminal CK1, a first electrode of the third scanning transistor GT3 is electrically connected to the second power supply terminal VGL, and a second electrode of the third scanning transistor GT3 is electrically connected to the second node N2;
  • a gate electrode of the fourth scanning transistor GT4 is electrically connected to the second node N2, a first electrode of the
  • the first to eighth scanning transistors GT1 to GT8 may be P-type transistors.
  • the tube may alternatively be an N-type transistor.
  • the first power supply terminal VGH continuously provides a high level signal
  • the second power supply terminal VGL continuously provides a low level signal
  • FIG. 9B is a timing diagram of the scan shift register provided in FIG. 9A .
  • FIG. 9B takes the first scan transistor GT1 to the eighth scan transistor GT8 as P-type transistors as an example.
  • the working process of the scan shift register provided by an exemplary embodiment includes the following stages:
  • the signals of the first clock signal terminal CK1 and the input terminal GIN are low-level signals, and the signal of the second clock signal terminal CK2 is a high-level signal. Since the signal of the first clock signal terminal CK1 is a low-level signal, the first scanning transistor GT1 is turned on, and the signal of the input terminal GIN is transmitted to the first node N1 via the first scanning transistor GT1. Since the signal of the eighth scanning transistor GT8 receives the low-level signal of the second power supply terminal VGL, the eighth scanning transistor GT8 is in an on state.
  • the level of the third node N3 can be turned on by the fifth scanning transistor GT5, and the signal of the second clock signal terminal CK2 is transmitted to the output terminal GOUT via the fifth scanning transistor GT5, that is, in the input stage B1, the output terminal GOUT is the signal of the second clock signal terminal CK2 of the high-level signal.
  • the third scanning transistor GT3 since the signal of the first clock signal terminal CK1 is a low-level signal, the third scanning transistor GT3 is turned on, and the low-level signal of the second power supply terminal VGL is transmitted to the second node N2 via the third scanning transistor GT3.
  • the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are both turned on. Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh scanning transistor GT7 is turned off.
  • the signal of the first clock signal terminal CK1 is a high level signal
  • the signal of the second clock signal terminal CK2 is a low level signal
  • the signal of the input terminal GIN is a high level signal.
  • the fifth scanning transistor GT5 is turned on, and the signal of the second clock signal terminal CK2 is used as the signal of the output terminal GOUT via the fifth scanning transistor GT5.
  • the signal of one end of the second scanning capacitor GC2 connected to the output terminal GOUT becomes the signal of the second power supply terminal VGL. Due to the bootstrap effect of the second scanning capacitor GC2, the eighth scanning transistor GT8 is turned off, the fifth scanning transistor GT5 can be better turned on, and the signal of the output terminal GOUT is a low level signal.
  • the signal of the first clock signal terminal CK1 is a high level signal, so that the first scanning transistor GT1 and the third scanning transistor GT3 are both turned off.
  • the second scanning transistor GT2 is turned on, and the high level signal of the first clock signal terminal CK1 is transmitted to the second node N2 via the second scanning transistor GT2, thereby, the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are both turned off. Since the signal of the second clock signal terminal CK2 is a low level signal, the seventh scanning transistor GT7 is turned on.
  • the signals of the first clock signal terminal CK1 and the second clock signal terminal CK2 are both high-level signals
  • the signal of the input terminal GIN is a high-level signal
  • the fifth scanning transistor GT5 is turned on
  • the second clock signal terminal CK2 is used as an output signal via the fifth scanning transistor GT5.
  • the signal of the first clock signal terminal CK1 is a high-level signal, so that the first scanning transistor GT1 and the third scanning transistor GT3 are both turned off, the eighth scanning transistor GT8 is turned on, the second scanning transistor GT2 is turned on, and the high-level signal of the first clock signal terminal CK1 is transmitted to the second node N2 via the second scanning transistor GT2, thereby, the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are both turned off. Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh scanning transistor GT7 is turned off.
  • the signal of the first clock signal terminal CK1 is a low-level signal
  • the signals of the second clock signal terminal CK2 and the input terminal GIN are high-level signals. Since the signal of the first clock signal terminal CK1 is a low-level signal, the first scanning transistor GT1 is turned on, the signal of the input terminal GIN is transmitted to the first node N1 via the first scanning transistor GT1, and the second scanning transistor GT2 is turned off. Since the eighth scanning transistor GT8 is in the on state, the fifth scanning transistor GT5 is turned off.
  • the third scanning transistor GT3 is turned on, the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are both turned on, and the high-level signal of the first power supply terminal VGH is transmitted to the output terminal GOUT via the fourth scanning transistor GT4, that is, the signal of the output terminal GOUT is a high-level signal.
  • the signal of the first clock signal terminal CK1 is a high-level signal
  • the signal of the second clock signal terminal CK2 is a low-level signal
  • the signal of the input terminal GIN is a high-level signal.
  • the fifth scanning transistor GT5 and the second scanning transistor GT2 are both turned off.
  • the signal of the first clock signal terminal CK1 is a high-level signal, so that the first scanning transistor GT1 and the third scanning transistor GT3 are both turned off.
  • the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are both turned on, and the high-level signal is transmitted to the output terminal GOUT via the fourth scanning transistor GT4, that is, the signal of the output terminal GOUT is a high-level signal.
  • the seventh scanning transistor GT7 is turned on, so that the high-level signal is transmitted to the third node N3 and the first node N1 via the sixth scanning transistor GT6 and the seventh scanning transistor GT7, so that the signals at the third node N3 and the first node N1 remain high-level signals.
  • the signals of the first clock signal terminal CK1 and the second clock signal CK2 are both high-level signals, and the signal of the input terminal GIN is a high-level signal.
  • the fifth scanning transistor GT5 and the second scanning transistor GT2 are turned off.
  • the signal of the first clock signal terminal CK1 is a high-level signal, so that the first scanning transistor GT1 and the third scanning transistor GT3 are both turned off, and the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are both turned on.
  • the high-level signal is transmitted to the output terminal GOUT via the fourth scanning transistor GT4, that is, the signal of the output terminal GOUT is a high-level signal.
  • Fig. 10A is an equivalent circuit diagram of a light emitting shift register.
  • the light emitting shift register may include: first to tenth light emitting transistors ET1 to ET10 and first to third light emitting capacitors EC1 to EC3.
  • a gate electrode of the first light emitting transistor ET1 is electrically connected to the first clock signal terminal CK1, a first electrode of the first light emitting transistor ET1 is electrically connected to the input terminal EIN, and a second electrode of the first light emitting transistor ET1 is electrically connected to the first node N1;
  • a gate electrode of the second light emitting transistor ET2 is electrically connected to the first node N1, a first electrode of the second light emitting transistor ET2 is electrically connected to the first clock signal terminal CK1, and a second electrode of the second light emitting transistor ET2 is electrically connected to the second node N2;
  • a gate electrode of the third light emitting transistor ET3 is electrically connected to the first clock signal terminal CK1, and a first electrode of the third light emitting transistor ET3 is electrically connected to the second power supply terminal VGL , the second electrode of the third light emitting transistor ET3 is electrically connected to the second node N2;
  • the gate electrode of the fourth light emitting transistor ET is electrically connected to the first
  • the first to tenth light emitting transistors ET1 to ET10 may be P-type transistors or may be N-type transistors.
  • the first power supply terminal VGH continuously provides a high level signal
  • the second power supply terminal VGL continuously provides a low level signal
  • Fig. 10B is a timing diagram of the light emitting shift register provided in Fig. 10A.
  • Fig. 10B takes the first light emitting transistor ET1 to the tenth light emitting transistor ET10 as P-type transistors as an example, and the working process of the light emitting shift register provided by an exemplary embodiment may include the following stages:
  • the signal of the first clock signal terminal CK1 is at a low level, so the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned on, and the turned-on first light-emitting transistor ET1 transmits the high-level signal of the input terminal EIN to the first node N1, and the signal of the first node N1 becomes a high-level signal, so the second light-emitting transistor ET2, the eighth light-emitting transistor ET8 and the tenth light-emitting transistor ET10 are turned off.
  • the turned-on third light-emitting transistor ET3 transmits the low-level signal of the second power supply terminal VGL to the second node N2, and the signal of the second node N2 becomes a low-level signal, so the fifth light-emitting transistor ET5 and the sixth light-emitting transistor ET6 are turned on. Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh light-emitting transistor ET7 is turned off. In addition, due to the storage function of the third light-emitting capacitor EC3, the ninth light-emitting transistor ET9 is turned off. In the first stage C1, since the ninth light-emitting transistor ET9 and the tenth light-emitting transistor ET10 are both turned off, the signal of the output terminal EOUT maintains the previous low level.
  • the signal of the second clock signal terminal CK2 is at a low level, so the fourth light-emitting transistor ET4 and the seventh light-emitting transistor ET7 are turned on. Since the signal of the first clock signal terminal CK1 is at a high level, the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned off. Due to the storage function of the first light-emitting capacitor EC1, the second node N2 can continue to maintain the low level of the previous stage, so the fifth light-emitting transistor ET5 and the sixth light-emitting transistor ET6 are turned on.
  • the high-level signal of the first power supply terminal VGH is transmitted to the first node N1 through the turned-on fifth light-emitting transistor ET5 and the fourth light-emitting transistor ET4, and the level of the first node N1 continues to maintain the high level of the previous stage, so the second light-emitting transistor ET2, the eighth light-emitting transistor ET8 and the tenth light-emitting transistor ET10 are turned off.
  • the low-level signal of the second clock signal terminal CK2 is transmitted to the gate electrode of the ninth light-emitting transistor ET9 through the turned-on sixth light-emitting transistor ET6 and the seventh light-emitting transistor ET7, and the ninth light-emitting transistor ET9 is turned on.
  • the turned-on ninth light-emitting transistor ET9 outputs the high-level signal of the first power supply terminal VGH, and the signal of the output terminal EOUT is at a high level.
  • the signal at the first clock signal terminal CK1 is at a low level, so the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned on.
  • the signal at the second clock signal terminal CK2 is at a high level, so the fourth light-emitting transistor ET4 and the seventh light-emitting transistor ET7 are turned off.
  • the ninth light-emitting transistor ET9 remains turned on, and the turned-on ninth light-emitting transistor ET9 outputs the high-level signal of the first power supply terminal VGH, and the signal at the output terminal EOUT is still at a high level.
  • the signal of the first clock signal terminal CK1 is at a high level, so the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned off.
  • the signal of the second clock signal terminal CK2 is at a low level, so the fourth light-emitting transistor ET4 and the seventh light-emitting transistor ET7 are turned on. Due to the storage function of the second light-emitting capacitor EC2, the level of the first node N1 remains at a high level in the previous stage, and the second light-emitting transistor ET2, the eighth light-emitting transistor ET8 and the tenth light-emitting transistor ET10 are turned off.
  • the second node N2 continues to maintain the low level in the previous stage, and the fifth light-emitting transistor ET5 and the sixth light-emitting transistor ET6 are turned on.
  • the low-level signal of the second clock signal terminal CK2 is transmitted to the gate electrode of the ninth light-emitting transistor ET9 through the turned-on sixth light-emitting transistor ET6 and the seventh light-emitting transistor ET7, so the ninth light-emitting transistor ET9 is turned on, and the turned-on ninth light-emitting transistor ET9 outputs the high-level signal of the first power supply terminal VGH, and the signal of the output terminal EOUT is still at a high level.
  • the signal at the first clock signal terminal CK1 is at a low level, so the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned on.
  • the signal at the second clock signal terminal CK2 is at a high level, so the fourth light-emitting transistor ET4 and the seventh light-emitting transistor ET7 are turned off.
  • the turned-on first light-emitting transistor ET1 transmits the high-level signal at the input terminal EIN to the first node N1, and the signal at the first node N1 becomes a low-level signal, so the second light-emitting transistor ET2, the eighth light-emitting transistor ET8 and the tenth light-emitting transistor ET10 are turned on.
  • the turned-on second light-emitting transistor ET2 The signal of the low-level first clock signal terminal CK1 is transmitted to the second node N2, which can pull down the level of the second node N2, so the second node N2 continues to maintain the low level of the previous stage, and the fifth light-emitting transistor ET5 and the sixth light-emitting transistor ET6 are turned on.
  • the turned-on eighth light-emitting transistor ET8 transmits the high-level signal of the first power supply terminal VGH to the gate electrode of the ninth light-emitting transistor ET9, so the ninth light-emitting transistor ET9 is turned off.
  • the turned-on tenth light-emitting transistor ET10 outputs the low-level signal of the second power supply terminal VGL, and the signal of the output terminal EOUT becomes low level.
  • Fig. 11 is a schematic diagram of the structure of the semiconductor layer and the second conductive layer in the display substrate provided in Fig. 5A
  • Fig. 12 is a schematic diagram of the structure of the semiconductor layer and the second conductive layer in the display substrate provided in Fig. 6A.
  • at least one light-emitting output signal line includes: an output connection portion COL and at least one output line OL, the output connection portion COL extends along a first direction D1, and the at least one output line OL is arranged along the first direction D1.
  • the output connection part COL is electrically connected to the light emitting shift register and at least one output line OL respectively.
  • the output line OL corresponds to the light emitting signal line connected to the light emitting output signal line one by one and is electrically connected to the corresponding light emitting signal line.
  • the output line OL includes: an output body portion OLA extending at least partially along the second direction D2 and an output connection portion OLB extending along the first direction D1 , and the output body portion OLA is electrically connected to the output connection portion OLB.
  • the second electrode of the first release transistor and the second electrode of the second release transistor are an integrated structure, and their orthographic projection on the substrate at least partially overlaps with the orthographic projection of the output connection portion on the substrate, and the integrated structure of the second electrode of the first release transistor and the second electrode of the second release transistor is electrically connected to the output connection portion.
  • the active layer RT11 of the first release transistor and the active layer RT21 of the second release transistor in the display substrate provided in Fig. 5A are an integrated structure and extend along the second direction D2.
  • the orthographic projection of the output connection portion OLB on the substrate does not overlap with the orthographic projection of the integrated structure of the active layer RT11 of the first release transistor and the active layer RT21 of the second release transistor on the substrate.
  • the active layer RT11 of the first release transistor and the active layer RT21 of the second release transistor in the display substrate provided in FIG. 6A are an integrated structure and include: an active main body portion R1 and an active connection portion R2, the active main body portion R1 and the active connection portion R2 are electrically connected, and the active main body portion R1 and the active connection portion R2 are arranged along a first direction D1.
  • the active body portion R1 extends along the second direction D2
  • the active connection portion R2 at least partially extends along the first direction D1 .
  • the active connection portion R2 is in a zigzag shape.
  • the active connection portion R2 is in a zigzag shape, which can increase resistance, increase static electricity consumption, avoid gate drive circuits from being burned, and improve display effects and reliability of the display substrate.
  • the output line OL at least partially extends along the second direction D2; the second electrode of the first release transistor and the second electrode of the second release transistor are an integral structure.
  • the positive projection of the active connection portion R2 on the substrate at least partially overlaps with the integral structure of the second electrode of the first release transistor and the second electrode of the second release transistor and the positive projection of the output line OL on the substrate, and is electrically connected to the integral structure of the second electrode of the first release transistor and the second electrode of the second release transistor and the output line OL, respectively.
  • the width of the active connection portion R2 is smaller than the width of the active body portion R1 .
  • the scan shift register includes a first scan capacitor, a second plate GC12 of the first scan capacitor is electrically connected to the first scan power line, and a second plate GC21 of the first scan capacitor extends along the second direction D2 .
  • the second electrode of the first scanning capacitor at least partially overlaps with the orthographic projections of the first scan power line GVGH, the second scan power line GVGL, the first scan clock signal line GCK1, the second scan clock signal line GCK2 and the scan start signal line GSTV on the substrate.
  • FIG13 is another schematic diagram of the structure of the display substrate.
  • the display area may include: a first display area A1 and a second display area A2 located at least on one side of the first display area A1, and the display substrate further includes: a light-emitting device and an anode connection line AL located in the display area 100.
  • the pixel circuit is electrically connected to the light-emitting device.
  • the pixel circuit includes: a first pixel circuit 11 and a second pixel circuit 12 located in the second display area A2, and the light-emitting device includes: a first light-emitting device 21 located in the first display area A1 and a second light-emitting device 22 located in the second display area.
  • the first pixel circuit 11 is electrically connected to the first light-emitting device 21, and the second pixel circuit is electrically connected to the second light-emitting device 22.
  • the orthographic projection of the first pixel circuit 11 on the substrate at least partially overlaps with the orthographic projection of the first light-emitting device 21 connected to the first pixel circuit 11 on the substrate.
  • the anode connection line AL is electrically connected to the second light emitting device 22 and the second pixel circuit 12 connected to the second light emitting device 22 , respectively.
  • the anode connection line AL may be a transparent conductive line.
  • the driving structure layer may further include: a first power line VDD and a data signal line Data at least partially located in the display area.
  • the first power line VDD and the data signal line Data at least partially extend along the first direction D1.
  • the data signal lines Data connected to the columns where the pixel circuits located at the left and right sides of the first display area are located extend along the first direction D1.
  • the driving structure layer may further include: a data link line DL located in the display area, the data link line DL at least partially extending along the second direction D2 .
  • the data signal lines connected to the columns where the pixel circuits located on the upper and lower sides of the first display area are arranged around the first display area, that is, the data signal lines connected to the columns where the pixel circuits located on the upper and lower sides of the first display area are in a zigzag shape.
  • the data signal lines connected to the columns where the pixel circuits located on the upper and lower sides of the first display area include: a plurality of data main body lines arranged at intervals extending in the first direction and a plurality of data connection lines arranged at intervals extending in the second direction, adjacent data main body lines are connected by data connection lines, and adjacent data connection lines are connected by data main line.
  • the data main line and the data connection line are arranged in different layers.
  • the structure of some pixel circuits includes data connection lines, and the structure of some pixel circuits does not include data connection lines.
  • FIG. 7B is illustrated by taking the structure of the pixel circuit including the data connection lines as an example
  • FIG. 7A and FIG. 7C are illustrated by taking the structure of the pixel circuit not including the data connection lines as an example.
  • the driving structure layer further includes: a fourth conductive layer and a fifth conductive layer sequentially stacked on the third conductive layer.
  • the third conductive layer includes at least: a data connection line.
  • the fourth conductive layer includes at least: a first power line and a data signal line.
  • the fifth conductive layer includes at least an anode connection line.
  • the driving structure layer may further include: at least one initial power supply line located in the non-display area and at least one initial signal line located at least partially in the display area; the initial power supply line is located on a side of the scan drive circuit close to the display area, the initial power supply line at least partially extends along the first direction D1, and the initial signal line at least partially extends along the second direction D2.
  • FIG. 5 and FIG. 6 are illustrated by taking two initial power supply lines, such as the first initial power supply line INITL1 and the second initial power supply line INITL2, as an example.
  • FIG. 7A and FIG. 7B are illustrated by taking two initial signal lines, the first initial signal line INIT1 and the second initial signal line INIT2, as an example. Clear.
  • the initial signal lines correspond to the initial power supply lines one by one, and the initial signal lines are electrically connected to the pixel circuits and the corresponding initial power supply lines, respectively.
  • the initial power supply line may have a double-layer structure.
  • the initial power supply line may include: a first sub-initial power supply line and a second sub-initial power supply line electrically connected to each other.
  • the third conductive layer includes at least: a first sub-initial power supply line of the initial power supply line;
  • the fourth conductive layer includes at least a second sub-initial power supply line of the initial power supply line.
  • the first insulating layer 11 is located between the semiconductor layer and the first conductive layer
  • the second insulating layer 12 is located between the first conductive layer and the second conductive layer
  • the third insulating layer 13 is located between the second conductive layer and the third conductive layer
  • the fourth insulating layer 14 and the planar layer 15 are located between the third conductive layer and the fourth conductive layer
  • the fifth insulating layer 16 is located between the fourth conductive layer and the fifth conductive layer
  • the sixth insulating layer 17 is located on a side of the fifth conductive layer away from the substrate.
  • the planar layer is provided with a groove X.
  • the depth of the groove X may be less than or equal to the thickness of the planar layer, which is not limited in the present disclosure.
  • the orthographic projection of the electrostatic discharge circuit ER on the substrate at least partially overlaps the orthographic projection of the groove X on the substrate.
  • the present disclosure can achieve a narrow frame without increasing the area occupied by the display frame by arranging the electrostatic discharge circuit at the groove position of the flat layer.
  • the driving structure layer may further include: a second power connection line and a second power line.
  • the second power line and the second power connection line are electrically connected to each other.
  • the second power line is electrically connected to the cathode of the light emitting device.
  • the second power connection line may be located in the third conductive layer, and the second power line may be located in the fourth conductive layer.
  • an orthographic projection of the second power connection line on the substrate and an orthographic projection of the second power line on the substrate at least partially overlap.
  • the second power line is connected to the first power connection line through a via hole between the fourth insulating layer and the planar layer.
  • the second power connection line may be in a linear shape extending in the second direction D2 and may be located at a side of the light emitting initial signal line away from the first light emitting clock signal line.
  • the shape of the second power line can be a linear shape extending along the second direction D2, and its orthographic projection on the substrate also at least partially overlaps with the orthographic projections of the light-emitting initial signal line, the first light-emitting clock signal line, the second light-emitting clock signal line, and the first light-emitting power line on the substrate.
  • a plurality of via holes are disposed on the second power line.
  • a distance between an orthographic projection of the second power line on the substrate and an orthographic projection of the second light emitting power line on the substrate is smaller than a distance between the first light emitting power line and the second light emitting power line.
  • the following is an exemplary description of the preparation process of the display substrate.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials.
  • Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition, and coating can be achieved by spraying, spin coating, and inkjet printing.
  • Any one or more of, etching can be any one or more of dry etching and wet etching, which is not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • 14 to 33 are illustrative of the structure located in the non-display area provided in FIGS. 5A and 6A
  • FIGS. 34 to 55 are illustrative of the pixel circuit located in the display area provided in FIGS. 7B and 7C .
  • Figure 14 is a schematic diagram of Figure 5A after the semiconductor layer pattern is formed
  • Figure 15 is a schematic diagram of Figure 6A after the semiconductor layer pattern is formed
  • Figure 34 is a schematic diagram of Figure 7B after the semiconductor layer pattern is formed
  • Figure 35 is a schematic diagram of Figure 7C after the semiconductor layer pattern is formed.
  • the semiconductor layer pattern may include: an active layer ET11 of the first light emitting transistor to an active layer ET101 of the tenth light emitting transistor located in the light emitting shift register, an active layer RT11 of the first release transistor to an active layer RT21 of the second release transistor located in the electrostatic release circuit, an active layer GT11 of the first scanning transistor to an active layer GT81 of the eighth scanning transistor located in the scanning shift register, and an active layer M11 of the first transistor to an active layer M71 of the seventh transistor located in the pixel circuit.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked.
  • the first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc.
  • the first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers, and the semiconductor layer may be made of amorphous silicon (a-Si).
  • its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.
  • PI1 first flexible
  • a-si amorphous silicon
  • the active layers ET41 and ET51 of the fourth and fifth light emitting transistors are connected as one body.
  • the active layers ET91 and ET101 of the ninth and tenth light emitting transistors are connected as one body.
  • the active layers ET11 of the first light emitting transistor to the active layer ET81 of the eighth light emitting transistor are located on a side of the active layer ET91 of the ninth light emitting transistor (also the active layer ET101 of the tenth light emitting transistor) away from the display area.
  • the active layer ET81 of the eighth light emitting transistor is located on a side away from the display area.
  • the active layer ET11 of the first light emitting transistor and the active layer ET41 of the fourth light emitting transistor are located on a side away from the display area of the active layer ET21 of the second light emitting transistor, and the active layer ET31 of the third light emitting transistor and the active layer ET61 of the sixth light emitting transistor are located on a side of the active layer ET21 of the second light emitting transistor close to the active layer ET91 of the ninth light emitting transistor (also the active layer ET101 of the tenth light emitting transistor).
  • the active layer ET51 of the fifth light emitting transistor of the current light emitting shift register is located on a side of the active layer ET41 of the fourth light emitting transistor close to the next light emitting shift register, and the active layers ET11 to ET61 of the first light emitting transistor of the current shift register are located on a side of the active layer ET81 of the eighth light emitting transistor close to the previous light emitting shift register.
  • the active layers ET11 to ET71 of the first to seventh light emitting transistors, the active layers ET91 of the ninth light emitting transistors, and the active layer ET101 of the tenth light emitting transistor may be strip-shaped extending along the first direction D1.
  • the active layer ET81 of the eighth light emitting transistor may be strip-shaped extending along the second direction D2.
  • the active layer of each light emitting transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the first region ET41-1 of the active layer ET41 of the fourth light emitting transistor may simultaneously serve as the second region ET51-2 of the active layer ET51 of the fifth light emitting transistor, the first region ET11-1 and the second region ET11-2 of the active layer ET11 of the first light emitting transistor, the first region ET21-1 and the second region ET21-2 of the active layer ET21 of the second light emitting transistor, the first region ET31-1 and the second region ET31-2 of the active layer ET31 of the third light emitting transistor, the second region ET41-2 of the active layer ET41 of the fourth light emitting transistor, and the fifth light emitting transistor.
  • the first region ET51-1 of the active layer ET51, the first region ET61-1 and the second region ET61-2 of the active layer ET61 of the sixth light-emitting transistor, the first region ET71-1 and the second region ET71-2 of the active layer ET71 of the seventh light-emitting transistor, the first region ET81-1 and the second region ET81-2 of the active layer ET81 of the eighth light-emitting transistor, the first region ET91-1 and the second region ET91-2 of the active layer ET91 of the ninth light-emitting transistor, and the first region ET101-1 and the second region ET101-2 of the active layer ET101 of the tenth light-emitting transistor can be set separately.
  • the active layer RT11 of the first release transistor and the active layer RT21 of the second release transistor are an integral structure connected to each other.
  • the active layer RT11 of the first release transistor and the active layer RT21 of the second release transistor are located on the side of the active layer ET91 of the ninth light emitting transistor (also the active layer ET101 of the tenth light emitting transistor) close to the display area.
  • the active layer RT21 of the second release transistor is located on a side of the active layer RT11 of the first release transistor close to the display area.
  • the shape of the active layer RT11 of the first release transistor (also the active layer RT21 of the second release transistor) in the display substrate provided in FIG. 3B may be a strip extending along the second direction D2 .
  • the active layer RT11 of the first release transistor (also the active layer RT21 of the second release transistor) in the display substrate provided in FIG3C may include: an active body portion R1 and an active connection portion R2.
  • the active body portion R1 and the active connection portion R2 are an integral structure connected to each other and arranged along the first direction D1.
  • the active body portion R1 may be in a strip shape extending along the second direction D2
  • the active connection portion R2 may be in a zigzag shape extending at least partially along the first direction D1 .
  • the width of the active connection portion R2 may be smaller than the width of the active body portion R1 .
  • the active layer of each release transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region RT11-2 may simultaneously serve as the second region RT21-2 of the active layer RT21 of the second release transistor.
  • the first region RT11-1 of the active layer RT11 of the first release transistor and the first region RT21-1 of the active layer RT21 of the second release transistor may be separately provided.
  • the second region RT11 - 2 of the active layer RT11 of the first release transistor includes a middle section of an active body portion and an active connection portion R2 .
  • the active layer GT11 of the first scan transistor, the active layer GT61 of the sixth scan transistor, and the active layer GT71 of the seventh scan transistor are interconnected as an integrated structure.
  • the active layer GT21 of the second scan transistor and the active layer GT31 of the third scan transistor are interconnected as an integrated structure.
  • the active layer GT41 of the fourth scan transistor and the active layer GT51 of the fifth scan transistor are interconnected as an integrated structure.
  • the active layers GT11 to GT31 of the first scanning transistor, and the active layers GT51 to GT81 of the fifth scanning transistor are located on the side of the active layer GT41 of the fourth scanning transistor (also the active layer GT51 of the fifth transistor) away from the display area, and on the side of the active layer RT11 of the first release transistor (also the active layer RT21 of the second release transistor) close to the display area.
  • the active layer GT21 of the second scanning transistor (also the active layer GT31 of the third scanning transistor) is located between the active layer GT11 of the first scanning transistor (the active layer GT61 of the sixth scanning transistor and the active layer GT71 of the seventh scanning transistor) and the active layer GT81 of the eighth scanning transistor.
  • the active layer GT11 of the first scanning transistor (the active layer GT61 of the sixth scanning transistor and the active layer GT71 of the seventh scanning transistor) is located on the side of the active layer GT21 of the second scanning transistor (also the active layer GT31 of the third scanning transistor) close to the active layer RT11 of the first release transistor (also the active layer RT21 of the second release transistor), and the active layer GT81 of the eighth scanning transistor is located on the side of the active layer GT21 of the second scanning transistor (also the active layer GT31 of the third scanning transistor) close to the active layer GT41 of the fourth scanning transistor (also the active layer GT51 of the fifth transistor).
  • the active layer GT41 of the fourth scanning transistor of the current level scanning shift register is located on the side of the active layer GT51 of the fifth transistor close to the next level scanning shift register.
  • the active layer GT11 of the first scan transistor, the active layer GT41 of the fourth scan transistor, the active layer GT51 of the fifth transistor, the active layer GT61 of the sixth scan transistor, the active layer GT71 of the seventh scan transistor, and the active layer GT81 of the eighth scan transistor may be in the shape of a line extending along the first direction D1.
  • the active layer GT21 of the second scan transistor may be in the shape of a line extending along the second direction D2.
  • the active layer GT31 of the third scan transistor may be in the shape of a horizontally flipped “7” shape.
  • the active layer of each scanning transistor may include a first region, a second region, and a channel region located between the first region and the second region.
  • the second region GT11-2 of the active layer GT11 of the first scanning transistor may be used as the second region GT71-2 of the active layer GT71 of the seventh scanning transistor
  • the second region GT21-2 of the active layer GT21 of the second scanning transistor may be used as the second region GT31-2 of the active layer GT31 of the third scanning transistor
  • the second region GT41-2 of the active layer GT41 of the fourth scanning transistor may be used as the second region GT51-2 of the active layer GT51 of the fifth scanning transistor at the same time.
  • the second region GT61-2 of the active layer GT61 of the sixth scanning transistor may be used as the second region GT71-1 of the active layer GT71 of the seventh scanning transistor.
  • the active layers M11 of the first transistor to M71 of the seventh transistor in the same sub-pixel are an integral structure connected to each other.
  • the active layer M21 of the second transistor and the active layer M61 of the sixth transistor may be located on the same side of the active layer M31 of the third transistor in the present subpixel
  • the active layer M41 of the fourth transistor and the active layer M51 of the fifth transistor may be located on the same side of the active layer M31 of the third transistor in the present subpixel
  • the active layer M21 of the second transistor and the active layer M41 of the fourth transistor may be located on the same side of the active layer M31 of the third transistor in the present subpixel.
  • the active layer M11 of the first transistor, the active layer M21 of the second transistor, and the active layer M41 of the fourth transistor in the present row of sub-pixels can be located on a side of the active layer M31 of the third transistor in the present sub-pixel away from the sub-pixel in the previous row, and the active layer M51 of the fifth transistor, the active layer M61 of the sixth transistor, and the active layer M71 of the seventh transistor in the present sub-pixel can be located on a side of the active layer M31 of the third transistor in the present sub-pixel close to the sub-pixel in the previous row.
  • the active layer M11 of the first transistor may have an "n" shape
  • the active layer M51 of the fifth transistor and the active layer M61 of the sixth transistor may have an "L” shape
  • the active layer M31 of the third transistor may have an " ⁇ ” shape
  • the active layer M41 of the fourth transistor and the active layer M71 of the seventh transistor may have an "I" shape.
  • the shape of the active layer M21 of the second transistor may be a zigzag shape including two bends.
  • the active layer M21 of the second transistor may be shaped like an “L”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region M11-2 of the active layer M11 of the first transistor may serve as the first region M21-1 of the active layer M21 of the second transistor
  • the first region M31-1 of the active layer M31 of the third transistor may serve as the second region M41-2 of the active layer M41 of the fourth transistor and the second region M51-2 of the active layer M51 of the fifth transistor
  • the second region M31-2 of the active layer M31 of the third transistor may serve as the first region M21 of the active layer M21 of the second transistor.
  • the second region M21-2 and the first region M61-1 of the active layer M61 of the sixth transistor, the second region M61-2 of the active layer M61 of the sixth transistor can serve as the second region M71-2 of the active layer M71 of the seventh transistor, the first region M11-1 of the active layer of the first transistor, the first region M41-1 of the active layer M41 of the fourth transistor, the first region M51-1 of the active layer M51 of the fifth transistor and the first region M71-1 of the active layer M71 of the seventh transistor can be set separately.
  • FIG. 16 is a schematic diagram of the first conductive layer pattern of FIGS. 5A and 6A
  • FIG. 17 is a schematic diagram of FIG. 5A after the first conductive layer pattern is formed
  • FIG. 18 is a schematic diagram of the display substrate provided by FIG. 6A after the first conductive layer pattern is formed
  • FIG. 16 is a schematic diagram of the first conductive layer pattern of FIGS. 5A and 6A
  • FIG. 17 is a schematic diagram of FIG. 5A after the first conductive layer pattern is formed
  • FIG. 18 is a schematic diagram of the display substrate provided by FIG. 6A after the first conductive layer pattern is formed
  • FIG. 16 is a schematic diagram of the first conductive layer pattern of FIGS. 5A and 6A
  • FIG. 17 is a schematic diagram of FIG. 5A after the first conductive layer pattern is formed
  • FIG. 18 is a schematic diagram of the display substrate provided by FIG. 6A after the first conductive layer pattern is formed
  • FIG. 36 is a schematic diagram of the first conductive layer pattern of FIG. 7B
  • FIG. 37 is a schematic diagram of FIG. 7B after the first conductive layer pattern is formed
  • FIG. 38 is a schematic diagram of the first conductive layer pattern of FIG. 7C
  • FIG. 39 is a schematic diagram of FIG. 7C after the first conductive layer pattern is formed.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern may at least include: the gate electrode ET12 of the first light-emitting transistor to the gate electrode ET102 of the tenth light-emitting transistor located in the light-emitting shift register and the first plate EC11 of the first light-emitting capacitor to the first plate EC31 of the third light-emitting capacitor, the gate electrode RT12 of the first release transistor and the gate electrode RT22 of the second release transistor located in the electrostatic release circuit, the gate electrode GT12 of the first scanning transistor to the gate electrode GT82 of the scanning light-emitting transistor located in the scanning shift register and the first plate GC11 of the first scanning capacitor and the first plate GC21 of the second scanning capacitor, the first signal connection line L1 and the second signal connection line L2, the reset signal line Reset, the scanning signal line Gate, the light-emitting signal line EM, the gate electrode M11 of the first transistor to the gate electrode M71 of the seventh transistor and the first plate
  • the gate electrode ET12 of the first light emitting transistor and the gate electrode ET32 of the third light emitting transistor are an integrated structure connected to each other.
  • the gate electrode ET22 of the second light emitting transistor, the gate electrode ET82 of the eighth light emitting transistor, the gate electrode ET102 of the tenth light emitting transistor, and the first electrode of the third light emitting capacitor are connected to each other.
  • the plate EC31 is an integrated structure connected to each other.
  • the gate electrode ET52 of the fifth light-emitting transistor, the gate electrode ET62 of the sixth light-emitting transistor and the first plate EC11 of the first light-emitting capacitor are an integrated structure connected to each other.
  • the gate electrode ET2 of the ninth light-emitting transistor and the first plate EC21 of the second light-emitting capacitor are an integrated structure connected to each other.
  • the gate electrode ET42 of the fourth light-emitting transistor and the gate electrode ET72 of the seventh light-emitting transistor can be set separately.
  • the first electrode EC31 of the third light emitting capacitor is located on the side of the first electrode EC11 of the first light emitting capacitor close to the display area
  • the gate electrode ET22 of the second light emitting transistor is located on the side of the first electrode EC31 of the third light emitting capacitor away from the display area
  • the gate electrode ET102 of the tenth light emitting transistor is located on the side of the first electrode EC31 of the third light emitting capacitor close to the display area
  • the gate electrode ET92 of the ninth light emitting transistor is located on the side of the first electrode EC21 of the second light emitting capacitor close to the display area
  • the gate electrode ET52 of the fifth light emitting transistor is located on the side of the first electrode EC11 of the first light emitting capacitor away from the display area
  • the gate electrode ET62 of the sixth light emitting transistor is located on the side of the first electrode EC11 of the first light emitting capacitor close to the display area.
  • the gate electrode ET82 of the eighth light emitting transistor of the current-stage light emitting shift register is located on the side of the first electrode EC31 of the third light emitting capacitor close to the next-stage light emitting shift register.
  • the first plate EC11 of the first light emitting capacitor and the first plate EC31 of the third light emitting capacitor of the current stage shift light emitting shift register are located on the side of the first plate EC21 of the second light emitting capacitor close to the previous stage light emitting shift register.
  • the gate electrode ET12 of the first light emitting transistor, the gate electrode ET42 of the fourth light emitting transistor, the gate electrode ET52 of the fifth light emitting transistor, the gate electrode ET62 of the sixth light emitting transistor, and the gate electrode ET72 of the seventh light emitting transistor may be shaped like a strip extending at least partially along the second direction D2.
  • the shape of the gate electrode ET22 of the second light-emitting transistor can be rectangular, and an opening is provided on the gate electrode ET22 of the second light-emitting transistor.
  • the shape of the opening can be rectangular and can be located in the middle of the gate electrode ET22 of the second light-emitting transistor, so that the gate electrode ET22 of the second light-emitting transistor forms a ring structure.
  • the gate electrode ET32 of the third light emitting transistor may have an inverted “T” shape.
  • the gate electrode ET82 of the eighth light emitting transistor may be in the shape of a strip extending at least partially along the first direction D1 , or may be in the shape of a zigzag line.
  • the shape of the gate electrode ET92 of the ninth light-emitting transistor may include a first connecting segment extending along the first direction D1 and a plurality of first branch segments extending along the second direction D2, the first connecting segment is connected to the first plate of the second capacitor, the first branch segments are located on a side of the first connecting segment close to the display area, and the gate electrode ET92 of the ninth light-emitting transistor may be shaped like a comb, with the first connecting segment serving as the comb back and the first branch segments serving as the comb teeth.
  • the shape of the gate electrode ET102 of the tenth light-emitting transistor may include a plurality of second branch segments extending along the second direction D2, and the plurality of second branch segments and the first electrode plate EC31 of the third light-emitting capacitor may be in a comb-like structure, with the first electrode plate of the third light-emitting capacitor serving as a comb back and the plurality of second branch segments serving as comb teeth.
  • the first electrode plate EC11 of the first light emitting capacitor may be in the shape of a strip extending at least partially along the first direction D1 , and a protrusion is provided on a side away from the display area.
  • the first electrode plate EC21 of the second light emitting capacitor may be in the shape of a strip extending along the second direction D2 .
  • the first electrode plate EC31 of the third light emitting capacitor may be in the shape of a strip extending along the first direction D1 .
  • the gate electrode ET12 of the first light-emitting transistor is arranged across the channel region of the active layer of the first light-emitting transistor
  • the gate electrode ET22 of the second light-emitting transistor is arranged across the channel region of the active layer of the second light-emitting transistor
  • the gate electrode ET32 of the third light-emitting transistor is arranged across the channel region of the active layer of the third light-emitting transistor
  • the gate electrode ET42 of the fourth light-emitting transistor is arranged across the channel region of the active layer of the fourth light-emitting transistor
  • the two first branch segments ET55 of the gate electrode ET52 of the fifth light-emitting transistor are arranged across the channel region of the active layer of the fifth light-emitting transistor
  • the gate electrode ET62 of the sixth light-emitting transistor is arranged across the channel region of the active layer of the fifth light-emitting transistor.
  • the gate electrode ET62 is arranged across the channel region of the active layer of the first light-emitting transistor, the gate electrode ET72 of the seventh light-emitting transistor is arranged across the channel region of the active layer of the seventh light-emitting transistor, the gate electrode ET82 of the eighth light-emitting transistor is arranged across the channel region of the active layer of the eighth light-emitting transistor, multiple first branch segments of the gate electrode ET92 of the ninth light-emitting transistor are arranged across the channel region of the active layer of the ninth light-emitting transistor, and the gate electrode ET102 of the tenth light-emitting transistor is arranged across the channel region of the active layer of the tenth light-emitting transistor. That is to say, the extension direction of the gate electrode of at least one light-emitting transistor is perpendicular to the extension direction of the channel region of the active layer.
  • the second light emitting transistor since the gate electrode ET22 of the second light emitting transistor has a ring structure, the second light emitting transistor has a double gate structure.
  • the gate electrode RT12 of the first release transistor and the gate electrode RT22 of the second release transistor may be in the shape of a bar extending in the first direction D1 .
  • the gate electrode RT12 of the first release transistor is arranged across the channel region of the active layer of the first transistor
  • the gate electrode RT22 of the second release transistor is arranged across the channel region of the active layer of the second transistor, that is, the extension direction of the gate electrode of at least one release transistor is perpendicular to the extension direction of the active layer.
  • the gate electrode GT12 of the first scanning transistor and the gate electrode GT32 of the third scanning transistor are interconnected as an integrated structure.
  • the gate electrode GT42 of the fourth scanning transistor, the gate electrode GT62 of the sixth scanning transistor, and the first plate GC31 of the first scanning capacitor are interconnected as an integrated structure.
  • the gate electrode GT52 of the fifth scanning transistor and the first plate EC21 of the second scanning capacitor are interconnected as an integrated structure.
  • the gate electrode GT22 of the second scanning transistor, the gate electrode GT72 of the seventh scanning transistor, and the gate electrode GT82 of the eighth scanning transistor can be provided separately.
  • the first plate GC11 of the first scanning capacitor is located on the side of the first plate GC21 of the second scanning capacitor away from the display area
  • the gate electrode GT52 of the fifth scanning transistor is located on the side of the first plate EC21 of the second scanning capacitor away from the display area
  • the gate electrode GT42 of the fourth scanning transistor is located on the side of the first plate GC31 of the first scanning capacitor close to the display area
  • the gate electrode GT62 of the sixth scanning transistor is located on the side of the first plate GC31 of the first scanning capacitor away from the display area.
  • the shape of the gate electrode GT12 of the first scan transistor may include: a second connection segment and two third branch segments, the third branch segments are located on a side of the second connection segment away from the display area, and the second connection end is connected to the gate electrode GT32 of the third scan transistor, wherein the lengths of the two branch segments are different.
  • the shape of the gate electrode GT22 of the second scan transistor may include a gate body portion extending in the second direction D2 and a gate connection portion extending in the first direction D1 .
  • the gate electrode GT32 of the third scanning transistor, the gate electrode GT42 of the fourth scanning transistor, the gate electrode GT62 of the sixth scanning transistor, the gate electrode GT72 of the seventh scanning transistor, and the gate electrode GT82 of the eighth scanning transistor may be shaped like a strip extending at least partially along the second direction D2.
  • the shape of the gate electrode GT52 of the fifth scanning transistor may include a plurality of fourth branch segments extending along the second direction D2, and the shape of the gate electrode GT52 of the fifth scanning transistor may be a comb, with the first plate GC21 of the second scanning capacitor serving as a comb back and the plurality of fourth branch segments serving as comb teeth.
  • the first electrode plate GC11 of the first scanning capacitor may be in the shape of a strip extending at least partially along the second direction D2 .
  • the first electrode plate ECG1 of the second scanning capacitor may be in the shape of a strip extending along the first direction D1 .
  • the two third branch segments of the gate electrode GT12 of the first scan transistor are arranged across the channel region of the active layer of the first scan transistor
  • the gate connection portion of the gate electrode GT22 of the second scan transistor is arranged across the channel region of the active layer of the second scan transistor
  • the gate electrode GT32 of the third scan transistor is arranged across the channel region of the active layer of the third scan transistor
  • the gate electrode GT42 of the fourth scan transistor is arranged across the channel region of the active layer of the fourth scan transistor
  • the two first branch segments GT55 of the gate electrode GT52 of the fifth scan transistor are arranged across the channel region of the active layer of the fifth scan transistor
  • the gate electrode GT62 of the sixth scan transistor is arranged across the channel region of the active layer of the first scan transistor
  • the gate electrode GT72 of the seventh scan transistor is arranged across the channel region of the active layer of the seventh scan transistor
  • the gate electrode GT82 of the eighth scan transistor is arranged across the channel region of the active layer of the eighth scan transistor, that is, the extension
  • two third branch segments of the gate electrode GT12 of the first scan transistor are arranged across the channel region of the active layer of the first scan transistor, and the first scan transistor has a double-gate structure.
  • the first signal connection line L1 and the second signal connection line L2 may at least partially extend in the second direction D2 .
  • the shape of the first electrode plate C1 of the capacitor may be rectangular, the corners of the rectangle may be chamfered, and the orthographic projection of the first electrode plate C1 of the capacitor on the substrate at least partially overlaps the orthographic projection of the active layer of the third transistor on the substrate.
  • the first electrode plate C1 of the capacitor may also serve as the gate electrode M32 of the third transistor.
  • the shape of the reset signal line Reset may be a line shape in which the main part extends along the second direction D2, and the reset signal line Reset connected to the sub-pixels of the current row may be located on a side of the first electrode plate C1 of the current sub-pixel close to the sub-pixels of the previous row.
  • the area where the reset signal line Reset overlaps with the active layer of the first transistor serves as the gate electrode MT12 of the first transistor of the dual-gate structure.
  • the shape of the scan signal line Gate can be a line shape in which the main part extends along the second direction D2, the scan signal line Gate connected to the sub-pixel of this row can be located on the side of the reset signal line Reset connected to the sub-pixel close to the first electrode C1, and the area where the scan signal line Gate overlaps with the active layer of the second transistor of the sub-pixel serves as the gate electrode MT22 of the second transistor of the dual-gate structure, and the area where the scan signal line Gate overlaps with the active layer of the fourth transistor serves as the gate electrode MT42 of the fourth transistor.
  • the scan signal line Gate includes a signal main body portion 21 and a signal connection portion 22.
  • One end of the signal connection portion 22 is electrically connected to the signal main body portion 21.
  • the signal main body portion 21 extends along the second direction D2, and the signal connection portion 22 extends along the first direction D1.
  • the signal connection portion 22 is located on a side of the signal main portion 21 close to the first electrode plate of the capacitor.
  • the signal connection portion 22 is located on a side of the signal main portion 21 away from the first electrode plate of the capacitor.
  • the shape of the light emitting signal line EM may be a line shape in which the main part extends along the second direction D2, the light emitting signal line EM may be located on the side of the first plate C1 of the capacitor of the sub-pixel close to the next row of sub-pixels, and the area where the light emitting signal line EM overlaps with the active layer of the fifth transistor of the sub-pixel serves as the active layer of the fifth transistor.
  • the gate electrode MT52, the area where the light-emitting signal line EM overlaps with the active layer of the sixth transistor of the sub-pixel serves as the gate electrode MT62 of the sixth transistor.
  • the reset signal line Reset, the scanning signal line Gate, and the light-emitting signal line EM can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • the semiconductor layer can be conductorized using the first conductive layer as a shield, and the semiconductor layer in the area blocked by the first conductive layer forms the channel region of the first to tenth light-emitting transistors, the channel region of the first to second release transistors, and the channel region of the first to eighth scanning transistors, and the semiconductor layer in the area not blocked by the first conductive layer is conductorized, that is, the first and second areas of the active layers of the first to tenth transistors, the first and second areas of the active layers of the first to second release transistors, and the first and second areas of the active layers of the first to eighth scanning transistors are all conductorized.
  • the first area of the active layer of the fourth light-emitting transistor (also the second area of the active layer of the fifth light-emitting transistor) is multiplexed as the first electrode of the fourth light-emitting transistor (also the second electrode of the fifth light-emitting transistor)
  • the second area of the active layer of the sixth scanning transistor (also the first area of the active layer of the seventh scanning transistor) is multiplexed as the second electrode of the sixth scanning transistor (also the first electrode of the seventh scanning transistor)
  • the second area of the active layer of the second transistor (also the second area of the active layer of the third transistor and the first area of the active layer of the sixth transistor) is multiplexed as the second electrode of the second transistor (also the second electrode of the third transistor and the first electrode of the sixth transistor)
  • the first area of the active layer of the third transistor (also the second area of the active layer of the fourth transistor and the second area of the active layer of the fifth transistor) is multiplexed as the first electrode of the third transistor (also the second electrode of the fourth transistor and
  • forming a third insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film using a patterning process to form a second insulating layer covering the first conductive layer, wherein the second insulating layer is provided with vias, as shown in FIG. 19 , which is a schematic diagram of the display substrate provided in FIG. 6A after the second insulating layer pattern is formed.
  • the via hole includes at least: a via hole V0 located at least in the electrostatic discharge circuit.
  • the orthographic projection of the via hole V0 on the substrate is located within the orthographic projection range of the active connection part on the substrate, exposing the surface of the active connection part, and the via hole V0 is configured to connect the subsequently formed light-emitting output signal line to the active connection part through the via hole.
  • a second insulating layer is also formed in FIGS. 5A , 7B, and 7C, but no via hole is disposed on the second insulating layer.
  • FIG. 20 is a schematic diagram of the second conductive layer pattern of FIG. 5A
  • FIG. 21 is a schematic diagram of FIG. 5A after the second conductive layer pattern is formed
  • FIG. 22 is a schematic diagram of the second conductive layer of FIG. 6A
  • FIG. 23 is a schematic diagram of FIG. 6A after the second conductive layer pattern is formed
  • FIG. 40 is a schematic diagram of the second conductive layer pattern of FIG.
  • FIG. 41 is a schematic diagram of FIG. 7B after the second conductive layer pattern is formed
  • FIG. 42 is a schematic diagram of the second conductive layer pattern of FIG. 7C
  • FIG. 43 is a schematic diagram of FIG. 7C after the second conductive layer pattern is formed.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern may include at least: a second plate EC12 of the first light emitting capacitor to a second plate EC32 of the third light emitting capacitor located in the light emitting shift register, a first plate GC12 of the first scanning capacitor and a second plate GC22 of the second scanning capacitor located in the scanning shift register, a second plate C2 of the capacitor located in the pixel circuit, a scanning signal output line GOL, a light emitting signal output line EOL, a third signal connection line L3, a first initial signal line INIT1 and a second initial signal line INIT2.
  • the second conductive layer pattern may further include: a shielding electrode SL.
  • the orthographic projection of the second plate EC12 of the first light-emitting capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the first light-emitting capacitor on the substrate.
  • the orthographic projection of the second plate EC22 of the second light-emitting capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the second light-emitting capacitor on the substrate.
  • the orthographic projection of the second plate EC32 of the third light-emitting capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the third light-emitting capacitor on the substrate.
  • the scan output signal line GOL and the second plate GC22 of the second scan capacitor are interconnected as an integral structure and are located on a side of the second plate GC22 of the second scan capacitor close to the display area.
  • the orthographic projection of the second plate GC12 of the first scanning capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the first scanning capacitor on the substrate.
  • the orthographic projection of the second plate GC22 of the second scanning capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the second scanning capacitor on the substrate.
  • the scan output signal line GOL at least partially extends along the second direction D2 .
  • the third signal connection line L3 has a bar shape extending along the second direction D2 .
  • the light emitting output signal line may include: an output connection portion COL connected to at least one output line OL.
  • the plurality of output lines OL are arranged along the first direction D1.
  • At least one output line OL is located on a side of the output connection portion COL close to the display area.
  • the output connection portion COL extends in the first direction D1
  • the output line OL at least partially extends in the second direction D2 .
  • the output line OL in FIG. 5A includes an output main body portion OLA and an output connection portion OLB, and the output main body portion OLA and the output connection portion OLB are an integral structure connected to each other.
  • the output body portion OLA extends in the second direction D2
  • the output connection portion OLB extends in the first direction D1 .
  • the orthographic projection of the output line OL in FIG. 6A on the substrate at least partially overlaps the orthographic projection of the active connection portion on the substrate and is connected to the active connection portion through a via.
  • the second plates C2 of the capacitors of adjacent sub-pixels located in the same row are electrically connected.
  • the second electrode plate C2 of the capacitor includes: a capacitor body 50, a first capacitor connecting portion 51, a second capacitor connecting portion 52, and a third capacitor connecting portion 53.
  • the first capacitor connecting portion 51 and the second capacitor connecting portion 52 are respectively located on both sides of the capacitor body 50, and in the first direction D1, the third capacitor connecting portion 53 is located on a side of the capacitor body 50 close to the first initial signal line.
  • the outline of the capacitor body 50 can be rectangular, and the corners of the rectangle can be chamfered, and the positive projection of the capacitor body 50 on the substrate overlaps at least partially with the positive projection of the first plate of the capacitor on the substrate.
  • An opening K is provided on the capacitor body 50, and the shape of the opening K can be any shape, and can be located in the middle of the capacitor body 50, so that the capacitor body 50 forms a ring structure.
  • the opening K exposes the third insulating layer covering the first plate, and the positive projection of the first plate on the substrate includes the positive projection of the opening K on the substrate.
  • the opening K is configured to expose the first plate of the capacitor, so that the second pole of the first transistor (also the first pole of the second transistor) formed subsequently is connected to the first plate of the capacitor.
  • the first capacitor connection portion of the present sub-pixel is electrically connected to the second capacitor connection portion of one of the adjacent sub-pixels located in the same row, and the second capacitor connection portion of the present sub-pixel is electrically connected to the first capacitor connection portion of another adjacent sub-pixel located in the same row.
  • an orthographic projection of the third capacitor connection portion on the substrate at least partially overlaps an orthographic projection of the capacitance of the second transistor on the substrate.
  • the first initial signal line INIT1 may be located on a side of the second plate C2 of the capacitor of the current sub-pixel close to the sub-pixel of the previous row.
  • the positive projection of the first initial signal line INIT1 on the substrate is located between the positive projection of the reset signal line on the substrate and the positive projection of the scan signal line on the substrate.
  • the first initial signal line INIT1 includes: an initial signal main body 41, a first initial connection block 42, and a second initial connection block 43.
  • the first initial connection block 42 and the second initial connection block 43 are electrically connected to the initial signal main body 41, respectively.
  • the first initial connection block 42 is located on a side of the initial signal main body 41 away from the second electrode plate of the capacitor, and the second initial connection block 43 is located on a side of the initial signal main body 41 close to the second electrode plate C2 of the capacitor.
  • the shape of the initial signal main body 41 can be a line shape extending along the second direction D2.
  • the first initial connection block 42 and the second initial connection block 43 can be equivalent to shielding electrodes, which are configured to effectively shield the influence of data voltage jumps on key nodes in the pixel circuit, prevent the data voltage jumps from affecting the potential of key nodes of the pixel driving circuit, and improve the display effect.
  • the second initial signal line INIT2 may be in the shape of a line extending along the second direction D2, and the second initial signal line INIT2 connected to the sub-pixels of the current row may be located on a side of the second electrode plate of the capacitor of the current sub-pixel close to the sub-pixels of the next row.
  • the orthographic projection of the second initial signal line INIT2 connected to the sub-pixels of the current row on the substrate is located between the orthographic projection of the light emitting signal line connected to the sub-pixels of the current row on the substrate and between the orthographic projection of the reset signal line connected to the sub-pixels of the next row on the substrate.
  • the second plate C2 of the capacitor includes a capacitor body 50, a first capacitor connecting portion 51 and a second capacitor connecting portion 52.
  • the first capacitor connecting portion 51 and the second capacitor connecting portion 52 are respectively located on both sides of the capacitor body 50.
  • the outline of the capacitor body 50 can be rectangular, and the corners of the rectangle can be chamfered, and the positive projection of the capacitor body 50 on the substrate overlaps at least partially with the positive projection of the first plate of the capacitor on the substrate.
  • An opening K is provided on the capacitor body 50, and the shape of the opening K can be any shape, and can be located in the middle of the capacitor body 50, so that the capacitor body 50 forms a ring structure.
  • the opening K exposes the third insulating layer covering the first plate, and the positive projection of the first plate on the substrate includes the positive projection of the opening K on the substrate.
  • the opening K is configured to expose the first plate of the capacitor, so that the second pole of the first transistor (also the first pole of the second transistor) formed subsequently is connected to the first plate of the capacitor.
  • the first capacitor connection portion of the present sub-pixel is electrically connected to the second capacitor connection portion of one of the adjacent sub-pixels located in the same row, and the second capacitor connection portion of the present sub-pixel is electrically connected to the first capacitor connection portion of another adjacent sub-pixel located in the same row.
  • the shape of the first initial signal line INIT1 may be a line extending along the second direction D2, and the first initial signal line INIT1 may be located on a side of the second electrode plate C2 of the capacitor of the present sub-pixel close to the sub-pixel in the previous row.
  • the positive projection of the first initial signal line INIT1 on the substrate is located on a side of the positive projection of the reset signal line on the substrate away from the positive projection of the scan signal line on the substrate.
  • the shielding electrode SL may be in an “n” shape.
  • the shielding electrode SL is located between the first initial signal line INT1 and the second plate C2 of the capacitor.
  • the orthographic projection of the shielding electrode SL on the substrate at least partially overlaps with the orthographic projections of the active layer of the first transistor and the active layer of the second transistor on the substrate, and is located between the orthographic projections of the reset signal line on the substrate and the orthographic projections of the scan signal line on the substrate. It is configured to effectively shield the influence of data voltage jump on key nodes in the pixel circuit, avoid the influence of data voltage jump on the potential of key nodes of the pixel driving circuit, and improve the display effect.
  • the shape of the second initial signal line INIT2 may be a line shape extending along the second direction D2, and the second initial signal line INIT2 connected to the sub-pixels of the current row may be located at the second electrode plate C2 of the capacitor close to the sub-pixels of the next row.
  • the positive projection of the second initial signal line INIT2 connected to the sub-pixels of the current row on the substrate is located between the positive projection of the scanning signal line connected to the sub-pixels of the current row on the substrate and the positive projection of the first initial signal line connected to the sub-pixels of the next row on the substrate.
  • a third insulating layer pattern comprising: depositing a third insulating film on a substrate having the aforementioned pattern formed thereon, and composing the third insulating film through a patterning process to form a third insulating layer pattern covering the aforementioned structure, wherein the third insulating layer is provided with a plurality of via patterns, as shown in FIGS. 24, 25, 44 and 45, wherein FIG. 24 is a schematic diagram of FIG. 5A after the third insulating layer pattern is formed, FIG. 25 is a schematic diagram of FIG. 6A after the third insulating layer pattern is formed, FIG. 44 is a schematic diagram of FIG. 7B after the third insulating layer pattern is formed, and FIG. 45 is a schematic diagram of FIG. 7C after the third insulating layer pattern is formed.
  • the plurality of via hole patterns in FIG. 5A may include at least: a first via hole V1 to a fifty-seventh via hole V57 .
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the active layer of the first light-emitting transistor, and the first via hole V1 is configured to connect the first electrode of the subsequently formed first light-emitting transistor to the first region of the active layer of the first light-emitting transistor through the via hole.
  • the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the first light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the active layer of the first light-emitting transistor, and the second via hole V2 is configured to connect the second electrode of the first light-emitting transistor (also the second electrode of the fourth light-emitting transistor) to be subsequently formed to the second region of the active layer of the first light-emitting transistor through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the second light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first area of the active layer of the second light-emitting transistor, and the third via hole V3 is configured to connect the first electrode of the subsequently formed second light-emitting transistor to the first area of the active layer of the second light-emitting transistor through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the second light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the active layer of the second light-emitting transistor, and the fourth via hole V4 is configured to connect the second electrode of the subsequently formed second light-emitting transistor (also the second electrode of the third light-emitting transistor) to the second region of the active layer of the second light-emitting transistor through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the third light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of the active layer of the third light-emitting transistor, and the fifth via hole V5 is configured to connect the first electrode of the subsequently formed third light-emitting transistor (which is also the first electrode of the tenth light-emitting transistor) to the first area of the active layer of the third light-emitting transistor through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the third light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the sixth via hole V6 are etched away, exposing the surface of the second region of the active layer of the third light-emitting transistor, and the sixth via hole V6 is It is configured so that the second electrode of the second light emitting transistor (also the second electrode of the third light emitting transistor) formed subsequently is connected to the second region of the active layer of the third light emitting transistor through the via hole.
  • the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the fourth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the second region of the active layer of the fourth light-emitting transistor, and the seventh via hole V7 is configured to connect the second electrode of the subsequently formed first light-emitting transistor (also the second electrode of the fourth light-emitting transistor) to the second region of the active layer of the fourth light-emitting transistor through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fifth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the eighth via hole V8 are etched away to expose the surface of the first area of the active layer of the fifth light-emitting transistor, and the eighth via hole V8 is configured to connect the first electrode of the subsequently formed fifth light-emitting transistor to the first area of the active layer of the fifth light-emitting transistor through the via hole.
  • the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the sixth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the first area of the active layer of the sixth light-emitting transistor, and the ninth via hole V9 is configured to connect the first electrode of the subsequently formed sixth light-emitting transistor to the first area of the active layer of the sixth light-emitting transistor through the via hole.
  • the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the sixth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the tenth via hole V10 are etched away to expose the surface of the second region of the active layer of the sixth light-emitting transistor, and the tenth via hole V10 is configured to connect the second electrode of the subsequently formed sixth light-emitting transistor (which is also the first electrode of the seventh light-emitting transistor) to the second region of the active layer of the sixth light-emitting transistor through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the seventh light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first area of the active layer of the seventh light-emitting transistor, and the eleventh via hole V11 is configured to connect the second electrode of the subsequently formed sixth light-emitting transistor (which is also the first electrode of the seventh light-emitting transistor) to the first area of the active layer of the seventh light-emitting transistor through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the seventh light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second region of the active layer of the seventh light-emitting transistor, and the twelfth via hole V12 is configured to connect the second electrode of the subsequently formed seventh light-emitting transistor (which is also the second electrode of the eighth light-emitting transistor) to the second region of the active layer of the seventh light-emitting transistor through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the eighth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first area of the active layer of the eighth light-emitting transistor, and the thirteenth via hole V13 is configured to connect the first electrode of the subsequently formed eighth light-emitting transistor (which is also the first electrode of the ninth light-emitting transistor) to the first area of the active layer of the eighth light-emitting transistor through the via hole.
  • the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eighth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the second region of the active layer of the eighth light-emitting transistor, and the fourteenth via hole V14 is configured to connect the second electrode of the subsequently formed seventh light-emitting transistor (which is also the second electrode of the eighth light-emitting transistor) to the second region of the active layer of the eighth light-emitting transistor through the via hole.
  • the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the ninth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the first area of the active layer of the ninth light-emitting transistor, and the fifteenth via hole V15 is configured to connect the first electrode of the subsequently formed eighth light-emitting transistor (which is also the first electrode of the ninth light-emitting transistor) to the first area of the active layer of the ninth light-emitting transistor through the via hole.
  • the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the ninth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the sixteenth via hole V16 are etched away to expose the surface of the second region of the active layer of the ninth light-emitting transistor, and the sixteenth via hole V16 is configured to connect the second electrode of the subsequently formed ninth light-emitting transistor to the second region of the active layer of the ninth light-emitting transistor through the via hole.
  • the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the tenth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the seventeenth via hole V17 are etched away to expose the surface of the first area of the active layer of the tenth light-emitting transistor, and the seventeenth via hole V17 is configured to connect the first electrode of the subsequently formed tenth light-emitting transistor to the first area of the active layer of the tenth light-emitting transistor through the via hole.
  • the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the tenth light-emitting transistor on the substrate, the first insulating layer and the second insulating layer in the eighteenth via hole V18 are etched away to expose the surface of the second region of the active layer of the tenth light-emitting transistor, and the eighteenth via hole V18 is configured to connect the second electrode of the subsequently formed tenth light-emitting transistor to the second region of the active layer of the tenth light-emitting transistor through the via hole.
  • the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the gate electrode of the first light-emitting transistor (also the gate electrode of the third light-emitting transistor) on the substrate, the second insulating layer in the nineteenth via hole V19 is etched away to expose the surface of the gate electrode of the first light-emitting transistor (also the gate electrode of the third light-emitting transistor), and the nineteenth via hole V19 is configured to connect the first electrode of the second light-emitting transistor subsequently formed and one of the first light-emitting clock signal line and the second light-emitting clock signal line to the gate electrode of the first light-emitting transistor (also the gate electrode of the third light-emitting transistor) through the via hole.
  • the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the gate electrode of the fourth light-emitting transistor on the substrate, the second insulating layer in the twentieth via hole V20 is etched away to expose the surface of the gate electrode of the fourth light-emitting transistor, and the twentieth via hole V20 is configured to connect the other of the subsequently formed first light-emitting clock signal line and the second light-emitting clock signal line to the gate electrode of the fourth light-emitting transistor through the via hole.
  • the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the gate electrode of the fifth light-emitting transistor (also the gate electrode of the sixth light-emitting transistor and the first electrode plate of the first light-emitting capacitor) on the substrate, and the second insulating layer in the twenty-first via hole V21 is etched away to expose the surface of the gate electrode of the fifth light-emitting transistor (also the gate electrode of the sixth light-emitting transistor and the first electrode plate of the first light-emitting capacitor), and the twenty-first via hole V21 is configured to connect the second electrode of the subsequently formed second light-emitting transistor (also the second electrode of the third light-emitting transistor) to the gate electrode of the fifth light-emitting transistor (also the gate electrode of the sixth light-emitting transistor and the first electrode plate of the first light-emitting capacitor) through the via hole.
  • the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the gate electrode of the seventh light-emitting transistor on the substrate, the second insulating layer in the twenty-second via hole V22 is etched away to expose the surface of the gate electrode of the seventh light-emitting transistor, and the twenty-second via hole V22 is configured to allow the other of the first light-emitting clock signal line and the second light-emitting clock signal line to be formed subsequently to pass through the via hole and connect to the seventh light-emitting transistor. Gate electrode connection of the body tube.
  • the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the gate electrode of the ninth light-emitting transistor (also the first electrode plate of the second light-emitting capacitor) on the substrate, and the second insulating layer in the twenty-third via hole V23 is etched away to expose the surface of the gate electrode of the ninth light-emitting transistor (also the first electrode plate of the second light-emitting capacitor), and the twenty-third via hole V23 is configured to connect the second electrode of the subsequently formed seventh light-emitting transistor (also the second electrode of the eighth light-emitting transistor) to the gate electrode of the ninth light-emitting transistor (also the first electrode plate of the second light-emitting capacitor) through the via hole.
  • the orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the second electrode plate of the first light-emitting capacitor on the substrate, exposing the surface of the second electrode plate of the first light-emitting capacitor, and the twenty-fourth via hole V24 is configured to connect the second electrode of the subsequently formed sixth light-emitting transistor (which is also the first electrode of the seventh light-emitting transistor) to the second electrode plate of the first light-emitting capacitor through the via hole.
  • the orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the second electrode plate of the second light-emitting capacitor on the substrate, exposing the surface of the second electrode plate of the second light-emitting capacitor, and the twenty-fifth via hole V25 is configured to connect the first electrode of the subsequently formed eighth light-emitting transistor (which is also the first electrode of the ninth light-emitting transistor) to the second electrode plate of the second light-emitting capacitor through the via hole.
  • the orthographic projection of the twenty-sixth via hole V26 on the substrate is located within the range of the orthographic projection of the second electrode plate of the third light-emitting capacitor on the substrate, exposing the surface of the second electrode plate of the third light-emitting capacitor, and the twenty-sixth via hole V26 is configured to connect the first electrode of the subsequently formed sixth light-emitting transistor to the second electrode plate of the third light-emitting capacitor through the via hole.
  • the orthographic projection of the twenty-seventh via hole V27 on the substrate is located within the range of the orthographic projection of the output main body portion of the output line on the substrate, exposing the surface of the output main body portion of the output line, and the twenty-seventh via hole V27 is configured to connect a subsequently formed second connecting line to the output main body portion of the output line through the via hole.
  • the orthographic projection of the twenty-eighth via hole V28 on the substrate is located within the range of the orthographic projection of the output connection portion of the output line on the substrate, exposing the surface of the output connection portion of the output line, and the twenty-eighth via hole V28 is configured to connect the second electrode of the subsequently formed first release transistor (also the second electrode of the second release transistor) to the output connection portion of the output line through the via hole.
  • the orthographic projection of the twenty-ninth via hole V29 on the substrate is located within the range of the orthographic projection of the output connection line on the substrate, exposing the surface of the output connection line, and the twenty-ninth via hole V29 is configured to connect the second electrode of the subsequently formed ninth light-emitting transistor and the second electrode of the tenth light-emitting transistor to the output connection line through the via hole.
  • the orthographic projection of the thirtieth via hole V30 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the first release transistor on the substrate, the first insulating layer and the second insulating layer in the thirtieth via hole V30 are etched away to expose the surface of the first area of the active layer of the first release transistor, and the thirtieth via hole V30 is configured to connect the first electrode (also the second light-emitting power line) of the subsequently formed first release transistor to the first area of the active layer of the first release transistor through the via hole.
  • the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the first release transistor (also the second area of the active layer of the second release transistor) on the substrate, the first insulating layer and the second insulating layer in the thirty-first via hole V31 are etched away to expose the surface of the second area of the active layer of the first release transistor (also the second area of the active layer of the second release transistor), and the thirty-first via hole V31 is configured to connect the second electrode of the subsequently formed first release transistor (also the second electrode of the second release transistor) to the second area of the active layer of the first release transistor (also the second area of the active layer of the second release transistor) through the via hole.
  • the orthographic projection of the thirty-second via hole V32 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the second release transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-second via hole V32 are etched away to expose the surface of the first area of the active layer of the second release transistor, and the thirty-second via hole V32 is configured to connect the first electrode of the subsequently formed second release transistor to the first area of the active layer of the second release transistor through the via hole.
  • the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the gate electrode of the first release transistor on the substrate, the second insulating layer in the thirty-third via V33 is etched away to expose the surface of the gate electrode of the first release transistor, and the thirty-third via V33 is configured to connect the second electrode of the first release transistor (also the second electrode of the second release transistor) to be formed subsequently to the gate electrode of the first release transistor through the via.
  • the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the gate electrode of the first release transistor on the substrate, the second insulating layer in the thirty-fourth via V34 is etched away to expose the surface of the gate electrode of the first release transistor, and the thirty-fourth via V34 is configured to connect the first electrode (also the first scanning power line) of the subsequently formed second release transistor to the gate electrode of the second release transistor through the via.
  • the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the first scanning transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-fifth via V35 are etched away to expose the surface of the first area of the active layer of the first scanning transistor, and the thirty-fifth via V35 is configured to connect the first electrode of the subsequently formed first scanning transistor to the first area of the active layer of the first scanning transistor through the via.
  • the orthographic projection of the thirty-sixth via V36 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the first scanning transistor (also the second area of the active layer of the seventh scanning transistor) on the substrate, the first insulating layer and the second insulating layer in the thirty-sixth via V36 are etched away to expose the surface of the second area of the active layer of the first scanning transistor (also the second area of the active layer of the seventh scanning transistor), and the thirty-sixth via V36 is configured to connect the second electrode of the subsequently formed first scanning transistor (also the second electrode of the seventh scanning transistor) to the second area of the active layer of the first scanning transistor (also the second area of the active layer of the seventh scanning transistor) through the via.
  • the orthographic projection of the thirty-seventh via V37 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the second scanning transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-seventh via V37 are etched away to expose the surface of the first area of the active layer of the second scanning transistor, and the thirty-seventh via V37 is configured to connect the first electrode of the subsequently formed second scanning transistor to the first area of the active layer of the second scanning transistor through the via.
  • the orthographic projection of the thirty-eighth via hole V38 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the second scanning transistor (also the second area of the active layer of the third scanning transistor) on the substrate, the first insulating layer and the second insulating layer in the thirty-eighth via hole V38 are etched away to expose the surface of the second area of the active layer of the second scanning transistor (also the second area of the active layer of the third scanning transistor), and the thirty-eighth via hole V38 is configured to connect the second electrode of the subsequently formed second scanning transistor (also the second electrode of the third scanning transistor) to the second area of the active layer of the second scanning transistor (also the second area of the active layer of the third scanning transistor) through the via hole.
  • the orthographic projection of the thirty-ninth via hole V39 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the third scanning transistor on the substrate, and the first insulating layer and the second insulating layer in the thirty-ninth via hole V39 are etched away to expose the surface of the first region of the active layer of the third scanning transistor.
  • the nineteenth via hole V39 is configured to connect the first electrode (also the second scan power line) of the third scan transistor formed subsequently to the first region of the active layer of the third scan transistor through the via hole.
  • the orthographic projection of the 40th via hole V40 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fourth scanning transistor on the substrate, the first insulating layer and the second insulating layer in the 40th via hole V40 are etched away to expose the surface of the first area of the active layer of the fourth scanning transistor, and the 40th via hole V40 is configured to connect the first electrode of the subsequently formed fourth scanning transistor to the first area of the active layer of the fourth scanning transistor through the via hole.
  • the orthographic projection of the forty-first via V41 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the fourth scanning transistor (the second area of the active layer of the fifth scanning transistor) on the substrate, the first insulating layer and the second insulating layer in the forty-first via V41 are etched away to expose the surface of the second area of the active layer of the fourth scanning transistor (the second area of the active layer of the fifth scanning transistor), and the forty-first via V41 is configured to connect the second electrode of the subsequently formed fourth scanning transistor (also the second electrode of the fifth scanning transistor) to the second area of the active layer of the fourth scanning transistor (the second area of the active layer of the fifth scanning transistor) through the via.
  • the orthographic projection of the forty-second via hole V42 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fifth scanning transistor on the substrate, the first insulating layer and the second insulating layer in the forty-second via hole V42 are etched away to expose the surface of the first area of the active layer of the fifth scanning transistor, and the forty-second via hole V42 is configured to connect the first electrode of the subsequently formed fifth scanning transistor to the first area of the active layer of the fifth scanning transistor through the via hole.
  • the orthographic projection of the forty-third via V43 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the sixth scanning transistor on the substrate, the first insulating layer and the second insulating layer in the forty-third via V43 are etched away to expose the surface of the first area of the active layer of the sixth scanning transistor, and the forty-third via V43 is configured to connect the first electrode of the subsequently formed sixth scanning transistor to the first area of the active layer of the sixth scanning transistor through the via.
  • the orthographic projection of the forty-fourth via V44 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the eighth scanning transistor on the substrate, the first insulating layer and the second insulating layer in the forty-fourth via V44 are etched away to expose the surface of the first area of the active layer of the eighth scanning transistor, and the forty-fourth via V44 is configured to connect the first electrode of the subsequently formed eighth scanning transistor to the first area of the active layer of the eighth scanning transistor through the via.
  • the orthographic projection of the forty-fifth via hole V45 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eighth scanning transistor on the substrate, the first insulating layer and the second insulating layer in the forty-fifth via hole V45 are etched away to expose the surface of the second region of the active layer of the eighth scanning transistor, and the forty-fifth via hole V45 is configured to connect the second electrode of the subsequently formed eighth scanning transistor to the second region of the active layer of the eighth scanning transistor through the via hole.
  • the orthographic projection of the forty-sixth via V46 on the substrate is located within the range of the orthographic projection of the gate electrode of the first scanning transistor (also the gate electrode of the third scanning transistor) on the substrate, the second insulating layer in the forty-sixth via V46 is etched away to expose the surface of the gate electrode of the first scanning transistor (also the gate electrode of the third scanning transistor), and the forty-sixth via V46 is configured to connect the first electrode of the second scanning transistor subsequently formed and one of the first scanning clock signal line and the second scanning clock signal line to the gate electrode of the first scanning transistor (also the gate electrode of the third scanning transistor) through the via.
  • the positive projection of the forty-seventh via hole V47 on the substrate is located within the range of the positive projection of the gate electrode of the second scanning transistor on the substrate, the second insulating layer in the forty-seventh via hole V47 is etched away to expose the surface of the gate electrode of the fourth scanning transistor, and the forty-seventh via hole V47 is configured to allow subsequent
  • the second electrode of the first scanning transistor (also the second electrode of the seventh scanning transistor) and the first electrode of the eighth scanning transistor are connected to the gate electrode of the second scanning transistor through the via hole.
  • the orthographic projection of the forty-eight via hole V48 on the substrate is located within the range of the orthographic projection of the gate electrode of the fourth scanning transistor (also the gate electrode of the sixth scanning transistor and the first plate of the first scanning capacitor) on the substrate, the second insulating layer in the forty-eight via hole V48 is etched away to expose the surface of the gate electrode of the fourth scanning transistor (also the gate electrode of the sixth scanning transistor and the first plate of the first scanning capacitor), and the forty-eight via hole V48 is configured to connect the second electrode of the subsequently formed second scanning transistor (also the second electrode of the third scanning transistor) to the gate electrode of the fourth scanning transistor (also the gate electrode of the sixth scanning transistor and the first plate of the first scanning capacitor) through the via hole.
  • the orthographic projection of the forty-ninth via V49 on the substrate is located within the range of the orthographic projection of the gate electrode of the fifth scanning transistor (also the first plate of the second scanning capacitor) on the substrate, the second insulating layer in the forty-ninth via V49 is etched away to expose the surface of the gate electrode of the fifth scanning transistor (also the first plate of the second scanning capacitor), and the forty-ninth via V49 is configured to connect the second electrode of the subsequently formed eighth scanning transistor to the gate electrode of the fifth scanning transistor (also the first plate of the second scanning capacitor) through the via.
  • the orthographic projection of the fiftieth via hole V50 on the substrate is located within the range of the orthographic projection of the gate electrode of the seventh scanning transistor on the substrate, the second insulating layer in the fiftieth via hole V50 is etched away to expose the surface of the gate electrode of the seventh scanning transistor, and the fiftieth via hole V50 is configured to connect the first electrode of the subsequently formed fifth light-emitting transistor and the other of the first scanning clock signal line and the second scanning clock signal line to the gate electrode of the seventh scanning transistor through the via hole.
  • the orthographic projection of the fifty-first via V51 on the substrate is located within the range of the orthographic projection of the gate electrode of the eighth scanning transistor on the substrate, the second insulating layer in the fifty-first via V51 is etched away to expose the surface of the gate electrode of the eighth scanning transistor, and the fifty-first via V51 is configured to connect a subsequently formed second scanning power line to the gate electrode of the eighth scanning transistor through the via.
  • the orthographic projection of the fifty-second via V52 on the substrate is located within the range of the orthographic projection of the second plate of the first scanning capacitor on the substrate, exposing the surface of the second plate of the first scanning capacitor, and the fifty-second via V52 is configured to connect the first electrode of the subsequently formed fourth scanning transistor and the first electrode of the sixth scanning transistor to the second plate of the first scanning capacitor through the via.
  • the orthographic projection of the fifty-third via V53 on the substrate is located within the range of the orthographic projection of the second plate of the second scanning capacitor on the substrate, exposing the surface of the second plate of the second scanning capacitor, and the fifty-third via V53 is configured to connect the second electrode of the subsequently formed fourth scanning transistor (which is also the second electrode of the fifth scanning transistor) to the second plate of the second scanning capacitor through the via.
  • the orthographic projection of the fifty-fourth via V54 on the substrate is located within the range of the orthographic projection of the third signal connection line on the substrate, exposing the surface of the third signal connection line, and the fifty-fourth via V54 is configured to connect the second electrode of the first scanning transistor of the scanning shift register of the current level formed subsequently and the second electrode of the fourth scanning transistor of the scanning shift register of the previous level (also the second electrode of the fifth scanning transistor) to the third signal connection line through the via.
  • the orthographic projection of the fifty-fifth via V55 on the substrate is located within the range of the orthographic projection of the scan output signal line on the substrate, exposing the surface of the scan output signal line, and the fifty-fifth via V55 is configured to connect a subsequently formed first connecting line to the scan output signal line through the via.
  • the orthographic projection of the fifty-sixth via hole V56 on the substrate is located within the range of the orthographic projection of the first signal connection line on the substrate, the second insulating layer in the fifty-sixth via hole V56 is etched away to expose the surface of the first signal connection line, and the fifty-sixth via hole V56 is configured to allow the first initial power supply line to be formed subsequently.
  • the line is connected to the first signal connection line through the via hole.
  • the orthographic projection of the fifty-seventh via V57 on the substrate is located within the range of the orthographic projection of the second signal connection line on the substrate, the second insulating layer in the fifty-seventh via V57 is etched away to expose the surface of the second signal connection line, and the fifty-seventh via V57 is configured to connect a subsequently formed second initial power supply line to the second signal connection line through the via.
  • the plurality of via hole patterns of the display substrate provided in FIG. 6A may include at least: a first via hole V1 to a fifty-sixth via hole V56 .
  • first to twenty-sixth via holes V1 to V26 in FIG. 6A are the same as the first to twenty-sixth via holes V1 to V26 in the display substrate provided in FIG. 5A , and are not described again herein.
  • the orthographic projection of the twenty-seventh via hole V27 on the substrate is located within the range of the orthographic projection of the output line on the substrate, exposing the surface of the output line, and the twenty-seventh via hole V27 is configured to connect a subsequently formed second connecting line to the output line through the via hole.
  • the orthographic projection of the twenty-eighth via hole V28 on the substrate is located within the range of the orthographic projection of the output connection line on the substrate, exposing the surface of the output connection line, and the twenty-eighth via hole V28 is configured to connect the second electrode of the subsequently formed ninth light-emitting transistor and the second electrode of the tenth light-emitting transistor to the output connection line through the via hole.
  • the orthographic projection of the twenty-ninth via V29 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the first release transistor on the substrate, the first insulating layer and the second insulating layer in the twenty-ninth via V29 are etched away to expose the surface of the first area of the active layer of the first release transistor, and the twenty-ninth via V29 is configured to connect the first electrode (also the second light-emitting power line) of the subsequently formed first release transistor to the first area of the active layer of the first release transistor through the via.
  • the orthographic projection of the thirtieth via hole V30 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the first release transistor (also the second area of the active layer of the second release transistor) on the substrate, the first insulating layer and the second insulating layer in the thirtieth via hole V30 are etched away to expose the surface of the second area of the active layer of the first release transistor (also the second area of the active layer of the second release transistor), and the thirtieth via hole V30 is configured to connect the second electrode of the first release transistor (also the second area of the active layer of the second release transistor) to be subsequently formed with the second area of the active layer of the first release transistor (also the second area of the active layer of the second release transistor) through the via hole.
  • the orthographic projection of the thirty-first via V31 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the second release transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-first via V312 are etched away to expose the surface of the first area of the active layer of the second release transistor, and the thirty-first via V31 is configured to connect the first electrode of the subsequently formed second release transistor to the first area of the active layer of the second release transistor through the via.
  • the orthographic projection of the thirty-second via V32 on the substrate is within the range of the orthographic projection of the gate electrode of the first release transistor on the substrate, the second insulating layer in the thirty-second via V32 is etched away to expose the surface of the gate electrode of the first release transistor, and the thirty-second via V32 is configured to connect the second electrode of the subsequently formed first release transistor (which is also the second region of the active layer of the second release transistor) to the gate electrode of the first release transistor through the via.
  • the orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the gate electrode of the first release transistor on the substrate, the second insulating layer in the thirty-third via hole V33 is etched away to expose the surface of the gate electrode of the first release transistor, and the thirty-third via hole V33 is configured to allow the first electrode (also the first scanning power line) of the second release transistor to be formed subsequently to pass through the via hole and connect to the gate electrode of the second release transistor. Gate electrode connection.
  • the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the first scanning transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-fourth via V34 are etched away to expose the surface of the first area of the active layer of the first scanning transistor, and the thirty-fifth via V35 is configured to connect the first electrode of the subsequently formed first scanning transistor to the first area of the active layer of the first scanning transistor through the via.
  • the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the first scanning transistor (also the second area of the active layer of the seventh scanning transistor) on the substrate, the first insulating layer and the second insulating layer in the thirty-fifth via V35 are etched away to expose the surface of the second area of the active layer of the first scanning transistor (also the second area of the active layer of the seventh scanning transistor), and the thirty-fifth via V35 is configured to connect the second electrode of the first scanning transistor (also the second electrode of the seventh scanning transistor) to be subsequently formed with the second area of the active layer of the first scanning transistor (also the second area of the active layer of the seventh scanning transistor) through the via.
  • the orthographic projection of the thirty-sixth via V36 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the second scanning transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-sixth via V36 are etched away to expose the surface of the first area of the active layer of the second scanning transistor, and the thirty-sixth via V36 is configured to connect the first electrode of the subsequently formed second scanning transistor to the first area of the active layer of the second scanning transistor through the via.
  • the orthographic projection of the thirty-seventh via V37 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the second scanning transistor (also the second area of the active layer of the third scanning transistor) on the substrate, the first insulating layer and the second insulating layer in the thirty-seventh via V37 are etched away to expose the surface of the second area of the active layer of the second scanning transistor (also the second area of the active layer of the third scanning transistor), and the thirty-seventh via V37 is configured to connect the second electrode of the subsequently formed second scanning transistor (also the second electrode of the third scanning transistor) to the second area of the active layer of the second scanning transistor (also the second area of the active layer of the third scanning transistor) through the via.
  • the orthographic projection of the thirty-eighth via hole V38 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the third scanning transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-eighth via hole V38 are etched away to expose the surface of the first area of the active layer of the third scanning transistor, and the thirty-eighth via hole V38 is configured to connect the first electrode (also the second scanning power line) of the subsequently formed third scanning transistor to the first area of the active layer of the third scanning transistor through the via hole.
  • the orthographic projection of the thirty-ninth via V39 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fourth scanning transistor on the substrate, the first insulating layer and the second insulating layer in the thirty-ninth via V39 are etched away to expose the surface of the first area of the active layer of the fourth scanning transistor, and the thirty-ninth via V39 is configured to connect the first electrode of the subsequently formed fourth scanning transistor to the first area of the active layer of the fourth scanning transistor through the via.
  • the orthographic projection of the 40th via V40 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the fourth scanning transistor (the second area of the active layer of the fifth scanning transistor) on the substrate, the first insulating layer and the second insulating layer in the 40th via V40 are etched away to expose the surface of the second area of the active layer of the fourth scanning transistor (the second area of the active layer of the fifth scanning transistor), and the 40th via V40 is configured to connect the second electrode of the subsequently formed fourth scanning transistor (also the second electrode of the fifth scanning transistor) to the second area of the active layer of the fourth scanning transistor (the second area of the active layer of the fifth scanning transistor) through the via.
  • the orthographic projection of the forty-first via hole V41 on the substrate is located at the fifth
  • the first area of the active layer of the scanning transistor is within the range of the positive projection on the substrate
  • the first insulating layer and the second insulating layer in the forty-first via V41 are etched away to expose the surface of the first area of the active layer of the fifth scanning transistor
  • the forty-first via V41 is configured to connect the first electrode of the subsequently formed fifth scanning transistor to the first area of the active layer of the fifth scanning transistor through the via.
  • the orthographic projection of the forty-second via V42 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the sixth scanning transistor on the substrate, the first insulating layer and the second insulating layer in the forty-second via V42 are etched away to expose the surface of the first area of the active layer of the sixth scanning transistor, and the forty-second via V423 is configured to connect the first electrode of the subsequently formed sixth scanning transistor to the first area of the active layer of the sixth scanning transistor through the via.
  • the orthographic projection of the forty-third via V43 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the eighth scanning transistor on the substrate, the first insulating layer and the second insulating layer in the forty-third via V43 are etched away to expose the surface of the first area of the active layer of the eighth scanning transistor, and the forty-third via V43 is configured to connect the first electrode of the subsequently formed eighth scanning transistor to the first area of the active layer of the eighth scanning transistor through the via.
  • the orthographic projection of the forty-fourth via V44 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eighth scanning transistor on the substrate, the first insulating layer and the second insulating layer in the forty-fourth via V44 are etched away to expose the surface of the second region of the active layer of the eighth scanning transistor, and the forty-fourth via V44 is configured to connect the second electrode of the subsequently formed eighth scanning transistor to the second region of the active layer of the eighth scanning transistor through the via.
  • the orthographic projection of the forty-fifth via V45 on the substrate is located within the range of the orthographic projection of the gate electrode of the first scanning transistor (also the gate electrode of the third scanning transistor) on the substrate, the second insulating layer in the forty-fifth via V45 is etched away to expose the surface of the gate electrode of the first scanning transistor (also the gate electrode of the third scanning transistor), and the forty-fifth via V45 is configured to connect the first electrode of the second scanning transistor formed subsequently and one of the first scanning clock signal line and the second scanning clock signal line to the gate electrode of the first scanning transistor (also the gate electrode of the third scanning transistor) through the via.
  • the orthographic projection of the forty-sixth via V46 on the substrate is located within the range of the orthographic projection of the gate electrode of the second scanning transistor on the substrate, the second insulating layer in the forty-sixth via V46 is etched away to expose the surface of the gate electrode of the fourth scanning transistor, and the forty-sixth via V46 is configured to connect the second electrode of the first scanning transistor (also the second electrode of the seventh scanning transistor) and the first electrode of the eighth scanning transistor to be formed subsequently to the gate electrode of the second scanning transistor through the via.
  • the orthographic projection of the forty-seventh via V47 on the substrate is located within the range of the orthographic projection of the gate electrode of the fourth scanning transistor (also the gate electrode of the sixth scanning transistor and the first plate of the first scanning capacitor) on the substrate, the second insulating layer in the forty-seventh via V47 is etched away to expose the surface of the gate electrode of the fourth scanning transistor (also the gate electrode of the sixth scanning transistor and the first plate of the first scanning capacitor), and the forty-seventh via V47 is configured to connect the second electrode of the subsequently formed second scanning transistor (also the second electrode of the third scanning transistor) to the gate electrode of the fourth scanning transistor (also the gate electrode of the sixth scanning transistor and the first plate of the first scanning capacitor) through the via.
  • the orthographic projection of the forty-eight via hole V48 on the substrate is located within the range of the orthographic projection of the gate electrode of the fifth scanning transistor (also the first plate of the second scanning capacitor) on the substrate, the second insulating layer in the forty-eight via hole V48 is etched away to expose the surface of the gate electrode of the fifth scanning transistor (also the first plate of the second scanning capacitor), and the forty-eight via hole V48 is configured to connect the second electrode of the subsequently formed eighth scanning transistor to the gate electrode of the fifth scanning transistor (also the first plate of the second scanning capacitor) through the via hole.
  • the orthographic projection of the forty-ninth via hole V49 on the substrate is located within the range of the orthographic projection of the gate electrode of the seventh scanning transistor on the substrate, the second insulating layer in the forty-ninth via hole V49 is etched away to expose the surface of the gate electrode of the seventh scanning transistor, and the forty-ninth via hole V49 is configured to connect the first electrode of the subsequently formed fifth light-emitting transistor and the other of the first scanning clock signal line and the second scanning clock signal line to the gate electrode of the seventh scanning transistor through the via hole.
  • the orthographic projection of the fiftieth via hole V50 on the substrate is located within the range of the orthographic projection of the gate electrode of the eighth scanning transistor on the substrate, the second insulating layer in the fiftieth via hole V50 is etched away to expose the surface of the gate electrode of the eighth scanning transistor, and the fiftieth via hole V50 is configured to connect a subsequently formed second scanning power line to the gate electrode of the eighth scanning transistor through the via hole.
  • the orthographic projection of the fifty-first via V51 on the substrate is located within the range of the orthographic projection of the second plate of the first scanning capacitor on the substrate, exposing the surface of the second plate of the first scanning capacitor, and the fifty-first via V51 is configured to connect the first electrode of the subsequently formed fourth scanning transistor and the first electrode of the sixth scanning transistor to the second plate of the first scanning capacitor through the via.
  • the orthographic projection of the fifty-second via V52 on the substrate is located within the range of the orthographic projection of the second plate of the second scanning capacitor on the substrate, exposing the surface of the second plate of the second scanning capacitor, and the fifty-second via V52 is configured to connect the second electrode of the subsequently formed fourth scanning transistor (which is also the second electrode of the fifth scanning transistor) to the second plate of the second scanning capacitor through the via.
  • the orthographic projection of the fifty-third via V53 on the substrate is located within the range of the orthographic projection of the third signal connection line on the substrate, exposing the surface of the third signal connection line, and the fifty-third via V53 is configured to connect the second electrode of the first scanning transistor of the scanning shift register of the current level formed subsequently and the second electrode of the fourth scanning transistor of the scanning shift register of the previous level (also the second electrode of the fifth scanning transistor) to the third signal connection line through the via.
  • the orthographic projection of the fifty-fourth via V54 on the substrate is located within the range of the orthographic projection of the scan output signal line on the substrate, exposing the surface of the scan output signal line, and the fifty-fourth via V54 is configured to connect a subsequently formed first connecting line to the scan output signal line through the via.
  • the orthographic projection of the fifty-fifth via V55 on the substrate is located within the range of the orthographic projection of the first signal connection line on the substrate, the second insulating layer in the fifty-fifth via V55 is etched away to expose the surface of the first signal connection line, and the fifty-fifth via V55 is configured to connect a subsequently formed first initial power supply line to the first signal connection line through the via.
  • the orthographic projection of the fifty-sixth via V56 on the substrate is located within the range of the orthographic projection of the second signal connection line on the substrate, the second insulating layer in the fifty-sixth via V56 is etched away to expose the surface of the second signal connection line, and the fifty-sixth via V56 is configured to connect a subsequently formed second initial power supply line to the second signal connection line through the via.
  • the plurality of via hole patterns in FIGS. 7B and 7C may include at least a fifty-eighth via hole V58 to a sixty-seventh via hole V67 .
  • the orthographic projection of the fifty-eight via V58 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the first transistor on the substrate, the first insulating layer and the second insulating layer in the fifty-eight via V58 are etched away to expose the surface of the first area of the active layer of the first transistor, and the fifty-eight via V58 is configured to connect the first electrode of the subsequently formed first transistor to the first area of the active layer of the first transistor through the via.
  • the orthographic projection of the fifty-ninth via hole V59 on the substrate is located at the positive projection of the second region of the active layer of the first transistor (also the first region of the active layer of the second transistor) on the substrate.
  • the first insulating layer and the second insulating layer in the fifty-ninth via V59 are etched away to expose the surface of the second area of the active layer of the first transistor (also the first area of the active layer of the second transistor), and the fifty-ninth via V59 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the second area of the active layer of the first transistor (also the first area of the active layer of the second transistor) through the via.
  • the orthographic projection of the sixtieth via V60 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fourth transistor on the substrate, the first insulating layer and the second insulating layer in the sixtieth via V60 are etched away to expose the surface of the first area of the active layer of the fourth transistor, and the sixtieth via V60 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of the active layer of the fourth transistor through the via.
  • the orthographic projection of the sixty-first via hole V61 on the substrate is within the range of the orthographic projection of the first region of the active layer of the fifth transistor on the substrate, and the first insulating layer and the second insulating layer in the sixty-first via hole V61 are etched away, exposing the surface of the second region of the active layer of the fifth transistor.
  • the sixty-first via hole V61 in FIG. 44 is configured to connect the first electrode of the subsequently formed fifth transistor to the first region of the active layer of the fifth transistor through the via hole.
  • the sixty-first via hole V61 in FIG. 45 is configured to connect the first sub-power line formed subsequently to the first region of the active layer of the fifth transistor through the via hole.
  • the orthographic projection of the sixty-second via V62 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the sixth transistor (the second area of the active layer of the seventh transistor) on the substrate, the first insulating layer and the second insulating layer in the sixty-second via V62 are etched away to expose the surface of the second area of the active layer of the sixth transistor (the second area of the active layer of the seventh transistor), and the sixty-second via V62 is configured to connect the second electrode of the subsequently formed sixth transistor (also the second electrode of the seventh transistor) to the second area of the active layer of the sixth transistor (the second area of the active layer of the seventh transistor) through the via.
  • the orthographic projection of the sixty-third via hole V63 on the substrate is within the range of the orthographic projection of the first region of the active layer of the seventh transistor on the substrate, and the first insulating layer and the second insulating layer in the sixty-third via hole V63 are etched away, exposing the surface of the first region of the active layer of the seventh transistor.
  • the sixty-third via hole V63 in FIG. 44 is configured to connect the first electrode of the subsequently formed seventh transistor to the first region of the active layer of the seventh transistor through the via hole.
  • the sixty-third via hole V63 in FIG. 45 is configured to connect the first electrode of the subsequently formed seventh transistor or the fourth signal connection line to the first region of the active layer of the seventh transistor through the via hole.
  • the orthographic projection of the sixty-fourth via V64 on the substrate is located within the range of the orthographic projection of the gate electrode of the third transistor (also the first plate of the capacitor) on the substrate, the second insulating layer in the sixty-fourth via V64 is etched away to expose the surface of the gate electrode of the third transistor (also the first plate of the capacitor), and the sixty-fourth via V64 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the gate electrode of the third transistor (also the first plate of the capacitor) through the via.
  • the orthographic projection of the sixty-fifth via V65 on the substrate is located within the range of the orthographic projection of the first initial signal line on the substrate, exposing the first initial signal line, and the sixty-fifth via V65 is configured to connect the first electrode of the subsequently formed first transistor to the first initial signal line through the via.
  • the orthographic projection of the sixty-sixth via hole V66 on the substrate is within the range of the orthographic projection of the second plate of the capacitor on the substrate, exposing the surface of the second plate of the capacitor.
  • the sixty-sixth via hole V66 in FIG. 44 is configured to connect the first electrode of the fifth transistor formed subsequently to the second plate of the capacitor through the via hole.
  • the sixty-sixth via hole V66 in FIG. 45 is configured to connect the first sub-power line formed subsequently to the second plate of the capacitor through the via hole.
  • the orthographic projection of the sixty-seventh via hole V67 on the substrate is located within the range of the orthographic projection of the second initial signal line on the substrate, exposing the surface of the second initial signal line.
  • V67 is configured to connect a first electrode of a seventh transistor formed subsequently to the second initial signal line through the via hole.
  • FIG. 26 is a schematic diagram of the third conductive layer pattern of FIGS. 5A and 6A
  • FIG. 27 is a schematic diagram of FIG. 5A after the third conductive layer pattern is formed
  • FIG. 28 is a schematic diagram of FIG. 6A after the third conductive layer pattern is formed
  • FIG. 46 is a schematic diagram of the third conductive layer pattern of FIG. 7B
  • FIG. 47 is a schematic diagram of FIG.
  • FIG. 48 is a schematic diagram of the third conductive layer pattern of 7C
  • FIG. 49 is a schematic diagram of FIG. 7C after the third conductive layer pattern is formed.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer pattern may at least include: a light-emitting initial signal line ESTV, a first light-emitting clock signal line ECK1, a second light-emitting clock signal line ECK2, a first light-emitting power line EVGH, a second light-emitting power line EVGL, a scan initial signal line GSTV, a first sub-clock signal line GCK1A of the first scan clock signal line, a third sub-clock signal line GCK2A of the second scan clock signal line, a first scan power line GVGH, a second scan power line GVGL, a first sub-initial power line INITL1A of the first initial power line, a first sub-initial power line INITL2A of the second initial power line, first to fourth connecting lines CL1 to CL4, first and second electrodes of multiple light-emitting transistors, first and second electrodes of multiple release transistors, and first and second
  • the third conductive layer pattern further includes at least a data link line DL.
  • the third conductive layer pattern further includes at least a first sub-power source VDDA and an electrode connection line CL.
  • the first light-emitting clock signal line ECK1 can be located on the side of the light-emitting initial signal line ESTV close to the display area
  • the second light-emitting clock signal line ECK2 can be located on the side of the first light-emitting clock signal line ECK1 close to the display area
  • the first light-emitting power line EVGH can be located on the side of the second light-emitting clock signal line ECK2 close to the display area
  • the second light-emitting power line EVGL is located on the side of the first light-emitting power line EVGH close to the display area
  • the first scanning power line GVGH is located on the side of the second light-emitting power line EVGL close to the display area
  • the first sub-clock signal line GCK1A of the first scanning clock signal line is located on the side of the first scanning power line GVGH close to the display area
  • the third sub-clock signal line GCK2A of the second scanning clock signal line is located on the side
  • any one of the light-emitting initial signal line ESTV, the first light-emitting clock signal line ECK1, the second light-emitting clock signal line ECK2, the first light-emitting power line EVGH, the second light-emitting power line EVGL, the scan initial signal line GSTV, the first sub-clock signal line GCK1A of the first scan clock signal line, the third sub-clock signal line GCK2A of the second scan clock signal line, the first scan power line GVGH, the second scan power line GVGL, the first sub-initial power line INITL1A of the first initial power line, and the first sub-initial power line INITL2A of the second initial power line extends at least partially along the first direction D1 and is in a line shape.
  • the first electrode ET13 and the second electrode ET14 of the first light emitting transistor to the first electrode ET103 and the second electrode ET104 of the tenth light emitting transistor may be located between the first light emitting power line EVGH and the second light emitting power line EVGL.
  • the first electrode RT11 and the second electrode RT14 of the first release transistor to the first electrode RT21 and the second electrode RT24 of the second release transistor are located between the second light emitting power line EVGL and the first scanning power line GVGH.
  • the first electrode GT13 and the second electrode GT14 of the first scanning transistor to the first electrode GT33 and the second electrode of the third scanning transistor, the first electrode GT63 of the sixth scanning transistor and the second electrode GT74 of the seventh scanning transistor may be located between the scanning initial signal line GSTV and the second scanning power line GVGL, and the first electrode GT43 and the second electrode GT44 of the fourth scanning transistor to the first electrode GT53 and the second electrode GT54 of the fifth scanning transistor and the first electrode GT83 and the second electrode GT84 of the eighth scanning transistor may be located between the second scanning power line GVGL and the first initial power supply line INITL1.
  • an orthographic projection of the second plate of the second scan capacitor on the substrate at least partially overlaps with an orthographic projection of the second scan power line, the first scan clock signal line, the second scan clock signal line, the scan initial signal line and the first scan power line on the substrate.
  • the first and second initial power lines INITL1 and INITL2 are located on a side of the second scan power line GVGL close to the display area, and the first initial power line INITL1 is located on a side of the second initial power line INITL2 close to the display area.
  • the first electrode ET13 of the first light emitting transistor may be in the shape of a bar extending in the first direction D1.
  • the first electrode ET13 of the first light emitting transistor passes through the first region of the active layer of the first light emitting transistor through the first via hole.
  • the second electrode ET14 of the first light emitting transistor and the second electrode ET44 of the fourth light emitting transistor are interconnected as an integral structure, and may be shaped as a strip extending along the first direction D1.
  • the second electrode ET14 of the first light emitting transistor (also the second electrode ET44 of the fourth light emitting transistor) is connected to the second region of the active layer of the first light emitting transistor through the second via hole, and is connected to the second region of the active layer of the fourth light emitting transistor through the seventh via hole.
  • the shape of the first electrode ET23 of the second light-emitting transistor can be a strip extending along the first direction D1
  • the first electrode ET23 of the second light-emitting transistor is connected to the first area of the active layer of the second light-emitting transistor through a third via hole, and is connected to the gate electrode of the first light-emitting transistor (which is also the gate electrode of the third light-emitting transistor) through a nineteenth via hole.
  • the second electrode ET24 of the second light emitting transistor and the second electrode ET34 of the third light emitting transistor are an integrated structure connected to each other, and at least partially extend along the first direction D1, and may be a zigzag shape.
  • the second electrode ET24 of the second light emitting transistor (also the second electrode ET34 of the third light emitting transistor) is connected to the second region of the active layer of the second light emitting transistor through the fourth via hole, connected to the second region of the active layer of the third light emitting transistor through the sixth via hole, and connected to the gate electrode of the fifth light emitting transistor (also the gate electrode of the sixth light emitting transistor and the first electrode plate of the first light emitting capacitor) through the twenty-first via hole.
  • the first electrode ET33 of the third light emitting transistor, the first electrode ET103 of the tenth light emitting transistor, and the second light emitting power line EVGL are interconnected as an integral structure, and the first electrode ET33 of the third light emitting transistor may be in the shape of a strip extending along the second direction D2, and the first electrode ET103 of the tenth light emitting transistor may be in the shape of an "n" shape with an opening toward the second light emitting power line EVGL.
  • the first electrode ET33 of the third light emitting transistor (also the first electrode ET103 of the tenth light emitting transistor) is connected to the first region of the active layer of the third light emitting transistor through the fifth via hole, and is connected to the first region of the active layer of the tenth light emitting transistor through the seventeenth via hole.
  • the first electrode ET53 of the fifth light emitting transistor and the first light emitting power line EVGH are an integrated structure connected to each other.
  • the first electrode ET53 of the fifth light emitting transistor may be in a block shape.
  • the fifth light emitting transistor ET53 is connected to the first region of the active layer of the fifth light emitting transistor through an eighth via hole.
  • the shape of the first electrode ET63 of the sixth light emitting transistor can be a block.
  • the first electrode ET63 of the sixth light emitting transistor is connected to the first region of the active layer of the sixth light emitting transistor through the ninth via hole, and is connected to the second electrode plate of the third light emitting capacitor through the twenty-sixth via hole.
  • the second electrode ET64 of the sixth light-emitting transistor and the first electrode ET73 of the seventh light-emitting transistor are an integral structure connected to each other.
  • the second electrode ET64 of the sixth light-emitting transistor (also the first electrode ET73 of the seventh light-emitting transistor) at least partially extends along the first direction D1.
  • the second electrode ET64 of the sixth light-emitting transistor (also the first electrode ET73 of the seventh light-emitting transistor) is connected to the second region of the active layer of the sixth light-emitting transistor through the tenth via hole, connected to the first region of the active layer of the seventh light-emitting transistor through the eleventh via hole, and connected to the second electrode plate of the first light-emitting capacitor through the twenty-fourth via hole.
  • the second electrode ET74 of the seventh light-emitting transistor and the second electrode ET84 of the eighth light-emitting transistor are an integrated structure connected to each other.
  • the shape of the second electrode ET74 of the seventh light-emitting transistor (also the second electrode ET84 of the eighth light-emitting transistor) can be a horizontally flipped "7" shape.
  • the second electrode ET74 of the seventh light-emitting transistor (also the second electrode ET84 of the eighth light-emitting transistor) is connected to the second region of the active layer of the seventh light-emitting transistor through the twelfth via hole, connected to the second region of the active layer of the eighth light-emitting transistor through the fourteenth via hole, and connected to the gate electrode of the ninth light-emitting transistor (also the first electrode plate of the second light-emitting capacitor) through the twenty-third via hole.
  • the first electrode ET83 of the eighth light emitting transistor, the first electrode ET93 of the ninth light emitting transistor and the first light emitting power line EVGH are interconnected as an integral structure.
  • the first electrode ET83 of the eighth light emitting transistor may be in a block shape
  • the first electrode ET93 of the ninth light emitting transistor may be in a comb shape
  • the first electrode ET83 of the eighth light emitting transistor (also the first electrode ET93 of the ninth light emitting transistor) is connected to the first region of the active layer of the eighth light emitting transistor through the thirteenth via hole, connected to the first region of the active layer of the ninth light emitting transistor through the fifteenth via hole, and connected to the second electrode plate of the second light emitting capacitor through the twenty-fifth via hole.
  • the shape of the second electrode ET94 of the ninth light-emitting transistor may be a comb shape, and the comb teeth of the second electrode ET94 of the ninth light-emitting transistor may be arranged in an interlaced manner with the comb teeth of the first electrode ET93 of the ninth light-emitting transistor.
  • the second electrode ET94 of the ninth light-emitting transistor is connected to the second region of the active layer of the ninth light-emitting transistor through the sixteenth via hole.
  • the second electrode ET94 of the ninth light-emitting transistor in FIG. 5A is connected to the output connection line through the twenty-ninth via hole.
  • the second electrode ET94 of the ninth light-emitting transistor in FIG. 6A is connected to the output connection line through the twenty-eighth via hole.
  • the shape of the second electrode ET104 of the tenth light-emitting transistor may be an "n" shape with an opening facing away from the second light-emitting power line EVGL.
  • the second electrode ET104 of the tenth light-emitting transistor is connected to the second region of the active layer of the tenth light-emitting transistor through the eighteenth via hole.
  • the second electrode ET104 of the tenth light-emitting transistor in FIG. 5A is connected to the output connection line through the twenty-ninth via hole.
  • the second electrode ET104 of the tenth light-emitting transistor in FIG. 6A is connected to the output connection line through the twenty-eighth via hole.
  • one of the first light emitting clock signal line ECK1 and the second light emitting clock signal line ECK2 is connected to the gate electrode of the first light emitting transistor (also the gate electrode of the third light emitting transistor) through a nineteenth via hole.
  • the other of the first and second light emitting clock signal lines ECK1 and ECK2 is connected to the gate electrode of the fourth light emitting transistor through the twentieth via hole and is connected to the gate electrode of the seventh light emitting transistor through the twenty-second via hole.
  • the second connection line CL2 may be in a block shape. As shown in Figure 27, the second connection line in Figure 5A is connected to the output main body portion of the output line through the twenty-seventh via hole.
  • the area where the second light emitting power line EVGL overlaps with the first area of the active layer of the first release transistor can be reused as the first electrode of the first release transistor.
  • the first electrode of the first release transistor in Figure 5A is connected to the first area of the active layer of the first release transistor through the 30th via hole
  • the first electrode of the first release transistor in Figure 6A is connected to the first area of the active layer of the first release transistor through the 29th via hole.
  • the second electrode ET14 of the first release transistor and the second electrode ET24 of the second release transistor are interconnected as an integral structure, and the shape may be a horizontally flipped "L" shape.
  • the orthographic projection of the second electrode ET14 of the first release transistor (also the second electrode of the second release transistor) on the substrate in FIG. 5A overlaps at least partially with the orthographic projection of the output connection portion on the substrate.
  • the orthographic projection of the second electrode ET14 of the first release transistor (also the second electrode of the second release transistor) on the substrate in FIG. 5A does not overlap with the orthographic projection of the output line on the substrate.
  • the second electrode ET14 of the first release transistor (also the second electrode of the second release transistor) in Fig. 5A is connected to the output connection portion of the output line through the 28th via hole, connected to the second region of the active layer of the first release transistor (also the second region of the active layer of the second release transistor) through the 31st via hole, and connected to the gate electrode of the first release transistor through the 33rd via hole.
  • the second electrode ET14 of the first release transistor (also the second electrode of the second release transistor) in Fig. 6A is connected to the second region of the active layer of the first release transistor (also the second region of the active layer of the second release transistor) through the 30th via hole, and connected to the gate electrode of the first release transistor through the 32nd via hole.
  • the second electrode ET21 of the second release transistor and the first scan power line GVGH are an integral structure connected to each other, and the shape may be an "L" shape that may be horizontally flipped.
  • the second electrode ET21 of the second release transistor in FIG. 5A is connected to the first region of the active layer of the second release transistor through the thirty-second via hole, and is connected to the gate electrode of the second release transistor through the thirty-fourth via hole.
  • the second electrode ET21 of the second release transistor in FIG. 6A is connected to the first region of the active layer of the second release transistor through the thirty-first via hole, and is connected to the gate electrode of the second release transistor through the thirty-third via hole.
  • the shape of the first electrode GT13 of the first scanning transistor may be a strip extending along the second direction D2.
  • the first electrode GT13 of the first scanning transistor in FIG. 5A is connected to the first region of the active layer of the first scanning transistor through the thirty-fifth via hole, and is connected to the third signal connection line through the fifty-fourth via hole.
  • the first electrode GT13 of the first scanning transistor in FIG. 6A is connected to the first region of the active layer of the first scanning transistor through the thirty-fourth via hole, and is connected to the third signal connection line through the fifty-third via hole.
  • the second electrode GT14 of the first scanning transistor and the second electrode GT74 of the seventh scanning transistor are interconnected integral structures, and the shape may be a strip extending along the second direction D2.
  • the second electrode GT14 of the first scanning transistor (also the second electrode GT74 of the seventh scanning transistor) in FIG. 5A is connected to the second region of the active layer of the first scanning transistor (also the second region of the active layer of the seventh scanning transistor) through the thirty-sixth via hole, and is connected to the gate electrode of the second scanning transistor through the forty-seventh via hole.
  • the shape of the first electrode GT23 of the second scanning transistor may be a strip extending along the first direction D1.
  • the first electrode GT23 of the second scanning transistor in the display substrate provided in FIG. 5A is connected to the first region of the active layer of the second scanning transistor through the thirty-seventh via hole, and is connected to the gate electrode of the first scanning transistor (also the gate electrode of the third scanning transistor) through the forty-sixth via hole.
  • the first electrode GT23 of the second scanning transistor in FIG. 6A is connected to the first region of the active layer of the second scanning transistor through the thirty-sixth via hole, and is connected to the gate electrode of the first scanning transistor (also the gate electrode of the third scanning transistor) through the forty-fifth via hole.
  • the second electrode GT24 of the second scanning transistor and the second electrode GT34 of the third scanning transistor are connected to each other as an integral structure, and the shape may be a strip extending along the second direction D2.
  • the second electrode GT24 (also the third electrode GT34) of the second scanning transistor in the display substrate provided in FIG. 5A The second electrode GT34 of the scanning transistor is connected to the second area of the active layer of the second scanning transistor (also the second area of the active layer of the third scanning transistor) through the thirty-eighth via hole, and is connected to the gate electrode of the fourth scanning transistor (also the gate electrode of the sixth scanning transistor and the first plate of the first scanning capacitor) through the forty-eighth via hole.
  • the second electrode GT24 of the second scanning transistor (also the second electrode GT34 of the third scanning transistor) in FIG. 6A is connected to the second area of the active layer of the second scanning transistor (also the second area of the active layer of the third scanning transistor) through the thirty-seventh via hole, and is connected to the gate electrode of the fourth scanning transistor (also the gate electrode of the sixth scanning transistor and the first plate of the first scanning capacitor) through the forty-seventh via hole.
  • the overlapped region of the second scan power line GVGL and the first region of the active layer of the third scan transistor is reused as the first electrode GT33 of the third scan transistor.
  • the first electrode GT33 of the third scan transistor in Figure 5A is connected to the first region of the active layer of the third scan transistor through the thirty-ninth via hole.
  • the shape of the first electrode GT43 of the fourth scanning transistor may be a strip extending along the second direction D2.
  • the first electrode GT43 of the fourth scanning transistor in the display substrate provided in FIG. 5A is connected to the first region of the active layer of the fourth scanning transistor through the 40th via hole, and is connected to the second electrode plate of the first scanning capacitor through the 52nd via hole.
  • the first electrode GT23 of the second scanning transistor in FIG. 6A is connected to the first region of the active layer of the fourth scanning transistor through the 39th via hole, and is connected to the second electrode plate of the first scanning capacitor through the 51st via hole.
  • the second electrode GT44 of the fourth scanning transistor and the second electrode GT54 of the fifth scanning transistor are an integrated structure connected to each other, and the shape may be an "m" shape with an opening toward the second scanning power supply line GVGH.
  • the second electrode GT44 of the fourth scanning transistor (also the second electrode GT54 of the fifth scanning transistor) in FIG. 5A is connected to the second area of the active layer of the fourth scanning transistor (the second area of the active layer of the fifth scanning transistor) through the 41st via hole, and is connected to the second electrode plate of the second scanning capacitor through the 53rd via hole.
  • the second electrode GT44 of the fourth scanning transistor (also the second electrode GT54 of the fifth scanning transistor) in FIG. 6A is connected to the second area of the active layer of the fourth scanning transistor (the second area of the active layer of the fifth scanning transistor) through the 40th via hole, and is connected to the second electrode plate of the second scanning capacitor through the 52nd via hole.
  • the shape of the first electrode GT53 of the fifth scanning transistor may be an "F" shape.
  • the first electrode GT53 of the fifth scanning transistor in FIG. 5A is connected to the first region of the active layer of the fifth scanning transistor through the 42nd via hole, and is connected to the gate electrode of the seventh scanning transistor through the 50th via hole.
  • the first electrode GT53 of the fifth scanning transistor in FIG. 6A is connected to the first region of the active layer of the fifth scanning transistor through the 41st via hole, and is connected to the gate electrode of the seventh scanning transistor through the 49th via hole.
  • the shape of the first electrode GT63 of the sixth scanning transistor may be a strip extending along the second direction D2.
  • the first electrode GT63 of the sixth scanning transistor in FIG. 5A is connected to the first region of the active layer of the sixth scanning transistor through the 43rd via hole, and is connected to the second electrode plate of the second scanning capacitor through the 52nd via hole.
  • the first electrode GT63 of the sixth scanning transistor in FIG. 6A is connected to the first region of the active layer of the sixth scanning transistor through the 42nd via hole, and is connected to the second electrode plate of the second scanning capacitor through the 51st via hole.
  • the shape of the first electrode GT83 of the eighth scanning transistor may be a block.
  • the first electrode GT83 of the eighth scanning transistor in FIG. 5A is connected to the first region of the active layer of the eighth scanning transistor through the 44th via hole, and is connected to the gate electrode of the fifth scanning transistor (also the second plate of the second scanning capacitor) through the 49th via hole.
  • the first electrode GT63 of the sixth scanning transistor in FIG. 6A is connected to the first region of the active layer of the eighth scanning transistor through the 43rd via hole, and is connected to the gate electrode of the fifth scanning transistor (also the second plate of the second scanning capacitor) through the 48th via hole.
  • the shape of the second electrode GT84 of the eighth scanning transistor may be a block shape.
  • the second electrode GT84 of the eighth scanning transistor in FIG. 5A is connected to the second region of the active layer of the eighth scanning transistor through the 45th via hole, and is connected to the gate electrode of the second scanning transistor through the 47th via hole.
  • the second electrode GT84 of the eighth scanning transistor in FIG. 6A is connected to the second region of the active layer of the eighth scanning transistor through the 44th via hole, and is connected to the gate electrode of the second scanning transistor through the 46th via hole.
  • one of the first sub-clock signal line GCK1A of the first scan clock signal line and the third sub-clock signal line GCK2A of the second scan clock signal line in Fig. 5A is connected to the gate electrode of the first scan transistor (also the gate electrode of the third scan transistor) through the 46th via hole.
  • one of the first sub-clock signal line GCK1A of the first scan clock signal line and the third sub-clock signal line GCK2A of the second scan clock signal line in Fig. 6A is connected to the gate electrode of the first scan transistor (also the gate electrode of the third scan transistor) through the 45th via hole.
  • the other of the first sub-clock signal line GCK1A of the first scan clock signal line and the third sub-clock signal line GCK2A of the second scan clock signal line in Fig. 5A is connected to the gate electrode of the seventh scan transistor through the 50th via hole.
  • the other of the first sub-clock signal line GCK1A of the first scan clock signal line and the third sub-clock signal line GCK2A of the second scan clock signal line in Fig. 6A is connected to the gate electrode of the seventh scan transistor through the 49th via hole.
  • the second scan power line GVGH in Fig. 5A is connected to the gate electrode of the eighth scan transistor through the fifty-first via hole.
  • the second scan power line GVGH in Fig. 6A is connected to the gate electrode of the eighth scan transistor through the fiftieth via hole.
  • the first connection line CL1 in Fig. 5A is connected to the scan output signal line through the fifty-fifth via hole.
  • the first connection line CL1 in Fig. 6A is connected to the scan output signal line through the fifty-fourth via hole.
  • the first sub initial power supply line INITL1A and the fourth connection line CL4 of the first initial power supply line in Fig. 5A are connected to the first signal connection line through the fifty-sixth via hole.
  • the first sub initial power supply line INITL1A and the fourth connection line CL4 of the first initial power supply line in Fig. 6A are connected to the first signal connection line through the fifty-fifth via hole.
  • the first sub initial power supply line INITL2A and the third connection line CL3 of the second initial power supply line in Fig. 5A are connected to the second signal connection line through the fifty-seventh via hole.
  • the first sub initial power supply line INITL2A and the third connection line CL3 of the second initial power supply line in Fig. 6A are connected to the second signal connection line through the fifty-sixth via hole.
  • the shape of the first electrode MT13 of the first transistor is a strip extending along the second direction D2.
  • the shape of the first electrode MT13 of the first transistor is a strip extending along the first direction D1.
  • the first electrode MT13 of the first transistor is electrically connected to the first region of the active layer of the first transistor through the fifty-eighth via hole, and is electrically connected to the first initial signal line through the sixty-fifth via hole.
  • the second electrode MT14 of the first transistor and the first electrode MT23 of the second transistor are an integral structure and are in the shape of a strip extending along the first direction D1.
  • the second electrode MT14 of the first transistor (also the first electrode MT23 of the second transistor) is electrically connected to the second region of the active layer of the first transistor (also the first region of the active layer of the second transistor) through the fifty-ninth via hole, and is electrically connected to the gate electrode of the third transistor (also the first plate of the capacitor) through the sixty-fourth via hole.
  • the shape of the first electrode MT43 of the fourth transistor is a block.
  • the first electrode MT43 of the fourth transistor is electrically connected to the first region of the active layer of the fourth transistor through the sixtieth via hole.
  • the first electrode M53 of the fifth transistor at least partially extends along the first direction D1.
  • the first electrode M53 of the fifth transistor is electrically connected to the first region of the active layer of the fifth transistor through the sixty-first via hole, and is electrically connected to the second plate of the capacitor through the sixty-sixth via hole.
  • the second electrode MT64 of the sixth transistor and the first electrode MT74 of the seventh transistor are an integral structure and are block-shaped.
  • the second electrode MT64 of the sixth transistor (also the first electrode MT74 of the seventh transistor) is electrically connected to the second region of the active layer of the sixth transistor (the second region of the active layer of the seventh transistor) through the sixty-second via hole.
  • the first electrode MT73 of the seventh transistor is in the shape of a strip extending along the first direction D1.
  • the first electrode MT73 of the seventh transistor is electrically connected to the first region of the active layer of the seventh transistor through the sixty-third via hole, and is electrically connected to the second initial signal line through the sixty-seventh via hole.
  • the data link line DL at least partially extends along the second direction D2 and may be located between the second electrode MT64 of the sixth transistor (also the first electrode MT74 of the seventh transistor) and the first electrode MT73 of the seventh transistor.
  • the shape of the first sub power line VDDA is a line shape extending at least partially along the first direction D1.
  • the overlapping region of the first sub power line VDDA and the first region of the active layer of the fifth transistor is reused as the first electrode MT53 of the fifth transistor.
  • the first sub power line VDDA is electrically connected to the first region of the active layer of the fifth transistor through the sixty-first via hole, and is electrically connected to the second plate of the capacitor through the sixty-sixth via hole.
  • the electrode connection line CL is electrically connected to the first pole MT73 of the seventh transistor of the adjacent sub-pixels in the same column.
  • the first poles MT73 of the seventh transistor of the adjacent sub-pixels of at least one column of sub-pixels are arranged at intervals, and the first poles MT73 of the seventh transistor of the adjacent sub-pixels of at least one column of sub-pixels are electrically connected through the electrode connection line CL.
  • the first poles MT73 of the seventh transistor of the adjacent sub-pixels of the j-th column of sub-pixels are arranged at intervals, and the first poles MT73 of the seventh transistor of the adjacent sub-pixels of the j+1-th column of sub-pixels are electrically connected through the electrode connection line CL.
  • the arrangement of the electrode connection line CL can form a mesh structure with a plurality of second initial signal lines, so that the signals of the second initial signal lines in each sub-pixel are consistent, and the display effect of the display substrate can be guaranteed.
  • a fourth insulating layer pattern comprising: depositing a fourth insulating film on a substrate having the aforementioned pattern, coating a first flat film, and patterning the fourth insulating film and the first flat film through a patterning process to form a fourth insulating layer covering the aforementioned structure and a flat layer pattern arranged on the fourth insulating layer, wherein the flat layer is provided with a groove and a plurality of via patterns, as shown in FIGS. 29 , 30 , 50 and 51 , wherein FIG. 29 is a schematic diagram of FIG. 5A after the flat layer pattern is formed, FIG. 30 is a schematic diagram of FIG. 6A after the flat layer pattern is formed, FIG. 50 is a schematic diagram of FIG. 7B after the flat layer pattern is formed, and FIG. 51 is a schematic diagram of FIG. 7C after the flat layer pattern is formed.
  • the multiple vias of the planar layer pattern may include at least: a seventy-first via V71, a seventy-second via V72, a seventy-third via V73, a seventy-fourth via V74, a seventy-fifth via V75, a seventy-sixth via V76, a seventy-seventh via V77, a seventy-eighth via V78, and sixty-eighth vias V68 to seventy vias V70.
  • the orthographic projection of the seventy-first via hole V71 on the substrate The fourth insulating layer in the seventy-first via V71 is etched away within the range of the positive projection of the first sub-clock signal line of the first scanning clock signal line on the substrate, exposing the first sub-clock signal line of the first scanning clock signal line, and the seventy-first via V71 is configured to connect the second sub-clock signal line of the first scanning clock signal line formed subsequently to the first sub-clock signal line of the first scanning clock signal line through the via.
  • the orthographic projection of the seventy-second via V72 on the substrate is located within the range of the orthographic projection of the third sub-clock signal line of the second scan clock signal line on the substrate, the fourth insulating layer in the seventy-second via V72 is etched away to expose the third sub-clock signal line of the second scan clock signal line, and the seventy-second via V72 is configured to connect the subsequently formed fourth sub-clock signal line of the second scan clock signal line to the third sub-clock signal line of the second scan clock signal line through the via.
  • the orthographic projection of the seventy-third via V73 on the substrate is located within the range of the orthographic projection of the first sub-initial power supply line of the first initial power supply line on the substrate, the fourth insulating layer in the seventy-third via V73 is etched away to expose the first sub-initial power supply line of the first initial power supply line, and the seventy-third via V73 is configured to connect the second sub-initial power supply line of the first initial power supply line formed subsequently to the first sub-initial power supply line of the first initial power supply line through the via.
  • the orthographic projection of the seventy-fourth via V74 on the substrate is located within the range of the orthographic projection of the first sub-initial power line of the second initial power line on the substrate, exposing the first sub-initial power line of the second initial power line, and the seventy-fourth via V74 is configured to connect the second sub-initial power line of the second initial power line formed subsequently to the first sub-initial power line of the second initial power line through the via.
  • the orthographic projection of the seventy-fifth via hole V75 on the substrate is located within the range of the orthographic projection of the first connecting line on the substrate, the fourth insulating layer in the seventy-fifth via hole V75 is etched away to expose the first connecting line, and the seventy-fifth via hole V75 is configured to connect the subsequently formed fifth connecting line to the first connecting line through the via hole.
  • the orthographic projection of the seventy-sixth via V76 on the substrate is located within the range of the orthographic projection of the second connecting line on the substrate, the fourth insulating layer in the seventy-sixth via V76 is etched away to expose the second connecting line, and the seventy-sixth via V76 is configured to connect the subsequently formed sixth connecting line to the second connecting line through the via.
  • the orthographic projection of the seventy-seventh via hole V77 on the substrate is located within the range of the orthographic projection of the third connecting line on the substrate, the fourth insulating layer in the seventy-seventh via hole V77 is etched away to expose the first connecting line, and the seventy-seventh via hole V77 is configured to connect the subsequently formed seventh connecting line to the third connecting line through the via hole.
  • the orthographic projection of the seventy-eight via hole V78 on the substrate is located within the range of the orthographic projection of the fourth connecting line on the substrate, the fourth insulating layer in the seventy-eight via hole V78 is etched away to expose the fourth connecting line, and the seventy-eighth via hole V78 is configured to connect the subsequently formed eighth connecting line to the fourth connecting line through the via hole.
  • the orthographic projection of the sixty-eight via V68 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, exposing the first electrode of the fourth transistor, and the sixty-eight via V68 is configured to connect a subsequently formed data signal line to the first electrode of the fourth transistor through the via.
  • the orthographic projection of the sixty-ninth via V69 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate, exposing the first electrode of the fifth transistor, and the sixty-ninth via V69 is configured to connect a subsequently formed first power line to the first electrode of the fifth transistor through the via.
  • the orthographic projection of the sixty-ninth via hole V69 on the substrate is located at the first The first sub power line is exposed within the range of the orthographic projection of the sub power line on the substrate, and the sixty-ninth via hole V69 is configured to connect the second sub power line formed subsequently to the first sub power line through the via hole.
  • the orthographic projection of the seventieth via V70 on the substrate is located within the range of the orthographic projection of the second pole of the sixth transistor (also the second pole of the seventh transistor) on the substrate, exposing the second pole of the sixth transistor (also the second pole of the seventh transistor), and the seventieth via V70 is configured to connect the subsequently formed anode connecting electrode to the second pole of the sixth transistor (also the second pole of the seventh transistor) through the via.
  • a fourth insulating layer is provided in FIGS. 5A and 6A , but the fourth insulating layer provided in FIGS. 5A and 6A has no via hole.
  • FIG. 31 is a schematic diagram of the fourth conductive layer pattern of FIGS. 5A and 6A
  • FIG. 32 is a schematic diagram of FIG. 5A after the fourth conductive layer pattern is formed
  • FIG. 33 is a schematic diagram of FIG. 6A after the fourth conductive layer pattern is formed
  • FIG. 52 is a schematic diagram of the fourth conductive layer pattern of FIG. 7B
  • FIG. 53 is a schematic diagram of FIG.
  • FIG. 54 is a schematic diagram of FIG. 7C after the fourth conductive layer pattern is formed
  • FIG. 55 is a schematic diagram of FIG. 7C after the fourth conductive layer pattern is formed.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer pattern may include at least: a second sub-clock signal line GCK1B of the first scan clock signal line, a fourth sub-clock signal line GCK2B of the second scan clock signal line, a second sub-initial power supply line INITL1B of the first initial power supply line, a second sub-initial power supply line INITL2B of the second initial power supply line, a fifth connecting line CL5, a sixth connecting line CL6, a seventh connecting line CL7 and an eighth connecting line CL8.
  • the second sub-clock signal line GCK1B of the first scan clock signal line is in a line shape in the first direction D1.
  • the second sub-clock signal line of the first scan clock signal line passes through the seventy-first via hole and the first sub-clock signal line of the first scan clock signal line.
  • an orthographic projection of the second sub-clock signal line GCK1B of the first scan clock signal line on the substrate at least partially overlaps an orthographic projection of the first sub-clock signal line of the first scan clock signal line on the substrate.
  • the fourth sub-clock signal line GCK2B of the second scan clock signal line is in a line shape in the first direction D1.
  • the fourth sub-clock signal line of the second scan clock signal line passes through the 72nd via hole and the third sub-clock signal line of the second scan clock signal line.
  • an orthographic projection of the fourth sub-clock signal line GCK2B of the second scan clock signal line on the substrate at least partially overlaps an orthographic projection of the third sub-clock signal line of the second scan clock signal line on the substrate.
  • the second sub-initial power line of the first initial power line is linear in the first direction D1 and connected to the first sub-initial power line of the first initial power line through the seventy-third via hole.
  • an orthographic projection of the second sub-initial power supply line of the first initial power supply line on the substrate at least partially overlaps an orthographic projection of the first sub-initial power supply line of the first initial power supply line on the substrate.
  • the second sub-initial power line of the second initial power line is linear in the first direction D1 and connected to the first sub-initial power line of the second initial power line through the seventy-fourth via hole.
  • an orthographic projection of a second sub-initial power supply line of the second initial power supply line on the substrate at least partially overlaps an orthographic projection of a first sub-initial power supply line of the second initial power supply line on the substrate.
  • the shape of the fifth connection line CL5 may be a block shape.
  • the seventy-fifth via hole is connected to the first connecting line.
  • the shape of the sixth connection line CL6 may be a block shape.
  • the sixth connection line CL6 is connected to the second connection line through the seventy-sixth via hole.
  • the seventh connection line CL7 may have a block shape.
  • the seventh connection line CL7 is connected to the third connection line through the seventy-seventh via hole.
  • the shape of the eighth connection line CL8 may be a block shape.
  • the eighth connection line CL8 is connected to the fourth connection line through the seventy-eighth via hole.
  • the fourth conductive layer pattern may include at least a data signal line Data, an anode connection electrode VL, and a flat portion BL.
  • the fourth conductive layer pattern may further include: a first power line VDD.
  • the fourth conductive layer pattern may further include a second sub power line VDDB.
  • the second sub power line VDDB and the first sub power line constitute a first power line.
  • the data signal line Data extends along the first direction D1.
  • the data signal line Data is electrically connected to the first electrode of the fourth transistor through the sixty-eighth via hole.
  • the anode connection electrode VL extends in the first direction D1.
  • the anode connection electrode VL is electrically connected to the second electrode of the sixth transistor (also the first electrode of the seventh transistor) through the seventieth via hole.
  • the flat portion BL is an integral structure with the first power line VDD.
  • the orthographic projection of the flat portion BL on the substrate at least partially overlaps with the orthographic projection of the anode of the light emitting device on the substrate.
  • the flat portion BL is an integral structure with the second sub power line VDDB.
  • the orthographic projection of the flat portion BL on the substrate at least partially overlaps the orthographic projection of the anode of the light emitting device on the substrate.
  • the first power line VDD extends in the first direction D1.
  • the first power line VDD is electrically connected to the first electrode of the fifth transistor through the sixty-ninth via hole.
  • the second sub power line VDD extends in the first direction D1.
  • the second sub power line VDD is electrically connected to the first sub power line through the sixty-ninth via hole.
  • forming the planar layer may include: depositing a fifth insulating film and a fifth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process to form a fifth insulating layer and a fifth conductive layer disposed on the fifth insulating layer, and depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the fifth conductive layer pattern.
  • the fifth conductive layer may include an anode connection line.
  • the driving structure layer is prepared on the substrate.
  • the driving structure layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a flat layer, a fourth conductive layer, a fifth insulating layer, a fifth conductive layer and a sixth insulating layer sequentially arranged on the substrate.
  • the semiconductor layer may be a metal oxide layer.
  • the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or Oxides of gallium and zinc.
  • the metal oxide layer can be a single layer, a double layer, or a multilayer.
  • the active layer film can be made of various materials such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide material
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • sexithiophene polythiophene
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the fifth conductive layer may employ an indium tin oxide (ITO) or indium zinc oxide (IZO) material.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the first insulating layer and the second insulating layer may be referred to as a gate insulating (GI) layer
  • the third insulating layer may be referred to as an interlayer insulating (ILD) layer.
  • the planar layer may employ an organic material such as resin or the like.
  • a light emitting structure layer is prepared on the driving structure layer, and the preparation process of the light emitting structure layer may include the following operations.
  • Forming a light-emitting structure layer may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the flat layer, the anode conductive layer including at least a plurality of anode patterns, coating a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film using a patterning process to form a pixel definition layer, first forming an organic light-emitting layer on the substrate on which the aforementioned pattern is formed using an evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer.
  • the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the material of the pixel definition layer may include polyimide, acryl, or polyethylene terephthalate.
  • the anode thin film may employ indium tin oxide (ITO) or indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the cathode film may be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals.
  • the electrostatic discharge circuit and the gate driving circuit in the present disclosure are formed by the same process, which can ensure the reliability of the display substrate without increasing the process steps.
  • the embodiment of the present disclosure further provides a display device, which may include: a display substrate and a photosensitive sensor.
  • the photosensitive sensor is located in the display substrate.
  • the display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.
  • the display device may be a liquid crystal display (LCD) or an organic light emitting diode (OLED).
  • the display device may be a liquid crystal panel, an electronic paper, an OLED panel, an active-matrix organic light emitting diode (OLED), or a display device.
  • the thickness and size of the layer or microstructure are exaggerated. It is understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” the other element, or there may be intermediate elements.

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Abstract

提供了一种显示基板和显示装置。显示基板包括：基底(10)以及设置在基底(10)上的驱动结构层，基底包括显示区域(100)和非显示区域(200)。驱动结构层包括：位于显示区域(100)的多个像素电路和位于非显示区域(200)的栅极驱动电路和静电释放电路(ER)，栅极驱动电路被配置为向像素电路提供驱动信号，栅极驱动电路包括多个驱动电路，多个驱动电路和静电释放电路(ER)沿靠近显示区域(100)的方向排列；静电释放电路(ER)设置在相邻的两个驱动电路之间，且与相邻的两个驱动电路中任一个电路的至少一条信号线电连接。

Description

显示基板和显示装置 技术领域
本公开涉及但不限于显示技术领域，特别涉及一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板，包括：基底以及设置在基底上的驱动结构层，所述基底包括显示区域和非显示区域，所述驱动结构层包括：位于显示区域的多个像素电路和位于非显示区域的栅极驱动电路和静电释放电路，所述栅极驱动电路被配置为向像素电路提供驱动信号，栅极驱动电路包括多个驱动电路，所述多个驱动电路和所述静电释放电路沿靠近所述显示区域的方向排列；
所述静电释放电路设置在相邻的两个驱动电路之间，且与相邻的两个驱动电路中任一个电路的至少一条信号线电连接。
在示例性实施方式中，所述静电释放电路至少包括：第一释放晶体管和第二释放晶体管；
第一释放晶体管的栅电极和第二极与第一信号端连接，第一释放晶体管的第一极与第二信号端连接；
第二释放晶体管的栅电极和第一极与第三信号端连接，第二释放晶体管的第二极与第一信号端连接。
在示例性实施方式中，所述多个驱动电路包括：发光驱动电路和扫描驱动电路，所述扫描驱动电路位于所述发光驱动电路靠近显示区域的一侧；
所述驱动结构层还包括：位于非显示区域的发光初始信号线、第一发光时钟信号线、第二发光时钟信号线、第一发光电源线、第二发光电源线，扫描初始信号线、第一扫描时钟信号线、第二扫描时钟信号线、第一扫描电源线和第二扫描电源线；发光初始信号线、第一发光时钟信号线、第二发光时钟信号线、第一发光电源线、第二发光电源线，扫描初始信号线、第一扫描时钟信号线、第二扫描时钟信号线、第一扫描电源线和第二扫描电源线中的任一条沿第一方向延伸；
所述发光驱动电路分别与发光初始信号线、第一发光时钟信号线、第二发光时钟信号线、第一发光电源线和第二发光电源线电连接；所述扫描驱动电路分别与扫描初始信号线、第二扫描时钟信号线、第一扫描时钟信号线、第一扫描电源线和第二扫描电源线电连接；
所述发光初始信号线、所述第一发光时钟信号线、所述第二发光时钟信号线、所述第 一发光电源线、所述第二发光电源线、所述第一扫描电源线、所述第一扫描时钟信号线、所述第二扫描时钟信号线、所述扫描初始信号线和所述第二扫描电源线沿靠近所述显示区域的方向依次排列。
在示例性实施方式中，所述静电释放电路在基底上的正投影与所述第一扫描电源线和所述第二发光电源线部分交叠，且至少部分静电释放电路位于所述第二发光电源线和所述第一扫描电源线之间。
在示例性实施方式中，所述驱动结构层还包括：位于非显示区域的发光输出信号线和扫描输出信号线以及至少部分位于显示区域的发光信号线和扫描信号线；扫描输出信号线、发光信号线和扫描信号线中的任一条至少部分沿第二方向延伸，所述第一方向与所述第二方向相交；所述像素电路，分别与发光信号线和扫描信号线连接；
所述发光驱动电路包括：多个级联的发光移位寄存器，所述扫描驱动电路包括：多个级联的扫描移位寄存器；
所述发光输出信号线，分别与发光移位寄存器和至少一条发光信号线电连接；
所述扫描输出信号线，分别与扫描移位寄存器和扫描信号线电连接。
在示例性实施方式中，所述静电释放电路的第一信号端与所述发光输出信号线电连接，所述静电释放电路的第二信号端与所述第二发光电源线电连接，所述静电释放电路的第三信号端与所述第一扫描电源线电连接。
在示例性实施方式中，所述第二发光电源线和所述第一扫描电源线之间的距离约为8微米至15微米。
在示例性实施方式中，所述发光移位寄存器包括多个发光晶体管和多个发光电容，所述扫描移位寄存器包括多个扫描晶体管和多个扫描电容，所述发光电容和所述扫描电容均包括第一极板和第二极板，所述驱动结构层包括：依次叠设的半导体层、第一导电层、第二导电层、第三导电层和第四导电层，所述第一扫描时钟信号线包括：相互电连接的第一子时钟信号线和第二子时钟信号线，所述第二扫描时钟信号线包括：相互电连接的第三子时钟信号线和第四子时钟信号线；
所述半导体层至少包括：多个发光晶体管的有源层、多个扫描晶体管的有源层、第一释放晶体管的有源层和第二释放晶体管的有源层；
所述第一导电层至少包括：发光信号线、扫描信号线、多个发光晶体管的栅电极、多个发光电容的第一极板，多个扫描晶体管的栅电极、多个扫描电容的第一极板、第一释放晶体管的栅电极和第二释放晶体管的栅电极；
所述第二导电层至少包括：多个发光电容的第二极板、多个扫描电容的第二极板、扫描输出信号线和发光输出信号线；
所述第三导电层至少包括：发光初始信号线、第一发光时钟信号线、第二发光时钟信号线、第一发光电源线、第二发光电源线，扫描初始信号线、第一扫描时钟信号线的第一子时钟信号线、第二扫描时钟信号线的第三子时钟信号线、第一扫描电源线和第二扫描电源线、多个发光晶体管的第一极和第二极、多个扫描晶体管的第一极和第二极、第一释放晶体管的第一极和第二极以及第二释放晶体管的第一极和第二极；
所述第四导电层至少包括：第一扫描时钟信号线的第二子时钟信号线和第二扫描时钟信号线的第四子时钟信号线。
在示例性实施方式中，多个发光晶体管的第一极和第二极位于第一发光电源线和第二发光电源线之间，第一释放晶体管的第一极和第二极至第二释放晶体管的第一极和第二极 位于第二发光电源线和第一扫描电源线之间，部分扫描晶体管的第一极和第二极位于扫描初始信号线和第二扫描电源线之间，另一部分扫描晶体管的第一极和第二极可以位于第二扫描电源线靠近显示区域的一侧。
在示例性实施方式中，至少一条所述发光输出信号线包括：输出连接部和至少一条输出线，所述输出连接部沿第一方向延伸，至少一条所述输出线沿第一方向排布；
所述输出连接部，分别与发光移位寄存器和至少一条输出线电连接，所述输出线与发光输出信号线所连接的发光信号线一一对应，且与对应的发光信号线电连接。
在示例性实施方式中，所述输出线包括：至少部分沿第二方向延伸的输出主体部和沿第一方向延伸的输出连接部，所述输出主体部与所述输出连接部电连接；
第一释放晶体管的第二极和第二释放晶体管的第二极为一体结构，且在基底上的正投影与输出连接部在基底上的正投影至少部分交叠，第一释放晶体管的第二极和第二释放晶体管的第二极的一体结构与输出连接部电连接。
在示例性实施方式中，第一释放晶体管的有源层和第二释放晶体管的有源层为一体结构，且沿第二方向延伸；
所述输出连接部在基底上的正投影与第一释放晶体管的有源层和第二释放晶体管的有源层的一体结构在基底上的正投影不交叠。
在示例性实施方式中，第一释放晶体管的有源层和第二释放晶体管的有源层为一体结构，且包括：有源主体部和有源连接部，有源主体部和有源连接部电连接，有源主体部和有源连接部沿第一方向排布；
所述有源主体部沿第二方向延伸，所述有源连接部至少部分沿第一方向延伸；
所述有源连接部的形状为折线形。
在示例性实施方式中，所述输出线至少部分沿第二方向延伸；第一释放晶体管的第二极和第二释放晶体管的第二极为一体结构；
所述有源连接部在基底上的正投影与第一释放晶体管的第二极和第二释放晶体管的第二极的一体结构和输出线在基底上的正投影至少部分交叠，且分别与第一释放晶体管的第二极和第二释放晶体管的第二极的一体结构和输出线电连接。
在示例性实施方式中，所述有源连接部的宽度小于所述有源主体部的宽度。
在示例性实施方式中，所述扫描移位寄存器包括：第一扫描电容，第一扫描电容的第二极板与第一扫描电源线电连接，第一扫描电容的第二极板沿第二方向延伸；
第一扫描电容的第二极板在基底上的正投影与第一扫描电源线、第二扫描电源线、第一扫描时钟信号线、第二扫描时钟信号线和扫描初始信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，所述显示区域包括：第一显示区和位于所述第一显示区至少一侧的第二显示区，所述显示基板还包括：位于所述显示区域的发光器件和阳极连接线，像素电路与发光器件电连接；所述像素电路包括：位于所述第二显示区的第一像素电路和第二像素电路，所述发光器件包括：位于所述第一显示区的第一发光器件和位于第二显示区的第二发光器件，第一像素电路与第一发光器件电连接，第二像素电路与第二发光器件电连接；
第一像素电路在基底上的正投影与第一像素电路所连接的第一发光器件在基底上的正投影至少部分交叠；
所述阳极连接线分别与第二发光器件和与第二发光器件所连接的第二像素电路电连接。
在示例性实施方式中，所述驱动结构层还包括：至少部分位于显示区域的第一电源线、数据信号线和数据连接线；所述第一电源线和所述数据信号线至少部分沿第一方向延伸，所述数据连接线至少部分沿第二方向延伸；
所述驱动结构层还包括：依次叠设在第三导电层上的第四导电层和第五导电层；
所述第三导电层至少包括：数据连接线；
所述第四导电层至少包括：第一电源线和数据信号线；
所述第五导电层至少包括：阳极连接线；
所述第五导电层为透明导电层。
在示例性实施方式中，所述驱动结构层还包括：位于所述第三导电层和所述第四导电之间的平坦层，所述平坦层设置有凹槽；
所述静电释放电路在基底上的正投影与凹槽在基底上的正投影至少部分交叠。
在示例性实施方式中，所述驱动结构层还包括：位于非显示区域的至少一条初始供电线和至少部分位于显示区域的至少一条初始信号线；初始供电线位于扫描驱动电路靠近显示区域的一侧，初始供电线至少部分沿第一方向延伸，初始信号线至少部分沿第二方向延伸；所述初始供电线包括相互电连接的第一子初始供电线和第二子初始供电线；
至少一条初始信号线与至少一条初始供电线一一对应，初始信号线，分别与像素电路和对应的初始供电线电连接；
所述第二导电层至少包括：初始信号线；
所述第三导电层至少包括：初始供电线的第一子初始供电线；
所述第四导电层至少包括：初始供电线的第二子初始供电线。
第二方面，本公开还提供了一种显示装置，包括：上述显示基板和感光传感器，所述感光传感器位于所述显示基板内。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示基板的结构示意图；
图2为显示基板的另一示意图；
图3A为一个像素电路的等效电路示意图；
图3B为图3A提供的像素电路的工作时序图；
图4为一种显示基板的结构示意图；
图5A为本公开实施例提供的显示基板的一个局部示意图；
图5B为图5A提供的显示基板沿A-A向的截面图；
图6A为本公开实施例提供的显示基板的另一局部示意图；
图6B为6A提供的显示基板沿A-A向的截面图；
图7A为一种像素电路的结构示意图；
图7B为另一像素电路的结构示意图；
图7C为又一像素电路的结构示意图；
图8为静电释放电路的等效电路图；
图9A为扫描移位寄存器的等效电路图；
图9B为图9A提供的扫描移位寄存器的时序图；
图10A为一种发光移位寄存器的等效电路图；
图10B为图10A提供的发光移位寄存器的时序图；
图11为图5A半导体层和第二导电层的结构示意图；
图12为图6A半导体层和第二导电层的结构示意图；
图13为显示基板的另一结构示意图；
图14为图5A形成半导体层图案后的示意图；
图15为图6A形成半导体层图案后的示意图；
图16为图5A和图6A的第一导电层图案的示意图；
图17为图5A形成第一导电层图案后的示意图；
图18为图6A形成第一导电层图案后的示意图；
图19为图6A形成第二绝缘层图案后的示意图；
图20为图5A的第二导电层图案的示意图；
图21为图5A形成第二导电层图案后的示意图；
图22为图6A的第二导电层图案的示意图；
图23为图6A形成第二导电层图案后的示意图；
图24为图5A形成第三绝缘层图案后的示意图；
图25为图6A形成第三绝缘层图案后的示意图；
图26为图5A和图6A的第三导电层图案的示意图；
图27为图5A形成第三导电层图案后的示意图；
图28为图6A形成第三导电层图案后的示意图；
图29为图5A形成平坦层图案后的示意图；
图30为图6A形成平坦层图案后的示意图；
图31为图5A和图6A的第四导电层图案的示意图；
图32为图5A形成第四导电层图案后的示意图；
图33为图6A形成第四导电层图案后的示意图；
图34为图7B形成半导体层图案后的示意图；
图35为图7C形成半导体层图案后的示意图；
图36为图7B的第一导电层图案的示意图；
图37为图7B形成第一导电层图案后的示意图；
图38为图7C的第一导电层图案的示意图；
图39为图7C形成第一导电层图案后的示意图；
图40为图7B的第二导电层图案的示意图；
图41为图7B形成第二导电层图案后的示意图；
图42为图7C的第二导电层图案的示意图；
图43为图7C形成第二导电层图案后的示意图；
图44为图7B形成第三绝缘层图案后的示意图；
图45为图7C形成第三绝缘层图案后的示意图；
图46为图7B的第三导电层图案的示意图；
图47为图7B形成第三导电层图案后的示意图；
图48为7C的第三导电层图案的示意图；
图49为图7C形成第三导电层图案后的示意图；
图50为图7B形成第四绝缘层图案后的示意图；
图51为图7C形成第四绝缘层图案后的示意图；
图52为图7B的第四导电层图案的示意图；
图53为图7B形成第四导电层图案后的示意图；
图54为图7C的第四导电层图案后的示意图；
图55为图7C形成第四导电层图案的示意图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水 平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
显示基板拥有高分辨率、高反应速度、高亮度、高开口率等优势，具有广泛的应用前景。显示基板中设置有驱动电路以驱动像素电路进行发光，从而实现显示。显示基板的形状一般为圆角矩形，圆角矩形的四个角称为圆角区域，驱动电路在圆角区域是按照圆角区域的弧线走势来摆放的，会造成驱动电路之间产生一些空白区域，空白区域过大会造成刻蚀不均一，影响驱动电路输出信号传输的稳定性，影响显示效果。
图1为一种显示基板的结构示意图，图2为显示基板的另一示意图。如图1和图2所示，显示基板可以包括：显示区域100和非显示区域200。其中，显示基板的显示区域100可以包括：第一显示区A1和位于第一显示区A1至少一侧的第二显示区A2。在一些示例中，第一显示区A1即为透光显示区，第一显示区A1还可以称为屏下摄像头(UDC，Under Display Camera)区域。第二显示区A2即为非透光显示区，第二显示区A2还可以称为正常显示区。例如，感光传感器(如，摄像头、红外传感器)等硬件在显示基板上的正投影可以位于显示基板的第一显示区A1内。
在示例性实施方式中，如图1所示，第一显示区A1可以为圆形，感光传感器在显示基板上的正投影的尺寸可以小于或等于第一显示区A1的尺寸。然而，本实施例对此并不限定。在另一些示例中，第一显示区A1可以为矩形，感光传感器在显示基板上的正投影的尺寸可以小于或等于第一显示区的内切圆的尺寸。
在示例性实施方式中，如图1所示，第一显示区A1可以位于显示区域100的顶部正中间位置。第二显示区A2可以围绕在第一显示区A1的四周。然而，本实施例对此并不限定。例如，第一显示区A1可以位于显示区域100的左上角或者右上角等其他位置。
在一些示例性实施方式中，如图1所示，显示区域可以为矩形，例如圆角矩形。第一显示区A1可以为圆形或椭圆形。然而，本实施例对此并不限定。例如，第一显示区可以为矩形、五边形、或六边形等其他形状。本公开提供的显示基板可以实现四边大角度弯折功能，改善模组贴合褶皱问题，提升了产品良率。
在示例性实施方式中，如图1和图2所示，显示区域可以包括：阵列排布的像素单元，至少一个像素单元包括至少三个子像素P，至少一个子像素包括：像素电路和发光器件。位于同一子像素中的像素电路与发光器件电连接，且设置为驱动发光器件发光。
在示例性实施方式中，像素单元中可以包括红色(R)子像素、绿色(G)子像素和蓝色(B)子像素，或者可以包括红色子像素、绿色子像素、蓝色子像素和白色子像素，本公开在此不做限定。
在示例性实施方式中，像素单元中子像素的形状可以是矩形状、菱形、五边形或六边形。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)或者量子点发光二极管(QLED)。其中，OLED可以包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
在示例性实施方式中，有机发光层可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，如图1所示，非显示区域200可以包括：位于显示区域100一侧的绑定区域和位于显示区域100其他侧的边框区域。
在示例性实施方式中，绑定区域可以包括沿着远离显示区域方向依次设置的引线区、弯折区和复合电路区，引线区连接到显示区域100，弯折区连接到引线区，复合电路区连接到弯折区。
在示例性实施方式中，引线区可以设置多条引出线，一部分多条引出线的一端与显示区域100中的多条数据扇出线对应连接，另一部分多条引出线的一端与显示区域100中的多条数据线对应连接，多条引出线的另一端跨过弯折区连接复合电路区的集成电路，使得 集成电路通过引出线和数据扇出线将数据信号施加到数据线。
在示例性实施方式中，弯折区可以以一曲率弯曲，可以将复合电路区的表面反转，即复合电路区朝向上方的表面可以通过弯折区的弯曲转换成面朝向下方。在示例性实施方式中，当弯折区被弯曲时，复合电路区可以与显示区域100重叠。
在示例性实施方式中，复合电路区可以包括防静电区、驱动芯片区和绑定引脚区，集成电路(Integrate Circuit，简称IC)可以绑定连接在驱动芯片区，柔性电路板(Flexible Printed Circuit，简称FPC)可以绑定连接在绑定引脚区。
在示例性实施方式中，集成电路可以产生用于驱动子像素所需的驱动信号，并且可以将驱动信号提供给在显示区域100中的子像素。例如，驱动信号可以是驱动子像素发光亮度的数据信号。在示例性实施方式中，集成电路可以通过各向异性导电膜或者其它方式绑定连接在驱动芯片区。在示例性实施方式中，绑定引脚区可以设置包括多个引脚(PIN)的焊盘，柔性电路板可以绑定连接到焊盘上。
在示例性实施方式中，如图2所示，显示基板可以包括时序控制器、数据驱动电路、栅极驱动电路和像素阵列，时序控制器分别与数据驱动电路和栅极驱动电路连接，数据驱动电路分别与数据信号线Data连接，栅极驱动电路与栅线连接，栅线可以包括发光信号线EM和扫描信号线Gate中的一种或者多种。像素电路分别与栅线和数据信号线连接。
在示例性实施方式中，时序控制器可以将适合于数据驱动电路的规格的灰度值和控制信号提供到数据驱动电路，可以将适合于栅极驱动电路的规格的时钟信号、起始信号等提供到栅极驱动电路，可以将适合于发光驱动电路的规格的时钟信号、发射停止信号等提供到发光驱动电路。数据驱动电路可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线的数据电压。例如，数据驱动电路可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线。
在示例性实施方式中，栅极驱动电路可以通过从时序控制器接收时钟信号、起始信号等来产生将提供到栅线的扫描信号。例如，栅极驱动电路可以将具有导通电平脉冲的信号顺序地提供到栅线。例如，栅极驱动电路可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的起始信号传输到下一级电路的方式产生扫描信号。
在示例性实施方式中，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。
在示例性实施方式中，图3A为一个像素电路的等效电路示意图。如图3A所示，像素电路可以包括7个晶体管(第一晶体管M1到第七晶体管M7)、1个电容C和8个信号线(数据信号线Data、扫描信号线Gate、复位信号线Reset、发光信号线EM、第一初始信号线INIT1、第二初始信号线INIT2、高电平电源线VDD和低电平电源线VSS)。
在示例性实施方式中，如图3A所示，电容C的第一极板与高电平电源线VDD连接，电容C的第二极板与第一节点N1连接。第一晶体管M1的栅电极与复位信号线Reset连接，第一晶体管M1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第一节点N1连接；第二晶体管M2的栅电极与扫描信号线Gate连接，第二晶体管M2的第一极与第一节点N1连接，第二晶体管M2的第二极与第二节点N2连接。第三晶体管M3的栅电极与第一节点N1连接，第三晶体管M3的第一极与第二节点N2连接，第三晶体管M3的第二极与第三节点N3连接。第四晶体管M4的栅电极与扫描信号线Gate连接，第四晶体管M4的第一极与数据信号线Data连接，第四晶体管M4的第二极与第二节点N2连接。第五晶体管M5的栅电极与发光信号线EM连接，第五晶体管M5的第一极与 高电平电源线VDD连接，第五晶体管M5的第二极与第二节点N2连接；第六晶体管M6的栅电极与发光信号线EM连接，第六晶体管M6的第一极与第三节点N3连接，第六晶体管M6的第二极与发光器件L的第一极连接。第七晶体管M7的栅电极与复位信号线Reset或者扫描信号线Gate连接，第七晶体管M7的第一极与第二初始信号线INIT2连接，第七晶体管M7的第二极与发光器件L的第一极连接，发光器件的第二极与低电平电源线VSS连接，图3A是以第七晶体管M7的栅电极与复位信号线Reset为例进行说明的。
在示例性实施方式中，第一晶体管M1可以称为节点复位晶体管，当复位信号线Reset输入有效电平信号时，第一晶体管M1将初始化电压传输到第一节点N1，以使第一节点N1的电荷量初始化。
在示例性实施方式中，第二晶体管M2可以称为补偿晶体管，当控制信号线SL输入有效电平信号时，第二晶体管M2将第二节点N2的信号传输到第一节点N1，以对第一节点N1的信号进行补偿。
在示例性实施方式中，第三晶体管M3可以称为驱动晶体管，第三晶体管M3根据栅电极与第一极之间的电位差来确定在高电平电源线VDD与低电平电源线VSS之间流动的驱动电流。
在示例性实施方式中，第四晶体管M4可以称为写入晶体管等，当扫描信号线Gate输入有效电平信号时，第四晶体管M4使数据信号线Data的数据电压输入到第三节点N3。
在示例性实施方式中，第五晶体管M5和第六晶体管M6可以称为发光晶体管。当发光信号线EM输入有效电平信号时，第五晶体管M5和第六晶体管M6通过在高电平电源线VDD与低电平电源线VSS之间形成驱动电流路径而使发光器件发光。
在示例性实施方式中，第七晶体管M7可以称为阳极复位晶体管，当复位信号线Reset或者扫描信号线Gate输入有效电平信号时，第七晶体管M7将初始化电压传输到发光器件L的第一极，以使发光器件L的第一极的电荷量初始化。
在示例性实施方式中，高电平电源线VDD的信号为持续提供高电平信号，低电平电源线VSS的信号为低电平信号。
按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，第一晶体管M1到第七晶体管M7可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管M1到第七晶体管M7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管M1到第七晶体管M7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施例中，当显示基板为LTPO显示基板时，第一晶体管T1和第二晶体管T2可以为N型晶体管，其余晶体管为P型晶体管。当显示基板为LTPS显示基板时，第一晶体管M1至第七晶体管M7为P型晶体管。
图3B为图3A提供的像素电路的工作时序图，图3B是以图3A中的晶体管均为P型晶体管为例进行说明的。下面通过图3B示例的像素电路的工作过程说明本公开示例性实施例。在示例性实施方式中，像素电路的工作过程可以包括：
第一阶段A1，称为复位阶段，扫描信号线Gate和发光信号线EM的信号均为高电平信号，复位信号线Reset的信号为低电平信号。复位信号线Reset的信号为高电平信号，第一晶体管M1导通，第一初始信号线INIT1的信号提供至第一节点N1，对电容C进行初始化，清除电容C中原有数据电压,第七晶体管M7导通，第二初始信号线INIT2的初始电压提供至发光器件L的第一极，对发光器件L的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化。扫描信号线Gate和发光信号线EM的信号为高电平信号，第二晶体管M2、第四晶体管M4、第五晶体管M5和第六晶体管M6断开，此阶段发光器件L不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，扫描信号线Gate为低电平信号，发光信号线EM和和复位信号线Reset的信号为高电平信号，数据信号线Data输出数据电压。此阶段由于第一节点N1为低电平信号，因此第三晶体管M3导通。扫描信号线Gate的信号为低电平信号，第二晶体管T2和第四晶体管M4导通，第二晶体管M2和第四晶体管M4导通使得数据信号线Data输出的数据电压经过第二节点N、导通的第三晶体管M3、2第三节点N3和导通的第二晶体管M2提供至第一节点N1，并将数据信号线Data输出的数据电压与第三晶体管M3的阈值电压之差充入电容C，直至第一节点N1的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管M3的阈值电压，确保发光器件L不发光。复位信号线Reset的信号为高电平信号，第一晶体管M1断开。发光信号线EM的信号为高电平信号，第五晶体管M5和第六晶体管M6断开。
第三阶段A3、称为发光阶段，扫描信号线Gate和复位信号线Reset的信号为高电平信号，发光信号线EM的信号为低电平信号。发光信号线EM的信号为低电平信号，第五晶体管M5和第六晶体管M6导通，高电平电源线VDD输出的电源电压通过导通的第五晶体管M5、第三晶体管M3和第六晶体管M6向发光器件L的第一极提供驱动电压，驱动发光器件L发光。
在像素电路驱动过程中，流过第三晶体管M3(驱动晶体管)的驱动电流由栅电极和第一极之间的电压差决定。由于第一节点N1的电压为Vd-|Vth|，因而第三晶体管M3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*[(Vdd-Vd]2
其中，I为流过第三晶体管M3的驱动电流，也就是驱动发光器件L的驱动电流，K为常数，Vgs为第三晶体管M3的栅电极和第一极之间的电压差，Vth为第三晶体管M3的阈值电压，Vd为数据信号线Data输出的数据电压，Vdd为高电平电源线VDD输出的电源电压。
在示例性实施方式中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属箔片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，显示基板可以为LTPO显示基板或者LTPS显示基板。
在示例性实施方式中，显示基板中的栅极驱动电路可以为两种、三种或者多种，取决于显示基板的结构，本公开对此不作任何限定。
FDC显示产品中部分金属导电层包括多个孤立的块状结构，使得金属导电层静电导走的能力较差，静电无法释放会引发部分晶体管烧伤，从而影响显示效果，降低了显示基板的可靠性。
图4为一种显示基板的结构示意图，图5A为本公开实施例提供的显示基板的一个局部示意图，图5B为图5A沿A-A向的截面图，图6A为本公开实施例提供的显示基板的另一局部示意图，图6B为图6A沿A-A向的截面图。如图4、图5A、图5B、图6A和图6B所示，本公开实施例提供的显示基板可以包括：基底10以及设置在基底10上的驱动结构层，基底包括显示区域100和非显示区域200，驱动结构层包括：位于显示区域的多个像素电路和位于非显示区域的栅极驱动电路和静电释放电路ER，栅极驱动电路被配置为向像素电路提供驱动信号，栅极驱动电路包括多个驱动电路。多个驱动电路和静电释放电路沿靠近显示区域的方向排列，静电释放电路ER设置在相邻的两个驱动电路之间，且与相邻的两个驱动电路中任一个电路的至少一条信号线电连接电连接。
在示例性实施方式中，显示基板还可以包括：设置在驱动结构层远离基底一侧的发光结构层以及设置在发光结构层远离基底一侧的封装结构层。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。每个子像素的驱动结构层可以包括构成像素电路的多个晶体管和存储电容，发光结构层可以包括阳极、像素定义层、有机发光层和阴极，阳极通过过孔与像素电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，触控结构层可以包括设置在封装结构层上的第一触控绝缘层、设置在第一触控绝缘层上的第一触控金属层、覆盖第一触控金属层的第二触控绝缘层43、设置在第二触控绝缘层上的第二触控金属层和覆盖第二触控金属层的触控保护层，第一触控金属层可以包括多个桥接电极，第二触控金属层可以包括多个第一触控电极和第二触控电极，第一触控电极或第二触控电极可以通过过孔与桥接电极连接。
本公开通过设置在相邻的驱动电路之间，且与相邻的驱动电路电连接的静电释放电路可以释放栅极驱动电路中的静电，提升显示基板的静电导走能力，提升了显示效果和显示基板的可靠性。
在示例性实施方式中，当显示基板为LTPO显示基板时，多个驱动电路可以包括：沿靠近显示区域依次排布的发光驱动电路、控制驱动电路和扫描驱动电路。其中，控制驱动电路连接像素电路中的N型晶体管，扫描驱动电路连接像素电路中的P型晶体管。示例性地，静电释放电路可以位于发光驱动电路和控制驱动电路之间，且与发光驱动电路和控制驱动电路中任一个电路的至少一条信号线电连接，或者，静电释放电路可以位于控制驱动电路和扫描驱动电路之间，且与控制驱动电路和扫描驱动电路中任一个电路的至少一条信号线电连接。
在示例性实施方式中，如图4所示，当显示基板为LTPS显示基板时，多个驱动电路可以包括：发光驱动电路和扫描驱动电路，扫描驱动电路位于发光驱动电路靠近显示区域100的一侧。
在示例性实施方式中，如图5A和图6A所示，驱动结构层还可以包括：位于非显示区域的发光初始信号线ESTV、第一发光时钟信号线ECK1、第二发光时钟信号线ECK2、第一发光电源线EVGH、第二发光电源线EVGL，扫描初始信号线GSTV、第一扫描时钟信号线GCK1、第二扫描时钟信号线GCK2、第一扫描电源线GVGH和第二扫描电源线GVGL。
在示例性实施方式中，如图5A和图6A所示，发光初始信号线ESTV、第一发光时钟信号线ECK1、第二发光时钟信号线ECK2、第一发光电源线EVGH、第二发光电源线EVGL，扫描初始信号线GSTV、第一扫描时钟信号线GCK1、第二扫描时钟信号线GCK2、第一扫描电源线GVGH和第二扫描电源线GVGL中的任一条沿第一方向D1延伸。
在示例性实施方式中，如图5A和图6A所示，发光驱动电路可以分别与发光初始信号线ESTV、第一发光时钟信号线ECK1、第二发光时钟信号线ECK2、第一发光电源线EVGH和第二发光电源线EVGL电连接。
在示例性实施方式中，如图5A和图6A所示，扫描驱动电路可以分别与扫描初始信号线GSTV、第二扫描时钟信号线GCK2、第一扫描时钟信号线GCK1、第一扫描电源线GVGH和第二扫描电源线GVGL电连接。
在示例性实施方式中，如图5A和图6A所示，第一扫描时钟信号线GCK1和第二扫描时钟信号线GCK2中至少一条可以为双层结构。
在示例性实施方式中，如图5A和图6A所示，第一扫描时钟信号线可以包括：相互电连接的第一子时钟信号线和第二子时钟信号线。第一子时钟信号线和第二子时钟信号线可以异层设置。
在示例性实施方式中，如图5A和图6A所示，第二扫描时钟信号线可以包括：相互电连接的第三子时钟信号线和第四子时钟信号线。第三子时钟信号线和第四子时钟信号线可以异层设置。
在示例性实施方式中，如图5A和图6A所示，发光初始信号线ESTV、第一发光时钟信号线ECK1、第二发光时钟信号线ECK2、第一发光电源线EVGH、第二发光电源线EVGL、第一扫描电源线GVGH、第一扫描时钟信号线GCK1、第二扫描时钟信号线GCK2、扫描初始信号线GSTV和第二扫描电源线GVGL沿靠近显示区域的方向依次排列。
在示例性实施方式中，第一发光电源线EVGH和第一扫描电源线GVGH的信号为高电平信号，第二发光电源线EVGL和第二扫描电源线GVGL的信号为低电平信号。
在示例性实施方式中，如图5A和图6A所示，静电释放电路ER在基底上的正投影与第一扫描电源线GVGH和第二发光电源线EVGL部分交叠，且至少部分静电释放电路位于所述第二发光电源线EVGL和第一扫描电源线GVGH之间。
在示例性实施方式中，图7A为一种像素电路的结构示意图，图7B为一种像素电路的另一结构示意图，图7C为一种像素电路的又一结构示意图。如图5A、图6A、图7A至图7C所示，驱动结构层还可以包括：位于非显示区域的发光输出信号线EOL和扫描输出信号线GOL以及至少部分位于显示区域的发光信号线EM和扫描信号线Gate。扫描输出信号线GOL、发光信号线EM和扫描信号线Gate中的任一条至少部分沿第二方向D2延伸，第一方向D1与第二方向D2相交。
在示例性实施方式中，像素电路，分别与发光信号线EM和扫描信号线Gate连接。
在示例性实施方式中，图5A和图6A所示，发光驱动电路可以包括：多个级联的发光移位寄存器EM-GOA，扫描驱动电路可以包括：多个级联的扫描移位寄存器Gate-GOA。
在示例性实施方式中，发光输出信号线EOL，分别与发光移位寄存器EM-GOA和至少一条发光信号线电连接。图5A和图6A是以发光输出信号线与两条发光信号线为例进行说明的。
在示例性实施方式中，扫描输出信号线GOL，分别与扫描移位寄存器Gate-GOA和扫描信号线电连接。
图8为静电释放电路的等效电路图。如图8所示，在示例性实施方式中，静电释放电路至少可以包括：第一释放晶体管R1和第二释放晶体管R2。其中，第一释放晶体管R1的栅电极和第二极与第一信号端S1连接，第一释放晶体管R1的第一极与第二信号端S2连接；第二释放晶体管R2的栅电极和第一极与第三信号端S3连接，第二释放晶体管R2的第二极与第一信号端S1连接。
在示例性实施方式中，第二信号端S2的信号可以为低电平信号，第三信号端S3的信号可以为高电平信号。
在示例性实施方式中，第一释放晶体管R1和第二释放晶体管R2可以是P型晶体管，或者可以是N型晶体管。静电释放电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一释放晶体管R1和第二释放晶体管R2可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一释放晶体管R1和第二释放晶体管R2可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。
在示例性实施方式中，静电释放电路的工作原理为：当第一信号端S1的信号的电压值过高(例如高于第三信号端S3的信号的电压值)时，第二释放晶体管R2导通，此时，第一信号端S1的信号的电压值会趋近于第三信号端S3的信号的电压值，而不至于过高。同理，当第一信号端S1的信号的电压值过低(例如低于第二信号端S2的信号的电压值)时，此时，第一释放晶体管R1导通，此时，第一信号端S1的信号的电压值会趋近于第二信号端S2的信号的电压值，而不至于过低。
在示例性实施方式中，静电释放电路的第一信号端可以与发光输出信号线EOL电连接，静电释放电路的第二信号端可以与第二发光电源线EVGL电连接，静电释放电路的第三信号端可以与第一扫描电源线GVGH电连接。
在示例性实施方式中，第二发光电源线EVGL和第一扫描电源线GVGH之间的距离约为8微米至15微米。示例性地，第二发光电源线EVGL和第一扫描电源线GVGH之间的距离可以为10微米。
在示例性实施方式中，像素电路包括：多个晶体管和电容、发光移位寄存器包括多个发光晶体管和多个发光电容，扫描移位寄存器包括多个扫描晶体管和多个扫描电容，发光电容和扫描电容均包括第一极板和第二极板，驱动结构层包括：依次叠设的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；
在示例性实施方式中，半导体层可以至少包括：多个晶体管的有源层、多个发光晶体管的有源层、多个扫描晶体管的有源层、第一释放晶体管的有源层和第二释放晶体管的有源层。
在示例性实施方式中，第一导电层可以至少包括：发光信号线、扫描信号线、多个晶体管的栅电极、多个发光晶体管的栅电极、电容的第一极板、多个发光电容的第一极板，多个扫描晶体管的栅电极、多个扫描电容的第一极板、第一释放晶体管的栅电极和第二释 放晶体管的栅电极。
在示例性实施方式中，第二导电层可以至少包括：电容的第二极板、多个发光电容的第二极板、多个扫描电容的第二极板、扫描输出信号线和发光输出信号线。
在示例性实施方式中，第三导电层可以至少包括：发光初始信号线、第一发光时钟信号线、第二发光时钟信号线、第一发光电源线、第二发光电源线，扫描初始信号线、第一扫描时钟信号线的第一子时钟信号线、第二扫描时钟信号线的第三子时钟信号线、第一扫描电源线、第二扫描电源线、多个晶体管的第一极和第二极、多个发光晶体管的第一极和第二极、多个扫描晶体管的第一极和第二极、第一释放晶体管的第一极和第二极以及第二释放晶体管的第一极和第二极。
在示例性实施方式中，第四导电层可以至少包括：第一扫描时钟信号线的第二子时钟信号线和第二扫描时钟信号线的第四子时钟信号线。
在示例性实施方式中，如图5A和图6A所示，多个发光晶体管的第一极和第二极位于第一发光电源线EVGH和第二发光电源线EVGL之间，第一释放晶体管的第一极和第二极至第二释放晶体管的第一极和第二极位于第二发光电源线EVGL和第一扫描电源线GVGH之间，部分扫描晶体管的第一极和第二极位于扫描初始信号线GSTV和第二扫描电源线GVGL之间，另一部分扫描晶体管的第一极和第二极可以位于第二扫描电源线GVGL靠近显示区域的一侧。
在示例性实施方式中，扫描移位寄存器可以为8T2C电路结构，发光移位寄存器可以为10T3C或者12T3C电路结构，本公开对此不做任何限定。
在示例性实施方式中，图9A为扫描移位寄存器的等效电路图。如图9A所示，扫描移位寄存器可以包括：第一扫描晶体管GT1至第八扫描晶体管GT8、第一扫描电容GC1和第二扫描电容GC2。
在示例性实施方式中，如图9A所示，第一扫描晶体管GT1的栅电极与第一时钟信号端CK1电连接，第一扫描晶体管GT1的第一极与输入端GIN电连接，第一扫描晶体管GT1的第二极与第一节点N1电连接；第二扫描晶体管GT2的栅电极与第一节点N1电连接，第二扫描晶体管GT2的第一极与第一时钟信号端CK1电连接，第二扫描晶体管GT2的第二极与第二节点N2电连接；第三扫描晶体管GT3的栅电极与第一时钟信号端CK1电连接，第三扫描晶体管GT3的第一极与第二电源端VGL电连接，第三扫描晶体管GT3的第二极与第二节点N2电连接；第四扫描晶体管GT4的栅电极与第二节点N2电连接，第四扫描晶体管GT4的第一极与第一电源端VGH电连接，第四扫描晶体管GT4的第二极与输出端GOUT电连接；第五扫描晶体管GT5的栅电极与第三节点N3电连接，第五扫描晶体管GT5的第一极与第二时钟信号端CK2电连接，第五扫描晶体管GT5的第二极与输出端GOUT电连接；第六扫描晶体管GT6的栅电极与第二节点N2电连接，第六扫描晶体管GT6的第一极与第一电源端VGH电连接，第六扫描晶体管GT6的第二极与第七扫描晶体管GT7的第一极电连接；第七扫描晶体管GT7的栅电极与第二时钟信号端CK2电连接，第七扫描晶体管GT7的第二极与第一节点N1电连接；第八扫描晶体管GT8的栅电极与第二电源端VGL电连接，第八扫描晶体管GT8的第一极与第一节点N1电连接，第八扫描晶体管GT8的第二极与第三节点N3电连接；第一扫描电容GC1的第一极板GC11与第二节点N2电连接，第一扫描电容GC1的第二极板GC12与第一电源端VGH电连接；第二扫描电容GC2的第一极板GC21与第三节点N3电连接，第二扫描电容GC2的第二极板GC22与输出端GOUT电连接。
在示例性实施方式中，第一扫描晶体管GT1至第八扫描晶体管GT8可以为P型晶体 管或者可以为N型晶体管。
在示例性实施方式中，第一电源端VGH持续提供高电平信号，第二电源端VGL持续提供低电平信号。
图9B为图9A提供的扫描移位寄存器的时序图，图9B是以第一扫描晶体管GT1至第八扫描晶体管GT8为P型晶体管为例，如图9B所示，一种示例性实施例提供的扫描移位寄存器的工作过程包括以下阶段：
在输入阶段B1，第一时钟信号端CK1和输入端GIN的信号为低电平信号，第二时钟信号端CK2的信号为高电平信号。由于第一时钟信号端CK1的信号为低电平信号，第一扫描晶体管GT1导通，输入端GIN的信号经由第一扫描晶体管GT1传输至第一节点N1。由于第八扫描晶体管GT8的信号接收第二电源端VGL的低电平信号，从而第八扫描晶体管GT8处于开启状态。第三节点N3的电平可以第五扫描晶体管GT5导通，第二时钟信号端CK2的信号经由第五扫描晶体管GT5传输至输出端GOUT，即在输入阶段B1，输出端GOUT为高电平信号的第二时钟信号端CK2的信号。另外，由于第一时钟信号端CK1的信号为低电平信号，第三扫描晶体管GT3导通，第二电源端VGL的低电平信号经由第三扫描晶体管GT3传输至第二节点N2。此时，第四扫描晶体管GT4和第六扫描晶体管GT6均导通。由于第二时钟信号端CK2的信号为高电平信号，第七扫描晶体管GT7截止。
在输出阶段B2，第一时钟信号端CK1的信号为高电平信号，第二时钟信号端CK2的信号为低电平信号，输入端GIN的信号为高电平信号。第五扫描晶体管GT5导通，第二时钟信号端CK2的信号经由第五扫描晶体管GT5作为输出端GOUT的信号。在输出阶段B2，第二扫描电容GC2的连接输出端GOUT的一端的信号变为第二电源端VGL的信号，由于第二扫描电容GC2的自举作用，第八扫描晶体管GT8截止，第五扫描晶体管GT5可以更好地打开，输出端GOUT的信号为低电平信号。另外，第一时钟信号端CK1的信号为高电平信号，从而第一扫描晶体管GT1和第三扫描晶体管GT3均截止。第二扫描晶体管GT2导通，第一时钟信号端CK1的高电平信号经由第二扫描晶体管GT2传输至第二节点N2，由此，第四扫描晶体管GT4和第六扫描晶体管GT6均截止。由于第二时钟信号端CK2的信号为低电平信号，第七扫描晶体管GT7导通。
在缓冲阶段B3，第一时钟信号端CK1和第二时钟信号端CK2的信号均为高电平信号，输入端GIN的信号为高电平信号，第五扫描晶体管GT5导通，第二时钟信号端CK2经由第五扫描晶体管GT5作为输出信号。第一时钟信号端CK1的信号为高电平信号，从而第一扫描晶体管GT1和第三扫描晶体管GT3均截止，第八扫描晶体管GT8导通，第二扫描晶体管GT2导通，第一时钟信号端CK1的高电平信号经由第二扫描晶体管GT2传输至第二节点N2，由此，第四扫描晶体管GT4和第六扫描晶体管GT6均截止。由于第二时钟信号端CK2的信号为高电平信号，第七扫描晶体管GT7截止。
在稳定阶段B4的第一子阶段B41中，第一时钟信号端CK1的信号为低电平信号，第二时钟信号端CK2和输入端GIN的信号为高电平信号。由于第一时钟信号端CK1的信号为低电平信号，第一扫描晶体管GT1导通，输入端GIN的信号经由第一扫描晶体管GT1传输至第一节点N1，第二扫描晶体管GT2截止。由于第八扫描晶体管GT8处于开启状态，第五扫描晶体管GT5截止。由于第一时钟信号端CK1的信号为低电平，第三扫描晶体管GT3导通，第四扫描晶体管GT4和第六扫描晶体管GT6均导通，第一电源端VGH的高电平信号经由第四扫描晶体管GT4传输至输出端GOUT，即输出端GOUT的信号为高电平信号。
在稳定阶段B4的第二子阶段B42中，第一时钟信号端CK1的信号为高电平信号，第二时钟信号端CK2的信号为低电平信号，输入端GIN的信号为高电平信号。第五扫描晶体管GT5和第二扫描晶体管GT2均截止。第一时钟信号端CK1的信号为高电平信号，从而第一扫描晶体管GT1和第三扫描晶体管GT3均截止，由于第一扫描电容GC1的保持作用下，第四扫描晶体管GT4和第六扫描晶体管GT6均导通，高电平信号经由第四扫描晶体管GT4传输至输出端GOUT，即输出端GOUT的信号为高电平信号。
在第二子阶段B42中，由于第二时钟信号端CK2的信号为低电平信号，第七扫描晶体管GT7导通，从而高电平信号经由第六扫描晶体管GT6和第七扫描晶体管GT7被传输至第三节点N3和第一节点N1，以使第三节点N3和第一节点N1的信号保持为高电平信号。
在第三子阶段B43中，第一时钟信号端CK1和第二时钟信号CK2的信号均为高电平信号，输入端GIN的信号为高电平信号。第五扫描晶体管GT5和第二扫描晶体管GT2截止。第一时钟信号端CK1的信号为高电平信号，从而第一扫描晶体管GT1和第三扫描晶体管GT3均截止，第四扫描晶体管GT4和第六扫描晶体管GT6均导通。高电平信号经由第四扫描晶体管GT4传输至输出端GOUT，即输出端GOUT的信号为高电平信号。
图10A为一种发光移位寄存器的等效电路图。如图10A所示，发光移位寄存器可以包括：第一发光晶体管ET1至第十发光晶体管ET10以及第一发光电容EC1至第三发光电容EC3。
在示例性实施方式中，如图10A所示，第一发光晶体管ET1的栅电极与第一时钟信号端CK1电连接，第一发光晶体管ET1的第一极与输入端EIN电连接，第一发光晶体管ET1的第二极与第一节点N1电连接；第二发光晶体管ET2的栅电极与第一节点N1电连接，第二发光晶体管ET2的第一极与第一时钟信号端CK1电连接，第二发光晶体管ET2的第二极与第二节点N2电连接；第三发光晶体管ET3的栅电极与第一时钟信号端CK1电连接，第三发光晶体管ET3的第一极与第二电源端VGL电连接，第三发光晶体管ET3的第二极与第二节点N2电连接；第四发光晶体管ET4的栅电极与第二时钟信号端CK2电连接，第四发光晶体管ET4的第一极与第一节点N1电连接，第四发光晶体管ET4的第二极与第五发光晶体管ET5的第一极电连接；第五发光晶体管ET5的栅电极与第二节点N2电连接，第五发光晶体管ET5的第二极与第一电源端VGH电连接；第六发光晶体管ET6的第一极与第二时钟信号端CK2电连接，第六发光晶体管ET6的第二极与第三节点N3电连接；第七发光晶体管ET7的栅电极与第二时钟信号端CK2电连接，第七发光晶体管ET7的第一极与第三节点N3电连接，第七发光晶体管ET7的第二极与第九发光晶体管ET9的栅电极电连接；第八发光晶体管ET8的栅电极与第一节点N1电连接，第八发光晶体管ET8的第一极与第一电源端VGH电连接，第八发光晶体管ET8的第二极与第九发光晶体管ET9的栅电极电连接；第九发光晶体管ET9的第一极与第一电源端VGH电连接，第九发光晶体管ET9的第二极与输出端EOUT电连接；第十发光晶体管ET10的第一极与第二电源端VGL电连接，第十发光晶体管ET10的第二极与输出端EOUT电连接；第一发光电容EC1的第一极板与第六发光晶体管ET6的栅电极电连接，第一发光电容EC1的第二极板与第三节点N3电连接；第二发光电容EC2的第一极板EC21与第九发光晶体管ET9的栅电极电连接，第二发光电容EC2的第二极板EC22与第一电源端VGH电连接；第三发光电容EC3的第一极板E31与第十发光晶体管ET10的栅电极电连接，第三发光电容EC3的第二极板EC32与第二电源端VGL电连接。
在示例性实施方式中，第一发光晶体管ET1至第十发光晶体管ET10可以为P型晶体管或者可以为N型晶体管。
在示例性实施方式中，第一电源端VGH持续提供高电平信号，第二电源端VGL持续提供低电平信号。
图10B为图10A提供的发光移位寄存器的时序图。图10B是以第一发光晶体管ET1至第十发光晶体管ET10为P型晶体管为例，一种示例性实施例提供的发光移位寄存器的工作过程可以包括以下阶段：
第一阶段C1，第一时钟信号端CK1的信号为低电平，所以第一发光晶体管ET1和第三发光晶体管ET3导通，导通的第一发光晶体管ET1将输入端EIN的高电平信号传输至第一节点N1，第一节点N1的信号变为高电平信号，所以第二发光晶体管ET2、第八发光晶体管ET8以及第十发光晶体管ET10截止。另外，导通的第三发光晶体管ET3将第二电源端VGL的低电平信号传输至第二节点N2，第二节点N2的信号变为低电平信号，所以第五发光晶体管ET5和第六发光晶体管ET6导通。由于第二时钟信号端CK2的信号为高电平信号，所以第七发光晶体管ET7截止。另外，由于第三发光电容EC3的存储作用，第九发光晶体管ET9截止。在第一阶段C1中，由于第九发光晶体管ET9以及第十发光晶体管ET10均截止，输出端EOUT的信号保持之前的低电平。
第二阶段C2，第二时钟信号端CK2的信号为低电平，所以第四发光晶体管ET4、第七发光晶体管ET7导通。由于第一时钟信号端CK1的信号为高电平，所以第一发光晶体管ET1和第三发光晶体管ET3截止。由于第一发光电容EC1的存储作用，所以第二节点N2可以继续保持上一阶段的低电平，所以第五发光晶体管ET5以及第六发光晶体管ET6导通。第一电源端VGH的高电平信号通过导通的第五发光晶体管ET5以及第四发光晶体管ET4传输至第一节点N1，第一节点N1的电平继续保持上一阶段的高电平，所以第二发光晶体管ET2、第八发光晶体管ET8以及第十发光晶体管ET10截止。另外，第二时钟信号端CK2的低电平信号通过导通的第六发光晶体管ET6以及第七发光晶体管ET7被传输至第九发光晶体管ET9的栅电极，第九发光晶体管ET9导通，导通的第九发光晶体管ET9将第一电源端VGH的高电平信号输出，输出端EOUT的信号为高电平。
第三阶段C3，第一时钟信号端CK1的信号为低电平，所以第一发光晶体管ET1以及第三发光晶体管ET3导通。第二时钟信号端CK2的信号为高电平，所以第四发光晶体管ET4以及第七发光晶体管ET7截止。由于第三发光电容EC3的存储作用，第九发光晶体管ET9保持导通状态，导通的第九发光晶体管ET9将第一电源端VGH的高电平信号输出，输出端EOUT的信号仍然为高电平。
第四阶段C4，第一时钟信号端CK1的信号为高电平，所以第一发光晶体管ET1以及第三发光晶体管ET3截止。第二时钟信号端CK2的信号为低电平，所以第四发光晶体管ET4以及第七发光晶体管ET7导通。由于第二发光电容EC2的存储作用，所以第一节点N1的电平保持上一阶段的高电平，第二发光晶体管ET2、第八发光晶体管ET8以及第十发光晶体管ET10截止。由于第一发光电容EC1的存储作用，第二节点N2继续保持上一阶段的低电平，第五发光晶体管ET5以及第六发光晶体管ET6导通。另外，第二时钟信号端CK2的低电平信号通过导通的第六发光晶体管ET6以及第七发光晶体管ET7被传输至第九发光晶体管ET9的栅电极，所以第九发光晶体管ET9导通，导通的第九发光晶体管ET9将第一电源端VGH的高电平信号输出，输出端EOUT的信号仍然为高电平。
第五阶段C5，第一时钟信号端CK1的信号为低电平，所以第一发光晶体管ET1以及第三发光晶体管ET3导通。第二时钟信号端CK2的信号为高电平，所以第四发光晶体管ET4以及第七发光晶体管ET7截止。导通的第一发光晶体管ET1将输入端EIN的高电平信号传输至第一节点N1，第一节点N1的信号变为低电平信号，所以第二发光晶体管ET2、第八发光晶体管ET8以及第十发光晶体管ET10导通。导通的第二发光晶体管ET2 将低电平的第一时钟信号端CK1的信号传输至第二节点N2，可以拉低第二节点N2的电平，所以第二节点N2继续保持上一阶段的低电平，第五发光晶体管ET5以及第六发光晶体管ET6导通。另外，导通的第八发光晶体管ET8将第一电源端VGH的高电平信号传输至第九发光晶体管ET9的栅电极，所以第九发光晶体管ET9截止。导通的第十发光晶体管ET10将第二电源端VGL的低电平信号输出，输出端EOUT的信号变为低电平。
在示例性实施方式中，图11为图5A提供的显示基板中半导体层和第二导电层的结构示意图，图12为图6A提供的显示基板中半导体层和第二导电层的结构示意图。如图11和图12所示，至少一条发光输出信号线包括：输出连接部COL和至少一条输出线OL，输出连接部COL沿第一方向D1延伸，至少一条输出线OL沿第一方向排布D1。
输出连接部COL，分别与发光移位寄存器和至少一条输出线OL电连接，输出线OL与发光输出信号线所连接的发光信号线一一对应，且与对应的发光信号线电连接。
在示例性实施方式中，如图11所示，图5A提供的显示基板中，输出线OL包括：至少部分沿第二方向D2延伸的输出主体部OLA和沿第一方向D1延伸的输出连接部OLB，输出主体部OLA与输出连接部OLB电连接。
在示例性实施方式中，如图5A所示，第一释放晶体管的第二极和第二释放晶体管的第二极为一体结构，且在基底上的正投影与输出连接部在基底上的正投影至少部分交叠，第一释放晶体管的第二极和第二释放晶体管的第二极的一体结构与输出连接部电连接。
在示例性实施方式中，如图11所示，图5A提供的显示基板中第一释放晶体管的有源层RT11和第二释放晶体管的有源层RT21为一体结构，且沿第二方向D2延伸。输出连接部OLB在基底上的正投影与第一释放晶体管的有源层RT11和第二释放晶体管的有源层RT21的一体结构在基底上的正投影不交叠。
在示例性实施方式中，如图12所示，图6A提供的显示基板中第一释放晶体管的有源层RT11和第二释放晶体管的有源层RT21为一体结构，且包括：有源主体部R1和有源连接部R2，有源主体部R1和有源连接部R2电连接，有源主体部R1和有源连接部R2沿第一方向D1排布。
在示例性实施方式中，如图12所示，有源主体部R1沿第二方向D2延伸，有源连接部R2至少部分沿第一方向D1延伸。
在示例性实施方式中，如图12所示，有源连接部R2的形状为折线形。有源连接部R2的形状为折线形可以增大电阻，使得增大静电消耗，避免栅极驱动电路被烧伤，提升了显示效果以及显示基板的可靠性。
在示例性实施方式中，如图12所示，输出线OL至少部分沿第二方向D2延伸；第一释放晶体管的第二极和第二释放晶体管的第二极为一体结构。有源连接部R2在基底上的正投影与第一释放晶体管的第二极和第二释放晶体管的第二极的一体结构和输出线OL在基底上的正投影至少部分交叠，且分别与第一释放晶体管的第二极和第二释放晶体管的第二极的一体结构和输出线OL电连接。
在示例性实施方式中，如图12所示，有源连接部R2的宽度小于有源主体部R1的宽度。
在示例性实施方式中，如图11和图12所示，扫描移位寄存器包括：第一扫描电容，第一扫描电容的第二极板GC12与第一扫描电源线电连接，第一扫描电容的第二极板GC21沿第二方向D2延伸。
在示例性实施方式中，如图5A、图6A、图11和图12所示，第一扫描电容的第二极 板GC21在基底上的正投影与第一扫描电源线GVGH、第二扫描电源线GVGL、第一扫描时钟信号线GCK1、第二扫描时钟信号线GCK2和扫描初始信号线GSTV在基底上的正投影至少部分交叠。
在示例性实施方式中，图13为显示基板的另一结构示意图。如图13所示，显示区域可以包括：第一显示区A1和位于第一显示区A1至少一侧的第二显示区A2，显示基板还包括：位于显示区域100的发光器件和阳极连接线AL。像素电路与发光器件电连接。像素电路包括：位于第二显示区A2的第一像素电路11和第二像素电路12，发光器件包括：位于第一显示区A1的第一发光器件21和位于第二显示区域的第二发光器件22.第一像素电路11与第一发光器件21电连接，第二像素电路与第二发光器件22电连接。
如图13所示，第一像素电路11在基底上的正投影与第一像素电路11所连接的第一发光器件21在基底上的正投影至少部分交叠。
如图13所示，阳极连接线AL分别与第二发光器件22和与第二发光器件22所连接的第二像素电路12电连接。
在示例性实施方式中，阳极连接线AL可以为透明导电线。
在示例性实施方式中，如图7A至图7C所示，驱动结构层还可以包括：至少部分位于显示区域的第一电源线VDD和数据信号线Data。第一电源线VDD和数据信号线Data至少部分沿第一方向D1延伸。
在示例性实施方式中，位于第一显示区左右两侧的像素电路所在列连接的数据信号线Data沿第一方向D1延伸。
在示例性实施方式中，如图7B所示，驱动结构层还可以包括：位于显示区域的数据连接线DL，数据连接线DL至少部分沿第二方向D2延伸。
在示例性实施方式中，为了保证第一显示区的显示效果，位于第一显示区上下两侧的像素电路所在列连接的数据信号线围设在第一显示区周边，即位于第一显示区上下两侧的像素电路所在列连接的数据信号线呈折线形。位于第一显示区上下两侧的像素电路所在列连接的数据信号线包括：沿第一方向延伸的多个间隔设置的数据主体线以及呈第二方向延伸的多个间隔设置的数据连接线，相邻数据主体线通过数据连接线连接，相邻数据连接线通过数据主体线连接。为了保证数据信号之间不串扰，数据主体线和数据连接线异层设置。
在显示基板中，部分像素电路的结构包括数据连接线，部分像素电路的结构不包括数据连接线。图7B是以包括数据连接线的像素电路的结构为例进行说明的，图7A和图7C是以不包括数据连接线的像素电路的结构为例进行说明的。
在示例性实施方式中，驱动结构层还包括：依次叠设在第三导电层上的第四导电层和第五导电层。
在示例性实施方式中，第三导电层至少包括：数据连接线。
在示例性实施方式中，第四导电层至少包括：第一电源线和数据信号线。
在示例性实施方式中，第五导电层至少包括：阳极连接线。
在示例性实施方式中，如图5A、图6A和图7A至图7C所示，驱动结构层还可以包括：位于非显示区域的至少一条初始供电线和至少部分位于显示区域的至少一条初始信号线；初始供电线位于扫描驱动电路靠近显示区域的一侧，初始供电线至少部分沿第一方向D1延伸，初始信号线至少部分沿第二方向D2延伸。图5和图6是以包括两条初始供电线例如第一条初始供电线INITL1和第二条初始供电线INITL2为例进行说明的。图7A和图7B是以两条初始信号线，第一初始信号线INIT1和第二初始信号线INIT2为例进行说 明的。
在示例性实施方式中，初始信号线与初始供电线一一对应，初始信号线，分别与像素电路和对应的初始供电线电连接。
在示例性实施方式中，初始供电线可以为双层结构。初始供电线可以包括：相互电连接的第一子初始供电线和第二子初始供电线。
在示例性实施方式中，第二导电层至少包括：初始信号线。
在示例性实施方式中，第三导电层至少包括：初始供电线的第一子初始供电线；
在示例性实施方式中，第四导电层至少包括：初始供电线的第二子初始供电线。
在示例性实施方式中，如图5B和图6B所示，驱动结构层还可以包括：第一绝缘层11、第二绝缘层12、第三绝缘层13、第四绝缘层14、平坦层15、第五绝缘层16、第六绝缘层17。第一绝缘层11位于半导体层和第一导电层之间，第二绝缘层12位于第一导电层和第二导电层之间，第三绝缘层13位于第二导电层和第三导电层之间，第四绝缘层14和平坦层15位于第三导电层和第四导电层之间，第五绝缘层16位于第四导电层和第五导电层之间，第六绝缘层17位于第五导电层远离基底的一侧。
在示例性实施方式中，如图5A和图6A所示，平坦层设置有凹槽X。凹槽X的深度可以小于或者等于平坦层的厚度，本公开对此不做任何限定。
在示例性实施方式中，静电释放电路ER在基底上的正投影与凹槽X在基底上的正投影至少部分交叠。本公开通过在平坦层的凹槽位置处设置静电释放电路，可以不增加显示边框所占用的区域，可以实现窄边框。
在示例性实施方式中，凹槽X沿第二方向的长度小于或者等于第二发光电源线EVGL与第一扫描电源线GVGH之间的距离。
在示例性实施方式中，驱动结构层还可以包括：第二电源连接线和第二电源线。第二电源线与第二电源连接线相互电连接。第二电源线与发光器件的阴极电连接。
在示例性实施方式中，第二电源连接线可以位于第三导电层，第二电源线可以位于第四导电层。
在示例性实施方式中，第二电源连接线在基底上的正投影和第二电源线在基底上的正投影至少部分交叠。第二电源线通过第四绝缘层和平坦层之间的过孔与第二电源连接线连接。
在示例性实施方式中，第二电源连接线的形状可以为沿第二方向D2延伸的线性状，且可以位于发光初始信号线远离第一发光时钟信号线的一侧。
在示例性实施方式中，第二电源线的形状可以为沿第二方向D2延伸的线性状，且在基底上的正投影还与发光初始信号线、第一发光时钟信号线、第二发光时钟信号线、第一发光电源线在基底上的正投影至少部分交叠。
在示例性实施方式中，第二电源线上设置有多个过孔。
在示例性实施方式中，第二电源线在基底上的正投影与第二发光电源线在基底上的正投影之间的距离小于第一发光电源线与第二发光电源线之间的距离。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中 的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。图14至图33是以图5A和图6A提供的位于非显示区域的结构为例进行说明的，图34至图55是以图7B和图7C提供的位于显示区域的像素电路为例进行说明的。
(1)在基底上形成半导体层图案，包括：在基底上沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层图案。如图14、图15、图34和图35所示，图14为图5A形成半导体层图案后的示意图，图15为图6A形成半导体层图案后的示意图，图34为图7B形成半导体层图案后的示意图，图35为图7C形成半导体层图案后的示意图。
在示例性实施方式中，如图14、图15、图34和图35所示，半导体层图案可以包括：位于发光移位寄存器的第一发光晶体管的有源层ET11至第十发光晶体管的有源层ET101、位于静电释放电路的第一释放晶体管的有源层RT11至第二释放晶体管的有源层RT21、位于扫描移位寄存器的第一扫描晶体管的有源层GT11至第八扫描晶体管的有源层GT81以及位于像素电路的第一晶体管的有源层M11至第七晶体管的有源层M71。
在示例性实施方式中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属萡片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底的制备。
在示例性实施方式中，如图14和图15所示，第四发光晶体管的有源层ET41和第五发光晶体管的有源层ET51为相互连接的一体结构。第九发光晶体管的有源层ET91和第十发光晶体管的有源层ET101为相互连接的一体结构。
在示例性实施方式中，如图14和图15所示，在第二方向D2上，第一发光晶体管的有源层ET11至第八发光晶体管的有源层ET81位于第九发光晶体管的有源层ET91(也是第十发光晶体管的有源层ET101)远离显示区域的一侧。第七发光晶体管的有源层ET71 位于第八发光晶体管的有源层ET81远离显示区域的一侧。第一发光晶体管的有源层ET11和第四发光晶体管的有源层ET41(也是第五发光晶体管的有源层ET51)位于第二发光晶体管的有源层ET21远离显示区域的一侧，第三发光晶体管的有源层ET31和第六发光晶体管的有源层ET61位于第二发光晶体管的有源层ET21靠近第九发光晶体管的有源层ET91(也是第十发光晶体管的有源层ET101)的一侧。在第一方向D1上，本级发光移位寄存器的第五发光晶体管的有源层ET51位于第四发光晶体管的有源层ET41靠近下一级发光移位寄存器的一侧，本级移位寄存器的第一发光晶体管的有源层ET11至第六发光晶体管的有源层ET61位于第八发光晶体管的有源层ET81靠近上一级发光移位寄存器的一侧。
在示例性实施方式中，如图14和图15所示，第一发光晶体管的有源层ET11至第七发光晶体管的有源层ET71、第九发光晶体管的有源层ET91和第十发光晶体管的有源层ET101的形状可以为沿第一方向D1延伸的条状。第八发光晶体管的有源层ET81的形状可以为沿第二方向D2延伸的条状。
在示例性实施方式中，每个发光晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第四发光晶体管的有源层ET41的第一区ET41-1可以同时作为第五发光晶体管的有源层ET51的第二区ET51-2，第一发光晶体管的有源层ET11的第一区ET11-1和第二区ET11-2、第二发光晶体管的有源层ET21的第一区ET21-1和第二区ET21-2、第三发光晶体管的有源层ET31的第一区ET31-1和第二区ET31-2、第四发光晶体管的有源层ET41的第二区ET41-2、第五发光晶体管的有源层ET51的第一区ET51-1、第六发光晶体管的有源层ET61的第一区ET61-1和第二区ET61-2、第七发光晶体管的有源层ET71的第一区ET71-1和第二区ET71-2、第八发光晶体管的有源层ET81的第一区ET81-1和第二区ET81-2、第九发光晶体管的有源层ET91的第一区ET91-1和第二区ET91-2以及第十发光晶体管的有源层ET101的第一区ET101-1和第二区ET101-2可以单独设置。
在示例性实施方式中，如图14和图15所示，第一释放晶体管的有源RT11和第二释放晶体管的有源层RT21为相互连接的一体结构。第一释放晶体管的有源RT11和第二释放晶体管的有源层RT21位于第九发光晶体管的有源层ET91(也是第十发光晶体管的有源层ET101)靠近显示区域的一侧。
在示例性实施方式中，如图14和图15所示，在第二方向D2上，第二释放晶体管的有源层RT21位于第一释放晶体管的有源RT11靠近显示区域的一侧。
在示例性实施方式中，如图14所示，图3B提供的显示基板中的第一释放晶体管的有源RT11(也是第二释放晶体管的有源层RT21)的形状可以为沿第二方向D2延伸的条状。
在示例性实施方式中，如图15所示，图3C提供的显示基板中的第一释放晶体管的有源RT11(也是第二释放晶体管的有源层RT21)可以包括：有源主体部R1和有源连接部R2。有源主体部R1和有源连接部R2为相互连接的一体结构，且沿第一方向D1排布。
在示例性实施方式中，如图15所示，有源主体部R1的形状可以为沿第二方向D2延伸的条状，有源连接部R2可以为至少部分沿第一方向D1延伸的折线型。
在示例性实施方式中，如图15所示，有源连接部R2的宽度可以小于有源主体部R1的宽度。
在示例性实施方式中，每个释放晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一释放晶体管的有源层RT11的第 二区RT11-2可以同时作为第二释放晶体管的有源层RT21的第二区RT21-2。第一释放晶体管的有源层RT11的第一区RT11-1和第二释放晶体管的有源层RT21的第一区RT21-1可以单独设置。
在示例性实施方式中，如图15所示，第一释放晶体管的有源层RT11的第二区RT11-2(第二释放晶体管的有源层RT21的第二区RT21-2)包括有源主体部的中间段以及有源连接部R2。
在示例性实施方式中，如图14和图15所示，第一扫描晶体管的有源层GT11、第六扫描晶体管的有源层GT61和第七扫描晶体管的有源层GT71为相互连接的一体结构。第二扫描晶体管的有源层GT21和第三扫描晶体管的有源层GT31为相互连接的一体结构。第四扫描晶体管的有源层GT41和第五扫描晶体管的有源层GT51为相互连接的一体结构。
在示例性实施方式中，如图14和图15所示，在第二方向D2上，第一扫描晶体管的有源层GT11至第三扫描晶体管的有源层GT31、第五扫描晶体管的有源层GT51至第八扫描晶体管的有源层GT81位于第四扫描晶体管的有源层GT41(也是第五晶体管的有源层GT51)远离显示区域的一侧，且位于第一释放晶体管的有源RT11(也是第二释放晶体管的有源层RT21)靠近显示区域的一侧。第二扫描晶体管的有源层GT21(也是第三扫描晶体管的有源层GT31)位于第一扫描晶体管的有源层GT11(第六扫描晶体管的有源层GT61和第七扫描晶体管的有源层GT71)和第八扫描晶体管的有源层GT81之间。第一扫描晶体管的有源层GT11(第六扫描晶体管的有源层GT61和第七扫描晶体管的有源层GT71)位于第二扫描晶体管的有源层GT21(也是第三扫描晶体管的有源层GT31)靠近第一释放晶体管的有源RT11(也是第二释放晶体管的有源层RT21)的一侧，第八扫描晶体管的有源层GT81位于第二扫描晶体管的有源层GT21(也是第三扫描晶体管的有源层GT31)靠近第四扫描晶体管的有源层GT41(也是第五晶体管的有源层GT51)的一侧。在第一方向D1上，本级扫描移位寄存器的第四扫描晶体管的有源层GT41位于第五晶体管的有源层GT51靠近下一级扫描移位寄存器的一侧。
在示例性实施方式中，如图14和图15所示，第一扫描晶体管的有源层GT11、第四扫描晶体管的有源层GT41、第五晶体管的有源层GT51、第六扫描晶体管的有源层GT61、第七扫描晶体管的有源层GT71、第八扫描晶体管的有源层GT81的形状可以为沿第一方向D1延伸的线形状。第二扫描晶体管的有源层GT21的形状可以为沿第二方向D2延伸的线形状。第三扫描晶体管的有源层GT31的形状可以为水平翻转的“7”字型。
在示例性实施方式中，每个扫描晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一扫描晶体管的有源层GT11的第二区GT11-2可以作为第七扫描晶体管的有源层GT71的第二区GT71-2，第二扫描晶体管的有源层GT21的第二区GT21-2可以作为第三扫描晶体管的有源层GT31的第二区GT31-2，第四扫描晶体管的有源层GT41的第二区GT41-2可以同时作为第五扫描晶体管的有源层GT51的第二区GT51-2。第六扫描晶体管的有源层GT61的第二区GT61-2可以作为第七扫描晶体管的有源层GT71的第二区GT71-1。
在示例性实施方式中，如图34和图35所示，同一子像素中的第一晶体管的有源层M11至第七晶体管的有源层M71为相互连接的一体结构。
在示例性实施方式中，如图34和图35所示，在第二方向D2上，第二晶体管的有源层M21和第六晶体管的有源层M61可以位于本子像素中第三晶体管的有源层M31的同一侧，第四晶体管的有源层M41和第五晶体管的有源层M51可以位于本子像素中第三晶体管的有源层M31的同一侧，第二晶体管的有源层M21和第四晶体管的有源层M41可 以位于本子像素的第三晶体管的有源层M31的不同侧。在第一方向D1上，本行子像素中第一晶体管的有源层M11、第二晶体管的有源层M21和第四晶体管的有源层M41可以位于本子像素中第三晶体管的有源层M31远离上一行子像素的一侧，本子子像素中的第五晶体管的有源层M51和第六晶体管的有源层M61和第七晶体管的有源层M71可以位于本子像素中第三晶体管的有源层M31靠近上一行子像素的一侧。
在示例性实施方式中，如图34和图35所示，第一晶体管的有源层M11的形状可以呈“n”字形，第五晶体管的有源层M51和第六晶体管的有源层M61的形状可以呈“L”字形，第三晶体管的有源层M31的形状可以呈“Ω”字形，第四晶体管的有源层M41和第七晶体管的有源层M71的形状可以呈“I”字形。
在示例性实施方式中，如图34所示，第二晶体管的有源层M21的形状可以呈包括两处弯折的折线形。
在示例性实施方式中，如图35所示，第二晶体管的有源层M21的形状可以呈“L”字形
在示例性实施方式中，如图34和图35所示，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一晶体管的有源层M11的第二区M11-2可以作为第二晶体管的有源层M21的第一区M21-1，第三晶体管的有源层M31的第一区M31-1可以同时作为第四晶体管的有源层M41的第二区M41-2和第五晶体管的有源层M51的第二区M51-2，第三晶体管的有源层M31的第二区M31-2可以同时作为第二晶体管的有源层M21的第二区M21-2和第六晶体管的有源层M61的第一区M61-1，第六晶体管的有源层M61的第二区M61-2可以作为第七晶体管的有源层M71的第二区M71-2，第一晶体管的有源层的第一区M11-1、第四晶体管的有源层M41的第一区M41-1、第五晶体管的有源层M51的第一区M51-1和第七晶体管的有源层M71的第一区M71-1可以单独设置。
(2)形成第一导电层图案，包括：在形成有前述图案的基底上沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一绝缘薄膜和第一导电薄膜进行图案化，形成第一绝缘层图案以及设置在第一绝缘层图案上的第一导电层图案，如图16至图18以及图36至图39所示，图16为图5A和图6A的第一导电层图案的示意图，图17为图5A形成第一导电层图案后的示意图，图18为图6A提供的显示基板形成第一导电层图案后的示意图，图36为图7B的第一导电层图案的示意图，图37为图7B形成第一导电层图案后的示意图，图38为图7C的第一导电层图案的示意图，图39为图7C形成第一导电层图案后的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，如图16至图18以及图36至图39所示，第一导电层图案至少可以包括：位于发光移位寄存器的第一发光晶体管的栅电极ET12至第十发光晶体管的栅电极ET102以及第一发光电容的第一极板EC11至第三发光电容的第一极板EC31、位于静电释放电路的第一释放晶体管的栅电极RT12和第二释放晶体管的栅电极RT22、位于扫描移位寄存器的第一扫描晶体管的栅电极GT12至扫描发光晶体管的栅电极GT82以及第一扫描电容的第一极板GC11和第二扫描电容的第一极板GC21、第一信号连接线L1和第二信号连接线L2、复位信号线Reset、扫描信号线Gate、发光信号线EM、第一晶体管的栅电极M11至第七晶体管的栅电极M71以及电容的第一极板C1。
在示例性实施方式中，如图16至图18所示，第一发光晶体管的栅电极ET12和第三发光晶体管的栅电极ET32为相互连接的一体结构。第二发光晶体管的栅电极ET22、第八发光晶体管的栅电极ET82、第十发光晶体管的栅电极ET102和第三发光电容的第一极 板EC31为相互连接的一体结构。第五发光晶体管的栅电极ET52、第六发光晶体管的栅电极ET62和第一发光电容的第一极板EC11为相互连接的一体结构。第九发光晶体管的栅电极ET2与第二发光电容的第一极板EC21为相互连接的一体结构。第四发光晶体管的栅电极ET42和第七发光晶体管的栅电极ET72可以单独设置。
在示例性实施方式中，如图16至图18所示，在第二方向D2上，第三发光电容的第一极板EC31位于第一发光电容的第一极板EC11靠近显示区域的一侧，第二发光晶体管的栅电极ET22位于第三发光电容的第一极板EC31远离显示区域的一侧，第十发光晶体管的栅电极ET102位于第三发光电容的第一极板EC31靠近显示区域的一侧，第九发光晶体管的栅电极ET92位于第二发光电容的第一极板EC21靠近显示区域的一侧，第五发光晶体管的栅电极ET52位于第一发光电容的第一极板EC11远离显示区域的一侧，第六发光晶体管的栅电极ET62位于第一发光电容的第一极板EC11靠近显示区域的一侧。在第一方向D1上，本级发光移位寄存器的第八发光晶体管的栅电极ET82位于第三发光电容的第一极板EC31靠近下一级发光移位寄存器的一侧。本级移位发光移位寄存器的第一发光电容的第一极板EC11和第三发光电容的第一极板EC31位于第二发光电容的第一极板EC21靠近上一级发光移位寄存器的一侧。
在示例性实施方式中，如图16至图18所示，第一发光晶体管的栅电极ET12、第四发光晶体管的栅电极ET42、第五发光晶体管的栅电极ET52、第六发光晶体管的栅电极ET62和第七发光晶体管的栅电极ET72的形状可以为至少部分沿第二方向D2延伸的条状。
在示例性实施方式中，如图16至图18所示，第二发光晶体管的栅电极ET22的形状可以为矩形状，第二发光晶体管的栅电极ET22上设置有开口，开口的形状可以为矩形状，可以位于第二发光晶体管的栅电极ET22的中部，使第二发光晶体管的栅电极ET22形成环形结构。
在示例性实施方式中，如图16至图18所示，第三发光晶体管的栅电极ET32的形状可以为倒立的“T”字型。
在示例性实施方式中，如图16至图18所示，第八发光晶体管的栅电极ET82的形状可以为至少部分沿第一方向D1延伸的条状，可以为折线。
在示例性实施方式中，如图16至图18所示，第九发光晶体管的栅电极ET92的形状可以包括沿第一方向D1延伸的第一连接段以及多个沿第二方向D2延伸的第一分支段，第一连接段与第二电容的第一极板连接，第一分支段位于第一连接段靠近显示区域的一侧，第九发光晶体管的栅电极ET92的形状可以呈梳妆，第一连接段作为梳背，第一分支段作为梳齿。
在示例性实施方式中，如图16至图18所示，第十发光晶体管的栅电极ET102的形状可以包括多个沿第二方向D2延伸的第二分支段，多个第二分支段与第三发光电容的第一极板EC31可以呈梳状结构，第三发光电容的第一极板作为梳背，多个第二分支段作为梳齿。
在示例性实施方式中，如图16至图18所示，第一发光电容的第一极板EC11的形状可以为至少部分沿第一方向D1延伸的条状，且在远离显示区域的一侧设置有凸起。
在示例性实施方式中，如图16至图18所示，第二发光电容的第一极板EC21的形状可以为沿第二方向D2延伸的条状。
在示例性实施方式中，如图16至图18所示，第三发光电容的第一极板EC31的形状可以为沿第一方向D1延伸的条状。
在示例性实施方式中，如图16至图18所示，第一发光晶体管的栅电极ET12跨设在第一发光晶体管的有源层的沟道区上，第二发光晶体管的栅电极ET22跨设在第二发光晶体管的有源层的沟道区上，第三发光晶体管的栅电极ET32跨设在第三发光晶体管的有源层的沟道区上，第四发光晶体管的栅电极ET42跨设在第四发光晶体管的有源层的沟道区上，第五发光晶体管的栅电极ET52的两个第一分支段ET55跨设在第五发光晶体管的有源层的沟道区上，第六发光晶体管的栅电极ET62跨设在第一发光晶体管的有源层的沟道区上，第七发光晶体管的栅电极ET72跨设在第七发光晶体管的有源层的沟道区上，第八发光晶体管的栅电极ET82跨设在第八发光晶体管的有源层的沟道区上，第九发光晶体管的栅电极ET92的多个第一分支段跨设在第九发光晶体管的有源层的沟道区上，第十发光晶体管的栅电极ET102跨设在第十发光晶体管的有源层的沟道区上，也就是说，至少一个发光晶体管的栅电极的延伸方向与有源层的沟道区的延伸方向相互垂直。
在示例性实施方式中，如图16至图18所示，由于第二发光晶体管的栅电极ET22为环形结构，因此，第二发光晶体管为双栅结构。
在示例性实施方式中，如图16至图18所示，第一释放晶体管的栅电极RT12和第二释放晶体管的栅电极RT22的形状可以为沿第一方向D1延伸的条状。
在示例性实施方式中，如图16至图18所示，第一释放晶体管的栅电极RT12跨设在第一晶体管的有源层的沟道区上，第二释放晶体管的栅电极RT22跨设在第二晶体管的有源层的沟道区上，也就是说，至少一个释放晶体管的栅电极的延伸方向与有源层的延伸方向相互垂直。
在示例性实施方式中，如图16至图18所示，第一扫描晶体管的栅电极GT12和第三扫描晶体管的栅电极GT32为相互连接的一体结构。第四扫描晶体管的栅电极GT42、第六扫描晶体管的栅电极GT62和第一扫描电容的第一极板GC31为相互连接的一体结构。第五扫描晶体管的栅电极GT52和第二扫描电容的第一极板EC21为相互连接的一体结构。第二扫描晶体管的栅电极GT22、第七扫描晶体管的栅电极GT72和第八扫描晶体管的栅电极GT82可以单独设置。
在示例性实施方式中，如图16至图18所示，在第二方向D2上，第一扫描电容的第一极板GC11位于第二扫描电容的第一极板GC21远离显示区域的一侧，第五扫描晶体管的栅电极GT52位于第二扫描电容的第一极板EC21远离显示区域的一侧，第四扫描晶体管的栅电极GT42位于第一扫描电容的第一极板GC31靠近显示区域的一侧，第六扫描晶体管的栅电极GT62位于第一扫描电容的第一极板GC31远离显示区域的一侧。
在示例性实施方式中，如图16至图18所示，第一扫描晶体管的栅电极GT12的形状可以包括：第二连接段和两个第三分支段，第三分支段位于第二连接段远离显示区域的一侧，第二连接端与第三扫描晶体管的栅电极GT32连接。其中，两个分支段的长度不同。
在示例性实施方式中，如图16至图18所示，第二扫描晶体管的栅电极GT22的形状可以包括：沿第二方向D2延伸的栅极主体部和沿第一方向D1延伸的栅极连接部。
在示例性实施方式中，如图16至图18所示，第三扫描晶体管的栅电极GT32、第四扫描晶体管的栅电极GT42、第六扫描晶体管的栅电极GT62、第七扫描晶体管的栅电极GT72和第八扫描晶体管的栅电极GT82的形状可以为至少部分沿第二方向D2延伸的条状。
在示例性实施方式中，如图16至图18所示，第五扫描晶体管的栅电极GT52的形状可以包括多个沿第二方向D2延伸的第四分支段，第五扫描晶体管的栅电极GT52的形状可以呈梳妆，第二扫描电容的第一极板GC21作为梳背，多个第四分支段作为梳齿。
在示例性实施方式中，如图16至图18所示，第一扫描电容的第一极板GC11的形状可以为至少部分沿第二方向D2延伸的条状。
在示例性实施方式中，如图16至图18所示，第二扫描电容的第一极板ECG1的形状可以为沿第一方向D1延伸的条状。
在示例性实施方式中，如图16至图18所示，第一扫描晶体管的栅电极GT12的两个第三分支段跨设在第一扫描晶体管的有源层的沟道区上，第二扫描晶体管的栅电极GT22的栅极连接部跨设在第二扫描晶体管的有源层的沟道区上，第三扫描晶体管的栅电极GT32跨设在第三扫描晶体管的有源层的沟道区上，第四扫描晶体管的栅电极GT42跨设在第四扫描晶体管的有源层的沟道区上，第五扫描晶体管的栅电极GT52的两个第一分支段GT55跨设在第五扫描晶体管的有源层的沟道区上，第六扫描晶体管的栅电极GT62跨设在第一扫描晶体管的有源层的沟道区上，第七扫描晶体管的栅电极GT72跨设在第七扫描晶体管的有源层的沟道区上，第八扫描晶体管的栅电极GT82跨设在第八扫描晶体管的有源层的沟道区上，也就是说，至少一个扫描晶体管的栅电极的延伸方向与有源层的沟道区的延伸方向相互垂直。
在示例性实施方式中，如图16至图18所示，第一扫描晶体管的栅电极GT12的两个第三分支段跨设在第一扫描晶体管的有源层的沟道区上，第一扫描晶体管为双栅结构。
在示例性实施方式中，如图16和图17所示，第一信号连接线L1和第二信号连接线L2可以至少部分沿第二方向D2延伸。
在示例性实施方式中，如图36至图39所示，电容的第一极板C1的形状可以为矩形状，矩形状的角部可以设置倒角，电容的第一极板C1在基底上的正投影与第三晶体管的有源层在基底上的正投影至少部分交叠。在示例性实施方式中，电容的第一极板C1可以同时作为第三晶体管的栅电极M32。
在示例性实施方式中，如图36至图39所示，复位信号线Reset的形状可以为主体部分沿着第二方向D2延伸的线形状，本行子像素连接的的复位信号线Reset可以位于本子像素的第一极板C1靠近上一行子像素的一侧。复位信号线Reset与第一晶体管的有源层相重叠的区域作为双栅结构的第一晶体管的栅电极MT12。
在示例性实施方式中，如图36至图39所示，扫描信号线Gate的形状可以为主体部分沿着第二方向D2延伸的线形状，本行子像素连接的扫描信号线Gate可以位于本子像素连接的复位信号线Reset靠近第一极板C1的一侧，扫描信号线Gate与本子像素的第二晶体管的有源层相重叠的区域作为双栅结构的第二晶体管的栅电极MT22，扫描信号线Gate与第四晶体管有源层相重叠的区域作为第四晶体管的栅电极MT42。
在示例性实施方式中，如图36至图39所示，扫描信号线Gate包括：信号主体部21和信号连接部22。信号连接部22的一端与信号主体部21电连接。信号主体部21沿第二方向D2延伸，信号连接部22沿第一方向D1延伸。
在示例性实施方式中，如图36和图37所示，信号连接部22位于信号主体部21靠近电容的第一极板的一侧。
在示例性实施方式中，如图38和图39所示，信号连接部22位于信号主体部21远离电容的第一极板的一侧。
在示例性实施方式中，发光信号线EM的形状可以为主体部分沿着第二方向D2延伸的线形状，发光信号线EM可以位于本子像素的电容的第一极板C1靠近下一行子像素的一侧，发光信号线EM与本子像素的第五晶体管的有源层相重叠的区域作为第五晶体管的 栅电极MT52，发光信号线EM与本子像素的第六晶体管的有源层相重叠的区域作为第六晶体管的栅电极MT62。
在示例性实施方式中，复位信号线Reset、扫描信号线Gate和发光信号线EM可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一发光晶体管至第十发光晶体管的沟道区，第一释放晶体管至第二释放晶体管的沟道区以及第一扫描晶体管至第八扫描晶体管的沟道区，未被第一导电层遮挡区域的半导体层被导体化，即第一发光晶体管至第十晶体管的有源层的第一区和第二区、第一释放晶体管至第二释放晶体管的有源层的第一区和第二区以及第一扫描晶体管至第八扫描晶体管的有源层的第一区和第二区均被导体化。在示例性实施方式中，如图16和图17所示，第四发光晶体管的有源层的第一区(也是第五发光晶体管的有源层的第二区)被复用为第四发光晶体管的第一极(也是第五发光晶体管的第二极)，第六扫描晶体管的有源层的第二区(也是第七扫描晶体管的有源层的第一区)被复用为第六扫描晶体管的第二极(也是第七扫描晶体管的第一极)，第二晶体管的有源层的第二区(也是第三晶体管的有源层的第二区和第六晶体管的有源层的第一区)复用为第二晶体管的第二极(也是第三晶体管的第二极和第六晶体管的第一极)，第三晶体管的有源层的第一区(也是第四晶体管的有源层的第二区和第五晶体管的有源层的第二区)复用为第三晶体管的第一极(也是第四晶体管的第二极和第五晶体管的第二极)。
(3)形成第二绝缘层图案，包括：在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第二绝缘薄膜，采用图案化工艺对第二绝缘薄膜进行图案化，形成覆盖第一导电层的第二绝缘层，第二绝缘层上设置有过孔，如图19所示，图19为图6A提供的显示基板形成第二绝缘层图案后的示意图。
在示例性实施方式中，过孔至少包括：位于至少静电释放电路的过孔V0。过孔V0在基底上的正投影位于有源连接部在基底上的正投影范围之内，暴露出有源连接部的表面，过孔V0被配置为使后续形成的发光输出信号线通过该过孔与有源连接部连接。
在示例性实施方式中，图5A、图7B和图7C中同样形成第二绝缘层，但是第二绝缘层上并未设置过孔。
(4)形成第二导电层图案，包括：在形成有前述图案的基底上，沉积第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，形成位于第二绝缘层图案上的第二导电层图案，如图20至图23以及图40至图43所示，图20为图5A的第二导电层图案的示意图，图21为图5A形成第二导电层图案后的示意图，图22为图6A的第二导电层的示意图，图23为图6A形成第二导电层图案后的示意图，图40为图7B的第二导电层图案的示意图，图41为图7B形成第二导电层图案后的示意图，图42为图7C的第二导电层图案的示意图，图43为图7C形成第二导电层图案后的示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，如图20至图23以及图40至图43所示，第二导电层图案至少可以包括：位于发光移位寄存器的第一发光电容的第二极板EC12至第三发光电容的第二极板EC32、位于扫描移位寄存器的第一扫描电容的第一极板GC12和第二扫描电容的第二极板GC22、位于像素电路的电容的第二极板C2、扫描信号输出线GOL、发光信号输出线EOL、第三信号连接线L3、第一初始信号线INIT1和第二初始信号线INIT2。
在示例性实施方式中，如图42和图43所示，第二导电层图案还可以包括：屏蔽电极 SL。
在示例性实施方式中，如图20至图23所示，第一发光电容的第二极板EC12在基底上的正投影与第一发光电容的第一极板在基底上的正投影至少部分交叠。第二发光电容的第二极板EC22在基底上的正投影与第二发光电容的第一极板在基底上的正投影至少部分交叠。第三发光电容的第二极板EC32在基底上的正投影与第三发光电容的第一极板在基底上的正投影至少部分交叠。
在示例性实施方式中，如图20至图23所示，扫描输出信号线GOL与第二扫描电容的第二极板GC22为相互连接的一体结构，且位于第二扫描电容的第二极板GC22靠近显示区域的一侧。
在示例性实施方式中，如图20至图23所示，第一扫描电容的第二极板GC12在基底上的正投影与第一扫描电容的第一极板在基底上的正投影至少部分交叠。第二扫描电容的第二极板GC22在基底上的正投影与第二扫描电容的第一极板在基底上的正投影至少部分交叠。
在示例性实施方式中，如图20至图23所示，扫描输出信号线GOL至少部分沿第二方向D2延伸。
在示例性实施方式中，如图20至图23所示，第三信号连接线L3的形状为沿第二方向D2延伸的条状。
在示例性实施方式中，如图20至图23所示，发光输出信号线可以包括：输出连接部COL和至少一条输出线OL连接。多条输出线OL沿第一方向D1排布。至少一条输出线OL位于输出连接部COL靠近显示区域的一侧。
在示例性实施方式中，如图20至图23所示，输出连接部COL沿第一方向D1延伸，输出线OL至少部分沿第二方向D2延伸。
在示例性实施方式中，如图20和图21所示，图5A中的输出线OL包括：输出主体部OLA和输出连接部OLB，输出主体部OLA和输出连接部OLB为相互连接的一体结构。
在示例性实施方式中，如图20和图21所示，输出主体部OLA沿第二方向D2延伸，输出连接部OLB沿第一方向D1延伸。
在示例性实施方式中，如图22和图23所示，图6A中的输出线OL在基底上的正投影与有源连接部在基底上的正投影至少部分交叠，且通过过孔与有源连接部连接。
在示例性实施方式中，如图40至图43所示，位于同一行的相邻子像素的电容的第二极板C2电连接。
在示例性实施方式中，如图40和图41所示，电容的第二极板C2包括：电容主体部50、第一电容连接部51、第二电容连接部52和第三电容连接部53。在第二方向D2上，第一电容连接部51和第二电容连接部52分别位于电容主体部50的两侧，在第一方向D1上，第三电容连接部53位于电容主体部50靠近第一初始信号线的一侧。
在示例性实施方式中，如图40和图41所示，电容主体部50的轮廓可以为矩形状，矩形状的角部可以设置倒角，电容主体部50在基底上的正投影与电容的第一极板在基底上的正投影至少部分交叠。电容主体部50上设置有开口K，开口K的形状可以为任意形状，可以位于电容主体部50的中部，使电容主体部50形成环形结构。开口K暴露出覆盖第一极板的第三绝缘层，且第一极板在基底上的正投影包含开口K在基底上的正投影。在示例性实施方式中，开口K被配置为暴露出电容的第一极板，使后续形成的第一晶体管的第二极(也是第二晶体管的第一极)与电容的第一极板连接。
在示例性实施方式中，如图40和图41所示，本子像素的第一电容连接部与位于同一行的其中一个相邻子像素的第二电容连接部电连接，本子像素的第二电容连接部与位于同一行的另一个相邻子像素的第一电容连接部电连接。
在示例性实施方式中，如图40和图41所示，第三电容连接部在基底上的正投影与第二晶体管的电容在基底上的正投影至少部分交叠。
在示例性实施方式中，如图40和图41所示，第一初始信号线INIT1可以位于本子像素的电容的第二极板C2靠近上一行子像素的一侧。第一初始信号线INIT1在基底上的正投影位于复位信号线在基底上的正投影和扫描信号线在基底的正投影之间。
在示例性实施方式中，如图40和图41所示，第一初始信号线INIT1包括：初始信号主体部41、第一初始连接块42和第二初始连接块43。第一初始连接块42和第二初始连接块43分别与初始信号主体部41电连接。第一初始连接块42位于初始信号主体部41远离电容的第二极板的一侧，第二初始连接块43位于初始信号主体部41靠近电容的第二极板C2的一侧。初始信号主体部41的形状可以为沿着第二方向D2延伸的线形状。第一初始连接块42和第二初始连接块43可以相当于屏蔽电极，屏蔽电极被配置为有效屏蔽数据电压跳变对像素电路中关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
在示例性实施方式中，如图40和图41所示，第二初始信号线INIT2的形状可以为沿着第二方向D2延伸的线形状，本行子像素连接的第二初始信号线INIT2可以位于本子像素的电容的第二极板靠近下一行子像素的一侧。本行子像素所连接的第二初始信号线INIT2在基底的正投影位于本行子像素连接的发光信号线在基底的正投影之间和下一行子像素连接的复位信号线在基底的正投影之间。
在示例性实施方式中，如图42和图43所示，电容的第二极板C2包括：电容主体部50、第一电容连接部51和第二电容连接部52。在第二方向D2上，第一电容连接部51和第二电容连接部52分别位于电容主体部50的两侧。
在示例性实施方式中，如图42和图43所示，电容主体部50的轮廓可以为矩形状，矩形状的角部可以设置倒角，电容主体部50在基底上的正投影与电容的第一极板在基底上的正投影至少部分交叠。电容主体部50上设置有开口K，开口K的形状可以为任意形状，可以位于电容主体部50的中部，使电容主体部50形成环形结构。开口K暴露出覆盖第一极板的第三绝缘层，且第一极板在基底上的正投影包含开口K在基底上的正投影。在示例性实施方式中，开口K被配置为暴露出电容的第一极板，使后续形成的第一晶体管的第二极(也是第二晶体管的第一极)与电容的第一极板连接。
在示例性实施方式中，如图42和图43所示，本子像素的第一电容连接部与位于同一行的其中一个相邻子像素的第二电容连接部电连接，本子像素的第二电容连接部与位于同一行的另一个相邻子像素的第一电容连接部电连接。
在示例性实施方式中，如图42和图43所示，第一初始信号线INIT1的形状可以为沿着第二方向D2延伸的线形状，第一初始信号线INIT1可以位于本子像素的电容的第二极板C2靠近上一行子像素的一侧。第一初始信号线INIT1在基底上的正投影位于复位信号线在基底上的正投影远离扫描信号线在基底的正投影的一侧。
在示例性实施方式中，如图42和图43所示，屏蔽电极SL的形状可以为“n”字型。屏蔽电极SL位于第一初始信号线INT1和电容的第二极板C2之间。屏蔽电极SL在基底上的正投影与第一晶体管的有源层和第二晶体管的有源层在基底上的正投影至少部分交叠，且位于复位信号线在基底上的正投影和扫描信号线在基底上的正投影之间。屏蔽电极 被配置为有效屏蔽数据电压跳变对像素电路中关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
在示例性实施方式中，如图42和图43所示，第二初始信号线INIT2的形状可以为沿着第二方向D2延伸的线形状，本行子像素连接的第二初始信号线INIT2可以位于电容的第二极板C2靠近下一行子像素。本行子像素连接的第二初始信号线INIT2在基底的正投影位于本行子像素连接的扫描信号线在基底的正投影和下一行子像素连接的第一初始信号线在基底的正投影之间。
(5)形成第三绝缘层图案，包括：在形成有前述图案的基底上，沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行构图，形成覆盖前述结构的第三绝缘层图案，第三绝缘层开设有多个过孔图案，如图24、图25、图44和图45所示，图24为图5A形成第三绝缘层图案后的示意图，图25为图6A形成第三绝缘层图案后的示意图，图44为图7B形成第三绝缘层图案后的示意图，图45为图7C形成第三绝缘层图案后的示意图。
在示例性实施方式中，如图24所示，图5A中多个过孔图案至少可以包括：第一过孔V1至第五十七过孔V57。
在示例性实施方式中，如图24所示，第一过孔V1在基底上的正投影位于第一发光晶体管的有源层的第一区在基底上的正投影的范围之内，第一过孔V1内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一发光晶体管的有源层的第一区的表面，第一过孔V1被配置为使后续形成的第一发光晶体管的第一极通过该过孔与第一发光晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第二过孔V2在基底上的正投影位于第一发光晶体管的有源层的第二区在基底上的正投影的范围之内，第二过孔V2内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一发光晶体管的有源层的第二区的表面，第二过孔V2被配置为使后续形成的第一发光晶体管的第二极(也是第四发光晶体管的第二极)通过该过孔与第一发光晶体管的有源层的第二区连接。
在示例性实施方式中，如图24所示，第三过孔V3在基底上的正投影位于第二发光晶体管的有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第二发光晶体管的有源层的第一区的表面，第三过孔V3被配置为使后续形成的第二发光晶体管的第一极通过该过孔与第二发光晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第四过孔V4在基底上的正投影位于第二发光晶体管的有源层的第二区在基底上的正投影的范围之内，第四过孔V4内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第二发光晶体管的有源层的第二区的表面，第四过孔V4被配置为使后续形成的第二发光晶体管的第二极(也是第三发光晶体管的第二极)通过该过孔与第二发光晶体管的有源层的第二区连接。
在示例性实施方式中，如图24所示，第五过孔V5在基底上的正投影位于第三发光晶体管的有源层的第一区在基底上的正投影的范围之内，第五过孔V5内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第三发光晶体管的有源层的第一区的表面，第五过孔V5被配置为使后续形成的第三发光晶体管的第一极(也是第十发光晶体管的第一极)通过该过孔与第三发光晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第六过孔V6在基底上的正投影位于第三发光晶体管的有源层的第二区在基底上的正投影的范围之内，第六过孔V6内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第三发光晶体管的有源层的第二区的表面，第六过孔V6被 配置为使后续形成的第二发光晶体管的第二极(也是第三发光晶体管的第二极)通过该过孔与第三发光晶体管的有源层的第二区连接。
在示例性实施方式中，如图24所示，第七过孔V7在基底上的正投影位于第四发光晶体管的有源层的第二区在基底上的正投影的范围之内，第七过孔V7内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第四发光晶体管的有源层的第二区的表面，第七过孔V7被配置为使后续形成的第一发光晶体管的第二极(也是第四发光晶体管的第二极)通过该过孔与第四发光晶体管的有源层的第二区连接。
在示例性实施方式中，如图24所示，第八过孔V8在基底上的正投影位于第五发光晶体管的有源层的第一区在基底上的正投影的范围之内，第八过孔V8内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第五发光晶体管的有源层的第一区的表面，第八过孔V8被配置为使后续形成的第五发光晶体管的第一极通过该过孔与第五发光晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第九过孔V9在基底上的正投影位于第六发光晶体管的有源层的第一区在基底上的正投影的范围之内，第九过孔V9内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第六发光晶体管的有源层的第一区的表面，第九过孔V9被配置为使后续形成的第六发光晶体管的第一极通过该过孔与第六发光晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第十过孔V10在基底上的正投影位于第六发光晶体管的有源层的第二区在基底上的正投影的范围之内，第十过孔V10内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第六发光晶体管的有源层的第二区的表面，第十过孔V10被配置为使后续形成的第六发光晶体管的第二极(也是第七发光晶体管的第一极)通过该过孔与第六发光晶体管的有源层的第二区连接。
在示例性实施方式中，如图24所示，第十一过孔V11在基底上的正投影位于第七发光晶体管的有源层的第一区在基底上的正投影的范围之内，第十一过孔V11内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第七发光晶体管的有源层的第一区的表面，第十一过孔V11被配置为使后续形成的第六发光晶体管的第二极(也是第七发光晶体管的第一极)通过该过孔与第七发光晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第十二过孔V12在基底上的正投影位于第七发光晶体管的有源层的第二区在基底上的正投影的范围之内，第十二过孔V12内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第七发光晶体管的有源层的第二区的表面，第十二过孔V12被配置为使后续形成的第七发光晶体管的第二极(也是第八发光晶体管的第二极)通过该过孔与第七发光晶体管的有源层的第二区连接。
在示例性实施方式中，如图24所示，第十三过孔V13在基底上的正投影位于第八发光晶体管的有源层的第一区在基底上的正投影的范围之内，第十三过孔V13内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第八发光晶体管的有源层的第一区的表面，第十三过孔V13被配置为使后续形成的第八发光晶体管的第一极(也是第九发光晶体管的第一极)通过该过孔与第八发光晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第十四过孔V14在基底上的正投影位于第八发光晶体管的有源层的第二区在基底上的正投影的范围之内，第十四过孔V14内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第八发光晶体管的有源层的第二区的表面，第十四过孔V14被配置为使后续形成的第七发光晶体管的第二极(也是第八发光晶体管的第二极)通过该过孔与第八发光晶体管的有源层的第二区连接。
在示例性实施方式中，如图24所示，第十五过孔V15在基底上的正投影位于第九发光晶体管的有源层的第一区在基底上的正投影的范围之内，第十五过孔V15内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第九发光晶体管的有源层的第一区的表面，第十五过孔V15被配置为使后续形成的第八发光晶体管的第一极(也是第九发光晶体管的第一极)通过该过孔与第九发光晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第十六过孔V16在基底上的正投影位于第九发光晶体管的有源层的第二区在基底上的正投影的范围之内，第十六过孔V16内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第九发光晶体管的有源层的第二区的表面，第十六过孔V16被配置为使后续形成的第九发光晶体管的第二极通过该过孔与第九发光晶体管的有源层的第二区连接。
在示例性实施方式中，如图24所示，第十七过孔V17在基底上的正投影位于第十发光晶体管的有源层的第一区在基底上的正投影的范围之内，第十七过孔V17内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第十发光晶体管的有源层的第一区的表面，第十七过孔V17被配置为使后续形成的第十发光晶体管的第一极通过该过孔与第十发光晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第十八过孔V18在基底上的正投影位于第十发光晶体管的有源层的第二区在基底上的正投影的范围之内，第十八过孔V18内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第十发光晶体管的有源层的第二区的表面，第十八过孔V18被配置为使后续形成的第十发光晶体管的第二极通过该过孔与第十发光晶体管的有源层的第二区连接。
在示例性实施方式中，如图24所示，第十九过孔V19在基底上的正投影位于第一发光晶体管的栅电极(也是第三发光晶体管的栅电极)在基底上的正投影的范围之内，第十九过孔V19内的第二绝缘层被刻蚀掉，暴露出第一发光晶体管的栅电极(也是第三发光晶体管的栅电极)的表面，第十九过孔V19被配置为使后续形成的第二发光晶体管的第一极和第一发光时钟信号线和第二发光时钟信号线中的其中一条通过该过孔与第一发光晶体管的栅电极(也是第三发光晶体管的栅电极)连接。
在示例性实施方式中，如图24所示，第二十过孔V20在基底上的正投影位于第四发光晶体管的栅电极在基底上的正投影的范围之内，第二十过孔V20内的第二绝缘层被刻蚀掉，暴露出第四发光晶体管的栅电极的表面，第二十过孔V20被配置为使后续形成的第一发光时钟信号线和第二发光时钟信号线中的另一条通过该过孔与第四发光晶体管的栅电极连接。
在示例性实施方式中，如图24所示，第二十一过孔V21在基底上的正投影位于第五发光晶体管的栅电极(也是第六发光晶体管的栅电极和第一发光电容的第一极板)在基底上的正投影的范围之内，第二十一过孔V21内的第二绝缘层被刻蚀掉，暴露出第五发光晶体管的栅电极(也是第六发光晶体管的栅电极和第一发光电容的第一极板)的表面，第二十一过孔V21被配置为使后续形成的第二发光晶体管的第二极(也是第三发光晶体管的第二极)通过该过孔与第五发光晶体管的栅电极(也是第六发光晶体管的栅电极和第一发光电容的第一极板)连接。
在示例性实施方式中，如图24所示，第二十二过孔V22在基底上的正投影位于第七发光晶体管的栅电极在基底上的正投影的范围之内，第二十二过孔V22内的第二绝缘层被刻蚀掉，暴露出第七发光晶体管的栅电极的表面，第二十二过孔V22被配置为使后续形成的第一发光时钟信号线和第二发光时钟信号线中的另一条通过该过孔与第七发光晶 体管的栅电极连接。
在示例性实施方式中，如图24所示，第二十三过孔V23在基底上的正投影位于第九发光晶体管的栅电极(也是第二发光电容的第一极板)在基底上的正投影的范围之内，第二十三过孔V23内的第二绝缘层被刻蚀掉，暴露出第九发光晶体管的栅电极(也是第二发光电容的第一极板)的表面，第二十三过孔V23被配置为使后续形成的第七发光晶体管的第二极(也是第八发光晶体管的第二极)通过该过孔与第九发光晶体管的栅电极(也是第二发光电容的第一极板)连接。
在示例性实施方式中，如图24所示，第二十四过孔V24在基底上的正投影位于第一发光电容的第二极板在基底上的正投影的范围之内，暴露出第一发光电容的第二极板的表面，第二十四过孔V24被配置为使后续形成的第六发光晶体管的第二极(也是第七发光晶体管的第一极)通过该过孔与第一发光电容的第二极板连接。
在示例性实施方式中，如图24所示，第二十五过孔V25在基底上的正投影位于第二发光电容的第二极板在基底上的正投影的范围之内，暴露出第二发光电容的第二极板的表面，第二十五过孔V25被配置为使后续形成的第八发光晶体管的第一极(也是第九发光晶体管的第一极)通过该过孔与第二发光电容的第二极板连接。
在示例性实施方式中，如图24所示，第二十六过孔V26在基底上的正投影位于第三发光电容的第二极板在基底上的正投影的范围之内，暴露出第三发光电容的第二极板的表面，第二十六过孔V26被配置为使后续形成的第六发光晶体管的第一极通过该过孔与第三发光电容的第二极板连接。
在示例性实施方式中，如图24所示，第二十七过孔V27在基底上的正投影位于输出线的输出主体部在基底上的正投影的范围之内，暴露出输出线的输出主体部的表面，第二十七过孔V27被配置为使后续形成的第二连接线通过该过孔与输出线的输出主体部连接。
在示例性实施方式中，如图24所示，第二十八过孔V28在基底上的正投影位于输出线的输出连接部在基底上的正投影的范围之内，暴露出输出线的输出连接部的表面，第二十八过孔V28被配置为使后续形成的第一释放晶体管的第二极(也是第二释放晶体管的第二极)通过该过孔与输出线的输出连接部连接。
在示例性实施方式中，如图24所示，第二十九过孔V29在基底上的正投影位于输出连接线在基底上的正投影的范围之内，暴露出输出连接线的表面，第二十九过孔V29被配置为使后续形成的第九发光晶体管的第二极和第十发光晶体管的第二极通过该过孔与输出连接线连接。
在示例性实施方式中，如图24所示，第三十过孔V30在基底上的正投影位于第一释放晶体管的有源层的第一区在基底上的正投影的范围之内，第三十过孔V30内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一释放晶体管的有源层的第一区的表面，第三十过孔V30被配置为使后续形成的第一释放晶体管的第一极(也是第二发光电源线)通过该过孔与第一释放晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第三十一过孔V31在基底上的正投影位于第一释放晶体管的有源层的第二区(也是第二释放晶体管的有源层的第二区)在基底上的正投影的范围之内，第三十一过孔V31内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一释放晶体管的有源层的第二区(也是第二释放晶体管的有源层的第二区)的表面，第三十一过孔V31被配置为使后续形成的第一释放晶体管的第二极(也是第二释放晶体管的第二极)通过该过孔与第一释放晶体管的有源层的第二区(也是第二释放晶体管的有源层的第二区)连接。
在示例性实施方式中，如图24所示，第三十二过孔V32在基底上的正投影位于第二释放晶体管的有源层的第一区在基底上的正投影的范围之内，第三十二过孔V32内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第二释放晶体管的有源层的第一区的表面，第三十二过孔V32被配置为使后续形成的第二释放晶体管的第一极通过该过孔与第二释放晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第三十三过孔V33在基底上的正投影位于第一释放晶体管的栅电极在基底上的正投影的范围之内，第三十三过孔V33内的第二绝缘层被刻蚀掉，暴露出第一释放晶体管的栅电极的表面，第三十三过孔V33被配置为使后续形成的第一释放晶体管的第二极(也是第二释放晶体管的第二极)通过该过孔与第一释放晶体管的栅电极连接。
在示例性实施方式中，如图24所示，第三十四过孔V34在基底上的正投影位于第一释放晶体管的栅电极在基底上的正投影的范围之内，第三十四过孔V34内的第二绝缘层被刻蚀掉，暴露出第一释放晶体管的栅电极的表面，第三十四过孔V34被配置为使后续形成的第二释放晶体管的第一极(也是第一扫描电源线)通过该过孔与第二释放晶体管的栅电极连接。
在示例性实施方式中，如图24所示，第三十五过孔V35在基底上的正投影位于第一扫描晶体管的有源层的第一区在基底上的正投影的范围之内，第三十五过孔V35内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一扫描晶体管的有源层的第一区的表面，第三十五过孔V35被配置为使后续形成的第一扫描晶体管的第一极通过该过孔与第一扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第三十六过孔V36在基底上的正投影位于第一扫描晶体管的有源层的第二区(也是第七扫描晶体管的有源层的第二区)在基底上的正投影的范围之内，第三十六过孔V36内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一扫描晶体管的有源层的第二区(也是第七扫描晶体管的有源层的第二区)的表面，第三十六过孔V36被配置为使后续形成的第一扫描晶体管的第二极(也是第七扫描晶体管的第二极)通过该过孔与第一扫描晶体管的有源层的第二区(也是第七扫描晶体管的有源层的第二区)连接。
在示例性实施方式中，如图24所示，第三十七过孔V37在基底上的正投影位于第二扫描晶体管的有源层的第一区在基底上的正投影的范围之内，第三十七过孔V37内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第二扫描晶体管的有源层的第一区的表面，第三十七过孔V37被配置为使后续形成的第二扫描晶体管的第一极通过该过孔与第二扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第三十八过孔V38在基底上的正投影位于第二扫描晶体管的有源层的第二区(也是第三扫描晶体管的有源层的第二区)在基底上的正投影的范围之内，第三十八过孔V38内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第二扫描晶体管的有源层的第二区(也是第三扫描晶体管的有源层的第二区)的表面，第三十八过孔V38被配置为使后续形成的第二扫描晶体管的第二极(也是第三扫描晶体管的第二极)通过该过孔与第二扫描晶体管的有源层的第二区(也是第三扫描晶体管的有源层的第二区)连接。
在示例性实施方式中，如图24所示，第三十九过孔V39在基底上的正投影位于第三扫描晶体管的有源层的第一区在基底上的正投影的范围之内，第三十九过孔V39内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第三扫描晶体管的有源层的第一区的表面，第三 十九过孔V39被配置为使后续形成的第三扫描晶体管的第一极(也是第二扫描电源线)通过该过孔与第三扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第四十过孔V40在基底上的正投影位于第四扫描晶体管的有源层的第一区在基底上的正投影的范围之内，第四十过孔V40内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第四扫描晶体管的有源层的第一区的表面，第四十过孔V40被配置为使后续形成的第四扫描晶体管的第一极通过该过孔与第四扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第四十一过孔V41在基底上的正投影位于第四扫描晶体管的有源层的第二区(第五扫描晶体管的有源层的第二区)在基底上的正投影的范围之内，第四十一过孔V41内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第四扫描晶体管的有源层的第二区(第五扫描晶体管的有源层的第二区)的表面，第四十一过孔V41被配置为使后续形成的第四扫描晶体管的第二极(也是第五扫描晶体管的第二极)通过该过孔与第四扫描晶体管的有源层的第二区(第五扫描晶体管的有源层的第二区)连接。
在示例性实施方式中，如图24所示，第四十二过孔V42在基底上的正投影位于第五扫描晶体管的有源层的第一区在基底上的正投影的范围之内，第四十二过孔V42内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第五扫描晶体管的有源层的第一区的表面，第四十二过孔V42被配置为使后续形成的第五扫描晶体管的第一极通过该过孔与第五扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第四十三过孔V43在基底上的正投影位于第六扫描晶体管的有源层的第一区在基底上的正投影的范围之内，第四十三过孔V43内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第六扫描晶体管的有源层的第一区的表面，第四十三过孔V43被配置为使后续形成的第六扫描晶体管的第一极通过该过孔与第六扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第四十四过孔V44在基底上的正投影位于第八扫描晶体管的有源层的第一区在基底上的正投影的范围之内，第四十四过孔V44内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第八扫描晶体管的有源层的第一区的表面，第四十四过孔V44被配置为使后续形成的第八扫描晶体管的第一极通过该过孔与第八扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图24所示，第四十五过孔V45在基底上的正投影位于第八扫描晶体管的有源层的第二区在基底上的正投影的范围之内，第四十五过孔V45内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第八扫描晶体管的有源层的第二区的表面，第四十五过孔V45被配置为使后续形成的第八扫描晶体管的第二极通过该过孔与第八扫描晶体管的有源层的第二区连接。
在示例性实施方式中，如图24所示，第四十六过孔V46在基底上的正投影位于第一扫描晶体管的栅电极(也是第三扫描晶体管的栅电极)在基底上的正投影的范围之内，第四十六过孔V46内的第二绝缘层被刻蚀掉，暴露出第一扫描晶体管的栅电极(也是第三扫描晶体管的栅电极)的表面，第四十六过孔V46被配置为使后续形成的第二扫描晶体管的第一极和第一扫描时钟信号线和第二扫描时钟信号线中的其中一条通过该过孔与第一扫描晶体管的栅电极(也是第三扫描晶体管的栅电极)连接。
在示例性实施方式中，如图24所示，第四十七过孔V47在基底上的正投影位于第二扫描晶体管的栅电极在基底上的正投影的范围之内，第四十七过孔V47内的第二绝缘层被刻蚀掉，暴露出第四扫描晶体管的栅电极的表面，第四十七过孔V47被配置为使后续 形成的第一扫描晶体管的第二极(也是第七扫描晶体管的第二极)和第八扫描晶体管的第一极通过该过孔与第二扫描晶体管的栅电极连接。
在示例性实施方式中，如图24所示，第四十八过孔V48在基底上的正投影位于第四扫描晶体管的栅电极(也是第六扫描晶体管的栅电极和第一扫描电容的第一极板)在基底上的正投影的范围之内，第四十八过孔V48内的第二绝缘层被刻蚀掉，暴露出第四扫描晶体管的栅电极(也是第六扫描晶体管的栅电极和第一扫描电容的第一极板)的表面，第四十八过孔V48被配置为使后续形成的第二扫描晶体管的第二极(也是第三扫描晶体管的第二极)通过该过孔与第四扫描晶体管的栅电极(也是第六扫描晶体管的栅电极和第一扫描电容的第一极板)连接。
在示例性实施方式中，如图24所示，第四十九过孔V49在基底上的正投影位于第五扫描晶体管的栅电极(也是第二扫描电容的第一极板)在基底上的正投影的范围之内，第四十九过孔V49内的第二绝缘层被刻蚀掉，暴露出第五扫描晶体管的栅电极(也是第二扫描电容的第一极板)的表面，第四十九过孔V49被配置为使后续形成的第八扫描晶体管的第二极通过该过孔与第五扫描晶体管的栅电极(也是第二扫描电容的第一极板)连接。
在示例性实施方式中，如图24所示，第五十过孔V50在基底上的正投影位于第七扫描晶体管的栅电极在基底上的正投影的范围之内，第五十过孔V50内的第二绝缘层被刻蚀掉，暴露出第七扫描晶体管的栅电极的表面，第五十过孔V50被配置为使后续形成的第五发光晶体管的第一极以及第一扫描时钟信号线和第二扫描时钟信号线中另一条通过该过孔与第七扫描晶体管的栅电极连接。
在示例性实施方式中，如图24所示，第五十一过孔V51在基底上的正投影位于第八扫描晶体管的栅电极在基底上的正投影的范围之内，第五十一过孔V51内的第二绝缘层被刻蚀掉，暴露出第八扫描晶体管的栅电极的表面，第五十一过孔V51被配置为使后续形成的第二扫描电源线通过该过孔与第八扫描晶体管的栅电极连接。
在示例性实施方式中，如图24所示，第五十二过孔V52在基底上的正投影位于第一扫描电容的第二极板在基底上的正投影的范围之内，暴露出第一扫描电容的第二极板的表面，第五十二过孔V52被配置为使后续形成的第四扫描晶体管的第一极和第六扫描晶体管的第一极通过该过孔与第一扫描电容的第二极板连接。
在示例性实施方式中，如图24所示，第五十三过孔V53在基底上的正投影位于第二扫描电容的第二极板在基底上的正投影的范围之内，暴露出第二扫描电容的第二极板的表面，第五十三过孔V53被配置为使后续形成的第四扫描晶体管的第二极(也是第五扫描晶体管的第二极)通过该过孔与第二扫描电容的第二极板连接。
在示例性实施方式中，如图24所示，第五十四过孔V54在基底上的正投影位于第三信号连接线在基底上的正投影的范围之内，暴露出第三信号连接线的表面，第五十四过孔V54被配置为使后续形成的本级扫描移位寄存器的第一扫描晶体管的第二极和上一级扫描移位寄存器的第四扫描晶体管的第二极(也是第五扫描晶体管的第二极)通过该过孔与第三信号连接线连接。
在示例性实施方式中，如图24所示，第五十五过孔V55在基底上的正投影位于扫描输出信号线在基底上的正投影的范围之内，暴露出扫描输出信号线的表面，第五十五过孔V55被配置为使后续形成的第一连接线通过该过孔与扫描输出信号线连接。
在示例性实施方式中，如图24所示，第五十六过孔V56在基底上的正投影位于第一信号连接线在基底上的正投影的范围之内，第五十六过孔V56内的第二绝缘层被刻蚀掉，暴露出第一信号连接线的表面，第五十六过孔V56被配置为使后续形成的第一初始供电 线通过该过孔与第一信号连接线连接。
在示例性实施方式中，如图24所示，第五十七过孔V57在基底上的正投影位于第二信号连接线在基底上的正投影的范围之内，第五十七过孔V57内的第二绝缘层被刻蚀掉，暴露出第二信号连接线的表面，第五十七过孔V57被配置为使后续形成的第二初始供电线通过该过孔与第二信号连接线连接。
在示例性实施方式中，如图25所示，图6A提供的显示基板的多个过孔图案至少可以包括：第一过孔V1至第五十六过孔V56。
在示例性实施方式中，图6A中的第一过孔V1至第二十六过孔V26与图5A提供的显示基板中的第一过孔V1至第二十六过孔V26相同，在此不再赘述。
在示例性实施方式中，如图25所示，第二十七过孔V27在基底上的正投影位于输出线在基底上的正投影的范围之内，暴露出输出线的表面，第二十七过孔V27被配置为使后续形成的第二连接线通过该过孔与输出线连接。
在示例性实施方式中，如图25所示，第二十八过孔V28在基底上的正投影位于输出连接线在基底上的正投影的范围之内，暴露出输出连接线的表面，第二十八过孔V28被配置为使后续形成的第九发光晶体管的第二极和第十发光晶体管的第二极通过该过孔与输出连接线连接。
在示例性实施方式中，如图25所示，第二十九过孔V29在基底上的正投影位于第一释放晶体管的有源层的第一区在基底上的正投影的范围之内，第二十九过孔V29内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一释放晶体管的有源层的第一区的表面，第二十九过孔V29被配置为使后续形成的第一释放晶体管的第一极(也是第二发光电源线)通过该过孔与第一释放晶体管的有源层的第一区连接。
在示例性实施方式中，如图25所示，第三十过孔V30在基底上的正投影位于第一释放晶体管的有源层的第二区(也是第二释放晶体管的有源层的第二区)在基底上的正投影的范围之内，第三十过孔V30内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一释放晶体管的有源层的第二区(也是第二释放晶体管的有源层的第二区)的表面，第三十过孔V30被配置为使后续形成的第一释放晶体管的第二极(也是第二释放晶体管的有源层的第二区)通过该过孔与第一释放晶体管的有源层的第二区(也是第二释放晶体管的有源层的第二区)连接。
在示例性实施方式中，如图25所示，第三十一过孔V31在基底上的正投影位于第二释放晶体管的有源层的第一区在基底上的正投影的范围之内，第三十一过孔V312内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第二释放晶体管的有源层的第一区的表面，第三十一过孔V31被配置为使后续形成的第二释放晶体管的第一极通过该过孔与第二释放晶体管的有源层的第一区连接。
在示例性实施方式中，如图25所示，第三十二过孔V32在基底上的正投影位于第一释放晶体管的栅电极在基底上的正投影的范围之内，第三十二过孔V32内的第二绝缘层被刻蚀掉，暴露出第一释放晶体管的栅电极的表面，第三十二过孔V32被配置为使后续形成的第一释放晶体管的第二极(也是第二释放晶体管的有源层的第二区)通过该过孔与第一释放晶体管的栅电极连接。
在示例性实施方式中，如图25所示，第三十三过孔V33在基底上的正投影位于第一释放晶体管的栅电极在基底上的正投影的范围之内，第三十三过孔V33内的第二绝缘层被刻蚀掉，暴露出第一释放晶体管的栅电极的表面，第三十三过孔V33被配置为使后续形成的第二释放晶体管的第一极(也是第一扫描电源线)通过该过孔与第二释放晶体管的 栅电极连接。
在示例性实施方式中，如图25所示，第三十四过孔V34在基底上的正投影位于第一扫描晶体管的有源层的第一区在基底上的正投影的范围之内，第三十四过孔V34内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一扫描晶体管的有源层的第一区的表面，第三十五过孔V35被配置为使后续形成的第一扫描晶体管的第一极通过该过孔与第一扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图25所示，第三十五过孔V35在基底上的正投影位于第一扫描晶体管的有源层的第二区(也是第七扫描晶体管的有源层的第二区)在基底上的正投影的范围之内，第三十五过孔V35内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一扫描晶体管的有源层的第二区(也是第七扫描晶体管的有源层的第二区)的表面，第三十五过孔V35被配置为使后续形成的第一扫描晶体管的第二极(也是第七扫描晶体管的第二极)通过该过孔与第一扫描晶体管的有源层的第二区(也是第七扫描晶体管的有源层的第二区)连接。
在示例性实施方式中，如图25所示，第三十六过孔V36在基底上的正投影位于第二扫描晶体管的有源层的第一区在基底上的正投影的范围之内，第三十六过孔V36内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第二扫描晶体管的有源层的第一区的表面，第三十六过孔V36被配置为使后续形成的第二扫描晶体管的第一极通过该过孔与第二扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图25所示，第三十七过孔V37在基底上的正投影位于第二扫描晶体管的有源层的第二区(也是第三扫描晶体管的有源层的第二区)在基底上的正投影的范围之内，第三十七过孔V37内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第二扫描晶体管的有源层的第二区(也是第三扫描晶体管的有源层的第二区)的表面，第三十七过孔V37被配置为使后续形成的第二扫描晶体管的第二极(也是第三扫描晶体管的第二极)通过该过孔与第二扫描晶体管的有源层的第二区(也是第三扫描晶体管的有源层的第二区)连接。
在示例性实施方式中，如图25所示，第三十八过孔V38在基底上的正投影位于第三扫描晶体管的有源层的第一区在基底上的正投影的范围之内，第三十八过孔V38内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第三扫描晶体管的有源层的第一区的表面，第三十八过孔V38被配置为使后续形成的第三扫描晶体管的第一极(也是第二扫描电源线)通过该过孔与第三扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图25所示，第三十九过孔V39在基底上的正投影位于第四扫描晶体管的有源层的第一区在基底上的正投影的范围之内，第三十九过孔V39内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第四扫描晶体管的有源层的第一区的表面，第三十九过孔V39被配置为使后续形成的第四扫描晶体管的第一极通过该过孔与第四扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图25所示，第四十过孔V40在基底上的正投影位于第四扫描晶体管的有源层的第二区(第五扫描晶体管的有源层的第二区)在基底上的正投影的范围之内，第四十过孔V40内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第四扫描晶体管的有源层的第二区(第五扫描晶体管的有源层的第二区)的表面，第四十过孔V40被配置为使后续形成的第四扫描晶体管的第二极(也是第五扫描晶体管的第二极)通过该过孔与第四扫描晶体管的有源层的第二区(第五扫描晶体管的有源层的第二区)连接。
在示例性实施方式中，如图25所示，第四十一过孔V41在基底上的正投影位于第五 扫描晶体管的有源层的第一区在基底上的正投影的范围之内，第四十一过孔V41内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第五扫描晶体管的有源层的第一区的表面，第四十一过孔V41被配置为使后续形成的第五扫描晶体管的第一极通过该过孔与第五扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图25所示，第四十二过孔V42在基底上的正投影位于第六扫描晶体管的有源层的第一区在基底上的正投影的范围之内，第四十二过孔V42内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第六扫描晶体管的有源层的第一区的表面，第四十二过孔V423被配置为使后续形成的第六扫描晶体管的第一极通过该过孔与第六扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图25所示，第四十三过孔V43在基底上的正投影位于第八扫描晶体管的有源层的第一区在基底上的正投影的范围之内，第四十三过孔V43内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第八扫描晶体管的有源层的第一区的表面，第四十三过孔V43被配置为使后续形成的第八扫描晶体管的第一极通过该过孔与第八扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图25所示，第四十四过孔V44在基底上的正投影位于第八扫描晶体管的有源层的第二区在基底上的正投影的范围之内，第四十四过孔V44内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第八扫描晶体管的有源层的第二区的表面，第四十四过孔V44被配置为使后续形成的第八扫描晶体管的第二极通过该过孔与第八扫描晶体管的有源层的第二区连接。
在示例性实施方式中，如图25所示，第四十五过孔V45在基底上的正投影位于第一扫描晶体管的栅电极(也是第三扫描晶体管的栅电极)在基底上的正投影的范围之内，第四十五过孔V45内的第二绝缘层被刻蚀掉，暴露出第一扫描晶体管的栅电极(也是第三扫描晶体管的栅电极)的表面，第四十五过孔V45被配置为使后续形成的第二扫描晶体管的第一极和第一扫描时钟信号线和第二扫描时钟信号线中的其中一条通过该过孔与第一扫描晶体管的栅电极(也是第三扫描晶体管的栅电极)连接。
在示例性实施方式中，如图25所示，第四十六过孔V46在基底上的正投影位于第二扫描晶体管的栅电极在基底上的正投影的范围之内，第四十六过孔V46内的第二绝缘层被刻蚀掉，暴露出第四扫描晶体管的栅电极的表面，第四十六过孔V46被配置为使后续形成的第一扫描晶体管的第二极(也是第七扫描晶体管的第二极)和第八扫描晶体管的第一极通过该过孔与第二扫描晶体管的栅电极连接。
在示例性实施方式中，如图25所示，第四十七过孔V47在基底上的正投影位于第四扫描晶体管的栅电极(也是第六扫描晶体管的栅电极和第一扫描电容的第一极板)在基底上的正投影的范围之内，第四十七过孔V47内的第二绝缘层被刻蚀掉，暴露出第四扫描晶体管的栅电极(也是第六扫描晶体管的栅电极和第一扫描电容的第一极板)的表面，第四十七过孔V47被配置为使后续形成的第二扫描晶体管的第二极(也是第三扫描晶体管的第二极)通过该过孔与第四扫描晶体管的栅电极(也是第六扫描晶体管的栅电极和第一扫描电容的第一极板)连接。
在示例性实施方式中，如图25所示，第四十八过孔V48在基底上的正投影位于第五扫描晶体管的栅电极(也是第二扫描电容的第一极板)在基底上的正投影的范围之内，第四十八过孔V48内的第二绝缘层被刻蚀掉，暴露出第五扫描晶体管的栅电极(也是第二扫描电容的第一极板)的表面，第四十八过孔V48被配置为使后续形成的第八扫描晶体管的第二极通过该过孔与第五扫描晶体管的栅电极(也是第二扫描电容的第一极板)连接。
在示例性实施方式中，如图25所示，第四十九过孔V49在基底上的正投影位于第七扫描晶体管的栅电极在基底上的正投影的范围之内，第四十九过孔V49内的第二绝缘层被刻蚀掉，暴露出第七扫描晶体管的栅电极的表面，第四十九过孔V49被配置为使后续形成的第五发光晶体管的第一极以及第一扫描时钟信号线和第二扫描时钟信号线中另一条通过该过孔与第七扫描晶体管的栅电极连接。
在示例性实施方式中，如图25所示，第五十过孔V50在基底上的正投影位于第八扫描晶体管的栅电极在基底上的正投影的范围之内，第五十过孔V50内的第二绝缘层被刻蚀掉，暴露出第八扫描晶体管的栅电极的表面，第五十过孔V50被配置为使后续形成的第二扫描电源线通过该过孔与第八扫描晶体管的栅电极连接。
在示例性实施方式中，如图25所示，第五十一过孔V51在基底上的正投影位于第一扫描电容的第二极板在基底上的正投影的范围之内，暴露出第一扫描电容的第二极板的表面，第五十一过孔V51被配置为使后续形成的第四扫描晶体管的第一极和第六扫描晶体管的第一极通过该过孔与第一扫描电容的第二极板连接。
在示例性实施方式中，如图25所示，第五十二过孔V52在基底上的正投影位于第二扫描电容的第二极板在基底上的正投影的范围之内，暴露出第二扫描电容的第二极板的表面，第五十二过孔V52被配置为使后续形成的第四扫描晶体管的第二极(也是第五扫描晶体管的第二极)通过该过孔与第二扫描电容的第二极板连接。
在示例性实施方式中，如图25所示，第五十三过孔V53在基底上的正投影位于第三信号连接线在基底上的正投影的范围之内，暴露出第三信号连接线的表面，第五十三过孔V53被配置为使后续形成的本级扫描移位寄存器的第一扫描晶体管的第二极和上一级扫描移位寄存器的第四扫描晶体管的第二极(也是第五扫描晶体管的第二极)通过该过孔与第三信号连接线连接。
在示例性实施方式中，如图25所示，第五十四过孔V54在基底上的正投影位于扫描输出信号线在基底上的正投影的范围之内，暴露出扫描输出信号线的表面，第五十四过孔V54被配置为使后续形成的第一连接线通过该过孔与扫描输出信号线连接。
在示例性实施方式中，如图25所示，第五十五过孔V55在基底上的正投影位于第一信号连接线在基底上的正投影的范围之内，第五十五过孔V55内的第二绝缘层被刻蚀掉，暴露出第一信号连接线的表面，第五十五过孔V55被配置为使后续形成的第一初始供电线通过该过孔与第一信号连接线连接。
在示例性实施方式中，如图25所示，第五十六过孔V56在基底上的正投影位于第二信号连接线在基底上的正投影的范围之内，第五十六过孔V56内的第二绝缘层被刻蚀掉，暴露出第二信号连接线的表面，第五十六过孔V56被配置为使后续形成的第二初始供电线通过该过孔与第二信号连接线连接。
在示例性实施方式中，如图44和图45所示，图7B和图7C中多个过孔图案至少可以包括：第五十八过孔V58至第六十七过孔V67。
在示例性实施方式中，如图44和图45所示，第五十八过孔V58在基底上的正投影位于第一晶体管的有源层的第一区在基底上的正投影的范围之内，第五十八过孔V58内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一晶体管的有源层的第一区的表面，第五十八过孔V58被配置为使后续形成的第一晶体管的第一极通过该过孔与第一晶体管的有源层的第一区连接。
在示例性实施方式中，如图44和图45所示，第五十九过孔V59在基底上的正投影位于第一晶体管的有源层的第二区(也是第二晶体管的有源层的第一区)在基底上的正投 影的范围之内，第五十九过孔V59内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一晶体管的有源层的第二区(也是第二晶体管的有源层的第一区)的表面，第五十九过孔V59被配置为使后续形成的第一晶体管的第二极(也是第二晶体管的第一极)通过该过孔与第一晶体管的有源层的第二区(也是第二晶体管的有源层的第一区)连接。
在示例性实施方式中，如图44和图45所示，第六十过孔V60在基底上的正投影位于第四晶体管的有源层的第一区在基底上的正投影的范围之内，第六十过孔V60内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第一区的表面，第六十过孔V60被配置为使后续形成的第四晶体管的第一极通过该过孔与第四晶体管的有源层的第一区连接。
在示例性实施方式中，如图44和图45所示，第六十一过孔V61在基底上的正投影位于第五晶体管的有源层的第一区在基底上的正投影的范围之内，第六十一过孔V61内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第五晶体管的有源层的第二区的表面。图44中的第六十一过孔V61被配置为使后续形成的第五晶体管的第一极通过该过孔与第五晶体管的有源层的第一区连接。图45中的第六十一过孔V61被配置为使后续形成的第一子电源线通过该过孔与第五晶体管的有源层的第一区连接。
在示例性实施方式中，如图44和图45所示，第六十二过孔V62在基底上的正投影位于第六晶体管的有源层的第二区(第七晶体管的有源层的第二区)在基底上的正投影的范围之内，第六十二过孔V62内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第六晶体管的有源层的第二区(第七晶体管的有源层的第二区)的表面，第六十二过孔V62被配置为使后续形成的第六晶体管的第二极(也是第七晶体管的第二极)通过该过孔与第六晶体管的有源层的第二区(第七晶体管的有源层的第二区)连接。
在示例性实施方式中，如图44和图45所示，第六十三过孔V63在基底上的正投影位于第七晶体管的有源层的第一区在基底上的正投影的范围之内，第六十三过孔V63内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第七晶体管的有源层的第一区的表面。图44中的第六十三过孔V63被配置为使后续形成的第七晶体管的第一极通过该过孔与第七晶体管的有源层的第一区连接。图45中的第六十三过孔V63被配置为使后续形成的第七晶体管的第一极或者第四信号连接线通过该过孔与第七晶体管的有源层的第一区连接。
在示例性实施方式中，如图44所示，第六十四过孔V64在基底上的正投影位于第三晶体管的栅电极(也是电容的第一极板)在基底上的正投影的范围之内，第六十四过孔V64内的第二绝缘层被刻蚀掉，暴露出第三晶体管的栅电极(也是电容的第一极板)的表面，第六十四过孔V64被配置为使后续形成的第一晶体管的第二极(也是第二晶体管的第一极)通过该过孔与第三晶体管的栅电极(也是电容的第一极板)连接。
在示例性实施方式中，如图44所示，第六十五过孔V65在基底上的正投影位于第一初始信号线在基底上的正投影的范围之内，暴露出第一初始信号线，第六十五过孔V65被配置为使后续形成的第一晶体管的第一极通过该过孔与第一初始信号线连接。
在示例性实施方式中，如图44和图45所示，第六十六过孔V66在基底上的正投影位于电容的第二极板在基底上的正投影的范围之内，暴露出电容的第二极板的表面。图44中的第六十六过孔V66被配置为使后续形成的第五晶体管的第一极通过该过孔与电容的第二极板连接。图45中的第六十六过孔V66被配置为使后续形成的第一子电源线通过该过孔与电容的第二极板连接。
在示例性实施方式中，如图44所示，第六十七过孔V67在基底上的正投影位于第二初始信号线在基底上的正投影的范围之内，暴露出第二初始信号线的表面，第六十七过孔 V67被配置为使后续形成的第七晶体管的第一极通过该过孔与第二初始信号线连接。
(6)形成第三导电层图案，包括：在形成前述图案的基底上，沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行构图，形成第三导电层图案，如图26至图28以及图46至图49所示，图26为图5A和图6A的第三导电层图案的示意图，图27为图5A形成第三导电层图案后的示意图，图28为图6A形成第三导电层图案后的示意图，图46为图7B的第三导电层图案的示意图，图47为图7B形成第三导电层图案后的示意图，图48为7C的第三导电层图案的示意图，图49为图7C形成第三导电层图案后的示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，如图26至图28以及图46至图49所示，第三导电层图案至少可以包括：发光初始信号线ESTV、第一发光时钟信号线ECK1、第二发光时钟信号线ECK2、第一发光电源线EVGH、第二发光电源线EVGL，扫描初始信号线GSTV、第一扫描时钟信号线的第一子时钟信号线GCK1A、第二扫描时钟信号线的第三子时钟信号线GCK2A、第一扫描电源线GVGH、第二扫描电源线GVGL、第一条初始供电线的第一子初始供电线INITL1A、第二条初始供电线的第一子初始供电线INITL2A、第一连接线CL1至第四连接线CL4、多个发光晶体管的第一极和第二极、多个释放晶体管的第一极和第二极以及多个扫描晶体管的第一极和第二极、第一晶体管的第一极MT13和第二极MT14、第二晶体管的第一极MT23、第四晶体管的第一极MT43、第五晶体管的第一极MT53、第六晶体管的第二极MT64以及第七晶体管的第一极MT73和第二极MT74。
在示例性实施方式中，如图46和图47所示，第三导电层图案至少还包括：数据连接线DL。
在示例性实施方式中，如图48和图49所示，第三导电层图案至少还包括：第一子电源下VDDA以及电极连接线CL。
在示例性实施方式中，如图26所示，第一发光时钟信号线ECK1可以位于发光初始信号线ESTV靠近显示区域的一侧，第二发光时钟信号线ECK2可以位于第一发光时钟信号线ECK1靠近显示区域的一侧，第一发光电源线EVGH可以位于第二发光时钟信号线ECK2靠近显示区域的一侧，第二发光电源线EVGL位于第一发光电源线EVGH靠近显示区域的一侧，第一扫描电源线GVGH位于第二发光电源线EVGL靠近显示区域的一侧，第一扫描时钟信号线的第一子时钟信号线GCK1A位于第一扫描电源线GVGH靠近显示区域的一侧，第二扫描时钟信号线的第三子时钟信号线GCK2A位于第一扫描时钟信号线GCK1靠近显示区域的一侧，扫描初始信号线GSTV位于第二扫描时钟信号线GCK2靠近显示区域的一侧，第二扫描电源线GVGL位于扫描初始信号线GSTV靠近显示区域的一侧。
在示例性实施方式中，发光初始信号线ESTV、第一发光时钟信号线ECK1、第二发光时钟信号线ECK2、第一发光电源线EVGH、第二发光电源线EVGL，扫描初始信号线GSTV、第一扫描时钟信号线的第一子时钟信号线GCK1A、第二扫描时钟信号线的第三子时钟信号线GCK2A、第一扫描电源线GVGH、第二扫描电源线GVGL、第一条初始供电线的第一子初始供电线INITL1A和第二条初始供电线的第一子初始供电线INITL2A中的任一条至少部分沿第一方向D1延伸，且为线形状。
在示例性实施方式中，如图26所示，第一发光晶体管的第一极ET13和第二极ET14至第十发光晶体管的第一极ET103和第二极ET104可以位于第一发光电源线EVGH和第二发光电源线EVGL之间。第一释放晶体管的第一极RT11和第二极RT14至第二释放晶体管的第一极RT21和第二极RT24位于第二发光电源线EVGL和第一扫描电源线GVGH 之间。第一扫描晶体管的第一极GT13和第二极GT14至第三扫描晶体管的第一极GT33和第二极以及第六扫描晶体管的第一极GT63和第七扫描晶体管的第二极GT74可以位于扫描初始信号线GSTV和第二扫描电源线GVGL之间，第四扫描晶体管的第一极GT43和第二极GT44至第五扫描晶体管的第一极GT53和第二极GT54以及第八扫描晶体管的第一极GT83和第二极GT84可以位于第二扫描电源线GVGL和第一条初始供电线INITL1之间。
在示例性实施方式中，第二扫描电容的第二极板在基底上的正投影与第二扫描电源线、第一扫描时钟信号线、第二扫描时钟信号线、扫描初始信号线和第一扫描电源线在基底上的正投影至少部分交叠。
在示例性实施方式中，如图26所示，第一条初始供电线INITL1和第二条初始供电线INITL2位于第二扫描电源线GVGL靠近显示区域的一侧，且第一条初始供电线INITL1位于第二条初始供电线INITL2靠近显示区域的一侧。
在示例性实施方式中，如图26至图28所示，第一发光晶体管的第一极ET13的形状可以为沿第一方向D1延伸的条状。第一发光晶体管的第一极ET13通过第一过孔第一发光晶体管的有源层的第一区。
在示例性实施方式中，如图26至图28所示，第一发光晶体管的第二极ET14与第四发光晶体管的第二极ET44为相互连接的一体结构，且可以形状为沿第一方向D1延伸的条状。第一发光晶体管的第二极ET14(也是第四发光晶体管的第二极ET44)通过第二过孔与第一发光晶体管的有源层的第二区连接，且通过第七过孔与第四发光晶体管的有源层的第二区连接。
在示例性实施方式中，如图26至图28所示，第二发光晶体管的第一极ET23的形状可以为沿第一方向D1延伸的条状，第二发光晶体管的第一极ET23通过第三过孔与第二发光晶体管的有源层的第一区连接，且通过第十九过孔与第一发光晶体管的栅电极(也是第三发光晶体管的栅电极)连接。
在示例性实施方式中，如图26至图28所示，第二发光晶体管的第二极ET24与第三发光晶体管的第二极ET34为相互连接的一体结构，且至少部分沿第一方向D1延伸，可以为折线型。第二发光晶体管的第二极ET24(也是第三发光晶体管的第二极ET34)通过第四过孔与第二发光晶体管的有源层的第二区连接，通过第六过孔与第三发光晶体管的有源层的第二区连接，且通过第二十一过孔与第五发光晶体管的栅电极(也是第六发光晶体管的栅电极和第一发光电容的第一极板)连接。
在示例性实施方式中，如图26至图28所示，第三发光晶体管的第一极ET33与第十发光晶体管的第一极ET103和第二发光电源线EVGL为相互连接的一体结构，且第三发光晶体管的第一极ET33的形状可以为沿第二方向D2延伸的条状，第十发光晶体管的第一极ET103的形状可以为开口朝向第二发光电源线EVGL的“n”字型。第三发光晶体管的第一极ET33(也是第十发光晶体管的第一极ET103)通过第五过孔与第三发光晶体管的有源层的第一区连接，且通过第十七过孔与第十发光晶体管的有源层的第一区连接。
在示例性实施方式中，如图26至图28所示，第五发光晶体管的第一极ET53与第一发光电源线EVGH为相互连接的一体结构。第五发光晶体管的第一极ET53的形状可以为块状。第五发光晶体管ET53通过第八过孔与第五发光晶体管的有源层的第一区连接。
在示例性实施方式中，如图26至图28所示，第六发光晶体管的第一极ET63的形状可以为块状。第六发光晶体管的第一极ET63通过第九过孔与第六发光晶体管的有源层的第一区连接，且通过第二十六过孔与第三发光电容的第二极板连接。
在示例性实施方式中，如图26至图28所示，第六发光晶体管的第二极ET64和第七发光晶体管的第一极ET73为相互连接的一体结构。第六发光晶体管的第二极ET64(也是第七发光晶体管的第一极ET73)至少部分沿第一方向D1延伸。第六发光晶体管的第二极ET64(也是第七发光晶体管的第一极ET73)通过第十过孔与第六发光晶体管的有源层的第二区连接，通过第十一过孔与第七发光晶体管的有源层的第一区连接，且通过第二十四过孔与第一发光电容的第二极板连接。
在示例性实施方式中，如图26至图28所示，第七发光晶体管的第二极ET74和第八发光晶体管的第二极ET84为相互连接的一体结构。第七发光晶体管的第二极ET74(也是第八发光晶体管的第二极ET84)的形状可以为水平翻转的“7”字型。第七发光晶体管的第二极ET74(也是第八发光晶体管的第二极ET84)通过第十二过孔与第七发光晶体管的有源层的第二区连接，通过第十四过孔与第八发光晶体管的有源层的第二区连接，且通过第二十三过孔与第九发光晶体管的栅电极(也是第二发光电容的第一极板)连接。
在示例性实施方式中，如图26至图28所示，第八发光晶体管的第一极ET83、第九发光晶体管的第一极ET93与第一发光电源线EVGH为相互连接的一体结构。第八发光晶体管的第一极ET83的形状可以为块状，第九发光晶体管的第一极ET93的形状可以为梳状，第八发光晶体管的第一极ET83(也是第九发光晶体管的第一极ET93)通过第十三过孔与第八发光晶体管的有源层的第一区连接，通过第十五过孔与第九发光晶体管的有源层的第一区连接，且通过第二十五过孔与第二发光电容的第二极板连接。
在示例性实施方式中，如图26至图28所示，第九发光晶体管的第二极ET94的形状可以为梳状，第九发光晶体管的第二极ET94的梳齿可以位于第九发光晶体管的第一极ET93的梳齿交错设置。第九发光晶体管的第二极ET94通过第十六过孔与第九发光晶体管的有源层的第二区连接。如图27所示，图5A中第九发光晶体管的第二极ET94通过第二十九过孔与输出连接线连接。如图28所示，图6A中第九发光晶体管的第二极ET94通过第二十八过孔与输出连接线连接。
在示例性实施方式中，如图26至图28所示，第十发光晶体管的第二极ET104的形状可以为开口背离第二发光电源线EVGL的“n”字型。第十发光晶体管的第二极ET104通过第十八过孔与第十发光晶体管的有源层的第二区连接。如图27所示，图5A中第十发光晶体管的第二极ET104通过第二十九过孔与输出连接线连接。如图28所示，图6A中第十发光晶体管的第二极ET104通过第二十八过孔与输出连接线连接。
在示例性实施方式中，如图26至图28所示，第一发光时钟信号线ECK1和第二发光时钟信号线ECK2中的其中一条通过第十九过孔与第一发光晶体管的栅电极(也是第三发光晶体管的栅电极)连接。
在示例性实施方式中，如图26至图28所示，第一发光时钟信号线ECK1和第二发光时钟信号线ECK2中的另一条通过第二十过孔与第四发光晶体管的栅电极连接，且通过第二十二过孔与第七发光晶体管的栅电极连接。
在示例性实施方式中，如图26至图28所示，第二连接线CL2可以为块状。如图27所示，图5A中的第二连接线通过第二十七过孔与输出线的输出主体部连接。
在示例性实施方式中，如图26至图28所示，第二发光电源线EVGL与第一释放晶体管的有源层的第一区交叠的区域可以复用为第一释放晶体管的第一极。如图27所示，图5A中第一释放晶体管的第一极通过第三十过孔与第一释放晶体管的有源层的第一区连接，图6A中第一释放晶体管的第一极通过第二十九过孔与第一释放晶体管的有源层的第一区连接。
在示例性实施方式中，如图26至图28所示，第一释放晶体管的第二极ET14和第二释放晶体管的第二极ET24为相互连接的一体结构，且形状可以为水平翻转的“L”字型。如图27所示，图5A中第一释放晶体管的第二极ET14(也是第二释放晶体管的第二极)在基底上的正投影与输出连接部在基底上的正投影至少部分交叠。图5A中的第一释放晶体管的第二极ET14(也是第二释放晶体管的第二极)在基底上的正投影与输出线在基底上的正投影不交叠。
在示例性实施方式中，如图27所示，图5A中第一释放晶体管的第二极ET14(也是第二释放晶体管的第二极)通过第二十八过孔与输出线的输出连接部连接，通过第三十一过孔与第一释放晶体管的有源层的第二区(也是第二释放晶体管的有源层的第二区)连接，通过第三十三过孔与第一释放晶体管的栅电极连接。如图28所示，图6A中第一释放晶体管的第二极ET14(也是第二释放晶体管的第二极)通过第三十过孔与第一释放晶体管的有源层的第二区(也是第二释放晶体管的有源层的第二区)连接，通过第三十二过孔与第一释放晶体管的栅电极连接。
在示例性实施方式中，如图26至图28所示，第二释放晶体管的第二极ET21与第一扫描电源线GVGH为相互连接的一体结构，且形状可以为形状可以为水平翻转的“L”字型。如图27所示，图5A中第二释放晶体管的第二极ET21通过第三十二过孔与第二释放晶体管的有源层的第一区连接，且通过第三十四过孔与第二释放晶体管的栅电极连接。如图28所示，图6A中第二释放晶体管的第二极ET21通过第三十一过孔与第二释放晶体管的有源层的第一区连接，且通过第三十三过孔与第二释放晶体管的栅电极连接。
在示例性实施方式中，如图26至图28所示，第一扫描晶体管的第一极GT13的形状可以为沿第二方向D2延伸的条状。如图27所示，图5A中第一扫描晶体管的第一极GT13通过第三十五过孔与第一扫描晶体管的有源层的第一区连接，且通过第五十四过孔与第三信号连接线连接。如图28所示，图6A中第一扫描晶体管的第一极GT13通过第三十四过孔与第一扫描晶体管的有源层的第一区连接，且通过第五十三过孔与第三信号连接线连接。
在示例性实施方式中，如图26至图28所示，第一扫描晶体管的第二极GT14和第七扫描晶体管的第二极GT74为相互连接的一体结构，且形状可以为沿第二方向D2延伸的条状。如图27所示，图5A中第一扫描晶体管的第二极GT14(也是第七扫描晶体管的第二极GT74)通过第三十六过孔与第一扫描晶体管的有源层的第二区(也是第七扫描晶体管的有源层的第二区)连接，通过第四十七过孔与第二扫描晶体管的栅电极连接。如图28所示，图6A中第一扫描晶体管的第二极GT14(也是第七扫描晶体管的第二极GT74)通过第三十五过孔与第一扫描晶体管的有源层的第二区(也是第七扫描晶体管的有源层的第二区)连接，通过第四十六过孔与第二扫描晶体管的栅电极连接。
在示例性实施方式中，如图26至图28所示，第二扫描晶体管的第一极GT23的形状可以为沿第一方向D1延伸的条状。如图27所示，图5A提供的显示基板中第二扫描晶体管的第一极GT23通过第三十七过孔与第二扫描晶体管的有源层的第一区连接，且通过第四十六过孔与第一扫描晶体管的栅电极(也是第三扫描晶体管的栅电极)连接。如图28所示，图6A中第二扫描晶体管的第一极GT23通过第三十六过孔与第二扫描晶体管的有源层的第一区连接，且通过第四十五过孔与第一扫描晶体管的栅电极(也是第三扫描晶体管的栅电极)连接。
在示例性实施方式中，如图26至图28所示，第二扫描晶体管的第二极GT24和第三扫描晶体管的第二极GT34为相互连接的一体结构，且形状可以为沿第二方向D2延伸的条状。如图27所示，图5A提供的显示基板中第二扫描晶体管的第二极GT24(也是第三 扫描晶体管的第二极GT34)通过第三十八过孔与第二扫描晶体管的有源层的第二区(也是第三扫描晶体管的有源层的第二区)连接，通过第四十八过孔与第四扫描晶体管的栅电极(也是第六扫描晶体管的栅电极和第一扫描电容的第一极板)连接。如图28所示，图6A中第二扫描晶体管的第二极GT24(也是第三扫描晶体管的第二极GT34)通过第三十七过孔与第二扫描晶体管的有源层的第二区(也是第三扫描晶体管的有源层的第二区)连接，通过第四十七过孔与第四扫描晶体管的栅电极(也是第六扫描晶体管的栅电极和第一扫描电容的第一极板)连接。
在示例性实施方式中，如图26至图28所示，第二扫描电源线GVGL与第三扫描晶体管的有源层的第一区交叠区域复用为第三扫描晶体管的第一极GT33。如图27所示，图5A中第三扫描晶体管的第一极GT33通过第三十九过孔与第三扫描晶体管的有源层的第一区连接。
在示例性实施方式中，如图26至图28所示，第四扫描晶体管的第一极GT43的形状可以为沿第二方向D2延伸的条状。如图27所示，图5A提供的显示基板中第四扫描晶体管的第一极GT43通过第四十过孔与第四扫描晶体管的有源层的第一区连接，且通过第五十二过孔与第一扫描电容的第二极板连接。如图28所示，图6A中第二扫描晶体管的第一极GT23通过第三十九过孔与第四扫描晶体管的有源层的第一区连接，且通过第五十一过孔与第一扫描电容的第二极板连接。
在示例性实施方式中，如图26至图28所示，第四扫描晶体管的第二极GT44和第五扫描晶体管的第二极GT54为相互连接的一体结构，且形状可以为开口朝向第二扫描电源线GVGH的“m”字型。如图27所示，图5A中第四扫描晶体管的第二极GT44(也是第五扫描晶体管的第二极GT54)通过第四十一过孔与第四扫描晶体管的有源层的第二区(第五扫描晶体管的有源层的第二区)连接，通过第五十三过孔与第二扫描电容的第二极板连接。如图28所示，图6A中第四扫描晶体管的第二极GT44(也是第五扫描晶体管的第二极GT54)通过第四十过孔与第四扫描晶体管的有源层的第二区(第五扫描晶体管的有源层的第二区)连接，通过第五十二过孔与第二扫描电容的第二极板连接。
在示例性实施方式中，如图26至图28所示，第五扫描晶体管的第一极GT53的形状可以呈“F”字型。如图27所示，图5A中第五扫描晶体管的第一极GT53通过第四十二过孔与第五扫描晶体管的有源层的第一区连接，且通过第五十过孔与第七扫描晶体管的栅电极连接。如图28所示，图6A中第五扫描晶体管的第一极GT53通过第四十一过孔与第五扫描晶体管的有源层的第一区连接，且通过第四十九过孔与第七扫描晶体管的栅电极连接。
在示例性实施方式中，如图26至图28所示，第六扫描晶体管的第一极GT63的形状可以为沿第二方向D2延伸的条状。如图27所示，图5A中第六扫描晶体管的第一极GT63通过第四十三过孔与第六扫描晶体管的有源层的第一区连接，且通过第五十二过孔与第二扫描电容的第二极板连接。如图28所示，图6A中第六扫描晶体管的第一极GT63通过第四十二过孔与第六扫描晶体管的有源层的第一区连接，且通过第五十一过孔与第二扫描电容的第二极板连接。
在示例性实施方式中，如图26至图28所示，第八扫描晶体管的第一极GT83的形状可以为块状。如图27所示，图5A中第八扫描晶体管的第一极GT83通过第四十四过孔与第八扫描晶体管的有源层的第一区连接，且通过第四十九过孔与第五扫描晶体管的栅电极(也是第二扫描电容的第二极板)连接。如图28所示，图6A中第六扫描晶体管的第一极GT63通过第四十三过孔与第八扫描晶体管的有源层的第一区连接，且通过第四十八过孔与第五扫描晶体管的栅电极(也是第二扫描电容的第二极板)连接。
在示例性实施方式中，如图26至图28所示，第八扫描晶体管的第二极GT84的形状可以为块状。如图27所示，图5A中第八扫描晶体管的第二极GT84通过第四十五过孔与第八扫描晶体管的有源层的第二区连接，且通过第四十七过孔与第二扫描晶体管的栅电极连接。如图28所示，图6A中第八扫描晶体管的第二极GT84通过第四十四过孔与第八扫描晶体管的有源层的第二区连接，且通过第四十六过孔与第二扫描晶体管的栅电极连接。
在示例性实施方式中，如图27所示，图5A中第一扫描时钟信号线的第一子时钟信号线GCK1A和第二扫描时钟信号线的第三子时钟信号线GCK2A中的其中一条通过第四十六过孔与第一扫描晶体管的栅电极(也是第三扫描晶体管的栅电极)连接。如图28所示，图6A中第一扫描时钟信号线的第一子时钟信号线GCK1A和第二扫描时钟信号线的第三子时钟信号线GCK2A中的其中一条通过第四十五过孔与第一扫描晶体管的栅电极(也是第三扫描晶体管的栅电极)连接。
在示例性实施方式中，如图27所示，图5A中第一扫描时钟信号线的第一子时钟信号线GCK1A和第二扫描时钟信号线的第三子时钟信号线GCK2A中的另一条通过第五十过孔与第七扫描晶体管的栅电极连接。如图28所示，图6A中第一扫描时钟信号线的第一子时钟信号线GCK1A和第二扫描时钟信号线的第三子时钟信号线GCK2A中的另一条通过第四十九过孔与第七扫描晶体管的栅电极连接。
在示例性实施方式中，如图27所示，图5A中第二扫描电源线GVGH通过第五十一过孔与第八扫描晶体管的栅电极连接。如图28所示，图6A中第二扫描电源线GVGH通过第五十过孔与第八扫描晶体管的栅电极连接。
在示例性实施方式中，如图27所示，图5A中第一连接线CL1通过第五十五过孔与扫描输出信号线连接。如图28所示，图6A中第一连接线CL1通过第五十四过孔与扫描输出信号线连接。
在示例性实施方式中，如图27所示，图5A中第一条初始供电线的第一子初始供电线INITL1A和第四连接线CL4通过第五十六过孔与第一信号连接线连接。如图28所示，图6A中第一条初始供电线的第一子初始供电线INITL1A和第四连接线CL4通过第五十五过孔与第一信号连接线连接。
在示例性实施方式中，如图27所示，图5A中第二条初始供电线的第一子初始供电线INITL2A和第三连接线CL3通过第五十七过孔与第二信号连接线连接。如图28所示，图6A中第二条初始供电线的第一子初始供电线INITL2A和第三连接线CL3通过第五十六过孔与第二信号连接线连接。
在示例性实施方式中，如图46和图47所示，第一晶体管的第一极MT13的形状为沿第二方向D2延伸的条状。如图48和图49所示，第一晶体管的第一极MT13的形状为沿第一方向D1延伸的条状。如图46至图49所示，第一晶体管的第一极MT13通过第五十八过孔与第一晶体管的有源层的第一区电连接，且通过第六十五过孔与第一初始信号线电连接。
在示例性实施方式中，如图46至图49所示，第一晶体管的第二极MT14和第二晶体管的第一极MT23为一体结构，且形状为沿第一方向D1延伸的条状。第一晶体管的第二极MT14(也是第二晶体管的第一极MT23)通过第五十九过孔与第一晶体管的有源层的第二区(也是第二晶体管的有源层的第一区)电连接，且通过第六十四过孔与第三晶体管的栅电极(也是电容的第一极板)电连接。
在示例性实施方式中，如图46至图49所示，第四晶体管的第一极MT43的形状为块 状。第四晶体管的第一极MT43通过第六十过孔与第四晶体管的有源层的第一区电连接。
在示例性实施方式中，如图46和图47所示，第五晶体管的第一极M53至少部分沿第一方向D1延伸。第五晶体管的第一极M53通过第六十一过孔与第五晶体管的有源层的第一区电连接，且通过第六十六过孔与电容的第二极板电连接。
在示例性实施方式中，如图46至图49所示，第六晶体管的第二极MT64和第七晶体管的第一极MT74为一体结构，且形状为块状。第六晶体管的第二极MT64(也是第七晶体管的第一极MT74)通过第六十二过孔与第六晶体管的有源层的第二区(第七晶体管的有源层的第二区)电连接。
在示例性实施方式中，如图46至图49所示，第七晶体管的第一极MT73的形状为沿第一方向D1延伸的条状。第七晶体管的第一极MT73通过第六十三过孔与第七晶体管的有源层的第一区电连接，且通过第六十七过孔与第二初始信号线电连接。
在示例性实施方式中，如图46和图49所示，数据连接线DL至少部分沿第二方向D2延伸，且可以位于第六晶体管的第二极MT64(也是第七晶体管的第一极MT74)和第七晶体管的第一极MT73之间。
在示例性实施方式中，如图48和图49所示，第一子电源线VDDA的形状为至少部分沿第一方向D1延伸的线形状。第一子电源线VDDA与第五晶体管的有源层的第一区重叠区域复用为第五晶体管的第一极MT53。第一子电源线VDDA通过第六十一过孔与第五晶体管的有源层的第一区电连接，且通过第六十六过孔与电容的第二极板电连接。
在示例性实施方式中，如图48和图49所示，电极连接线CL与位于同一列的相邻子像素的第七晶体管的第一极MT73电连接。至少一列子像素的相邻子像素的第七晶体管的第一极MT73间隔设置，至少一列子像素的相邻子像素的第七晶体管的第一极MT73通过电极连接线CL电连接。其中，第j列子像素的相邻子像素的第七晶体管的第一极MT73间隔设置，第j+1列子像素的相邻子像素的第七晶体管的第一极MT73通过电极连接线CL电连接。电极连接线CL的设置可以与多条第二初始信号线形成网状结构，使得各个子像素中的第二初始信号线的信号一致，可以保证显示基板的显示效果。
在示例性实施方式中，如图48和图49所示，当位于同一列子像素的相邻子像素的第七晶体管的第一极MT73间隔设置时，穿过第七晶体管的第一极MT73的沿第一方向D1延伸的虚拟直线穿过第六晶体管的第二极MT64(也是第七晶体管的第一极MT74)。当位于同一列子像素的相邻子像素的第七晶体管的第一极MT73相互连接时，电极连接线CL在基底上的正投影与第六晶体管的第二极MT64(也是第七晶体管的第一极MT74)在基底上的正投影不交叠。
(7)形成第四绝缘层图案，包括：在形成有前述图案的基底上，沉积第四绝缘薄膜，涂覆第一平坦薄膜，通过图案化工艺对第四绝缘薄膜和第一平坦薄膜进行构图，形成覆盖前述结构的第四绝缘层以及设置在第四绝缘层上的平坦层图案，平坦层开设有凹槽以及多个过孔图案，如图29、图30、图50和图51所示，图29为图5A形成平坦层图案后的示意图，图30为图6A形成平坦层图案后的示意图，图50为图7B形成平坦层图案后的示意图，图51为图7C形成平坦层图案后的示意图。
在示例性实施方式中，如图29、图30、图50和图51所示，平坦层图案的多个过孔至少可以包括：第七十一过孔V71、第七十二过孔V72、第七十三过孔V73、第七十四过孔V74、第七十五过孔V75、第七十六过孔V76、第七十七过孔V77、第七十八过孔V78以及第六十八过孔V68至第七十过孔V70。
在示例性实施方式中，如图29和图30所示，第七十一过孔V71在基底上的正投影 位于第一扫描时钟信号线的第一子时钟信号线在基底上的正投影的范围之内，第七十一过孔V71内的第四绝缘层被刻蚀掉，暴露出第一扫描时钟信号线的第一子时钟信号线，第七十一过孔V71被配置为使后续形成的第一扫描时钟信号线的第二子时钟信号线通过该过孔与第一扫描时钟信号线的第一子时钟信号线连接。
在示例性实施方式中，如图29和图30所示，第七十二过孔V72在基底上的正投影位于第二扫描时钟信号线的第三子时钟信号线在基底上的正投影的范围之内，第七十二过孔V72内的第四绝缘层被刻蚀掉，暴露出第二扫描时钟信号线的第三子时钟信号线，第七十二过孔V72被配置为使后续形成的第二扫描时钟信号线的第四子时钟信号线通过该过孔与第二扫描时钟信号线的第三子时钟信号线连接。
在示例性实施方式中，如图29和图30所示，第七十三过孔V73在基底上的正投影位于第一条初始供电线的第一子初始供电线在基底上的正投影的范围之内，第七十三过孔V73内的第四绝缘层被刻蚀掉，暴露出第一条初始供电线的第一子初始供电线，第七十三过孔V73被配置为使后续形成的第一条初始供电线的第二子初始供电线通过该过孔与第一条初始供电线的第一子初始供电线连接。
在示例性实施方式中，如图29和图30所示，第七十四过孔V74在基底上的正投影位于第二条初始供电线的第一子初始供电线在基底上的正投影的范围之内，暴露出第二条初始供电线的第一子初始供电线，第七十四过孔V74被配置为使后续形成的第二条初始供电线的第二子初始供电线通过该过孔与第二条初始供电线的第一子初始供电线连接。
在示例性实施方式中，如图29和图30所示，第七十五过孔V75在基底上的正投影位于第一连接线在基底上的正投影的范围之内，第七十五过孔V75内的第四绝缘层刻蚀掉，暴露出第一连接线，第七十五过孔V75被配置为使后续形成的第五连接线通过该过孔与第一连接线连接。
在示例性实施方式中，如图29和图30所示，第七十六过孔V76在基底上的正投影位于第二连接线在基底上的正投影的范围之内，第七十六过孔V76内的第四绝缘层刻蚀掉，暴露出第二连接线，第七十六过孔V76被配置为使后续形成的第六连接线通过该过孔与第二连接线连接。
在示例性实施方式中，如图29和图30所示，第七十七过孔V77在基底上的正投影位于第三连接线在基底上的正投影的范围之内，第七十七过孔V77内的第四绝缘层刻蚀掉，暴露出第一连接线，第七十七过孔V77被配置为使后续形成的第七连接线通过该过孔与第三连接线连接。
在示例性实施方式中，如图29和图30所示，第七十八过孔V78在基底上的正投影位于第四连接线在基底上的正投影的范围之内，第七十八过孔V78内的第四绝缘层刻蚀掉，暴露出第四连接线，第七十八过孔V78被配置为使后续形成的第八连接线通过该过孔与第四连接线连接。
在示例性实施方式中，如图50和图51所示，第六十八过孔V68在基底上的正投影位于第四晶体管的第一极在基底上的正投影的范围之内，暴露出第四晶体管的第一极，第六十八过孔V68被配置为使后续形成的数据信号线通过该过孔与第四晶体管的第一极连接。
在示例性实施方式中，如图50所示，第六十九过孔V69在基底上的正投影位于第五晶体管的第一极在基底上的正投影的范围之内，暴露出第五晶体管的第一极，第六十九过孔V69被配置为使后续形成的第一电源线通过该过孔与第五晶体管的第一极连接。
在示例性实施方式中，如图51所示，第六十九过孔V69在基底上的正投影位于第一 子电源线在基底上的正投影的范围之内，暴露出第一子电源线，第六十九过孔V69被配置为使后续形成的第二子电源线通过该过孔与第一子电源线连接。
在示例性实施方式中，如图50和图51所示，第七十过孔V70在基底上的正投影位于第六晶体管的第二极(也是第七晶体管的第二极)在基底上的正投影的范围之内，暴露出第六晶体管的第二极(也是第七晶体管的第二极)，第七十过孔V70被配置为使后续形成的阳极连接电极通过该过孔与第六晶体管的第二极(也是第七晶体管的第二极)连接。
在示例性实施方式中，图5A和图6A中设置有第四绝缘层，但是设置在图5A各图6A中的第四绝缘层没有过孔。
(8)形成第四导电层图案，包括：在形成前述图案的基底上，沉积第四导电薄膜，通过图案化工艺对第四导电薄膜进行构图，形成第四导电层图案，如图31、图32、图33、图52至图55所示，图31为图5A和图6A的第四导电层图案的示意图，图32为图5A形成第四导电层图案后的示意图，图33为图6A形成第四导电层图案后的示意图，图52为图7B的第四导电层图案的示意图，图53为图7B形成第四导电层图案后的示意图，图54为图7C的第四导电层图案后的示意图，图55为图7C形成第四导电层图案的示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，如图31至图33所示，第四导电层图案至少可以包括：第一扫描时钟信号线的第二子时钟信号线GCK1B、第二扫描时钟信号线的第四子时钟信号线GCK2B、第一条初始供电线的第二子初始供电线INITL1B、第二条初始供电线的第二子初始供电线INITL2B、第五连接线CL5、第六连接线CL6、第七连接线CL7和第八连接线CL8。
在示例性实施方式中，第一扫描时钟信号线的第二子时钟信号线GCK1B的形状为第一方向D1的线形状。第一扫描时钟信号线的第二子时钟信号线通过第七十一过孔与第一扫描时钟信号线的第一子时钟信号线。
在示例性实施方式中，第一扫描时钟信号线的第二子时钟信号线GCK1B在基底上的正投影与第一扫描时钟信号线的第一子时钟信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，第二扫描时钟信号线的第四子时钟信号线GCK2B的形状为第一方向D1的线形状。第二扫描时钟信号线的第四子时钟信号线通过第七十二过孔与第二扫描时钟信号线的第三子时钟信号线。
在示例性实施方式中，第二扫描时钟信号线的第四子时钟信号线GCK2B在基底上的正投影与第二扫描时钟信号线的第三子时钟信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，第一条初始供电线的第二子初始供电线的形状为第一方向D1的线性状。第一条初始供电线的第二子初始供电线通过第七十三过孔与第一条初始供电线的第一子初始供电线连接。
在示例性实施方式中，第一条初始供电线的第二子初始供电线在基底上的正投影与第一条初始供电线的第一子初始供电线在基底上的正投影至少部分交叠。
在示例性实施方式中，第二条初始供电线的第二子初始供电线的形状为第一方向D1的线性状。第二条初始供电线的第二子初始供电线通过第七十四过孔与第二条初始供电线的第一子初始供电线连接。
在示例性实施方式中，第二条初始供电线的第二子初始供电线在基底上的正投影与第二条初始供电线的第一子初始供电线在基底上的正投影至少部分交叠。
在示例性实施方式中，第五连接线CL5的形状可以为块状。第五连接线CL5通过第 七十五过孔与第一连接线连接。
在示例性实施方式中，第六连接线CL6的形状可以为块状。第六连接线CL6通过第七十六过孔与第二连接线连接。
在示例性实施方式中，第七连接线CL7的形状可以为块状。第七连接线CL7通过第七十七过孔与第三连接线连接。
在示例性实施方式中，第八连接线CL8的形状可以为块状。第八连接线CL8通过第七十八过孔与第四连接线连接。
在示例性实施方式中，如图52至图55所示，第四导电层图案至少可以包括：数据信号线Data、阳极连接电极VL、平坦部BL。
在示例性实施方式中，如图52和图53所示，第四导电层图案还可以包括：第一电源线VDD。
在示例性实施方式中，如图54和图55所示，第四导电层图案还可以包括：第二子电源线VDDB。第二子电源线VDDB和第一子电源线构成第一电源线。
在示例性实施方式中，如图52至图55所示，数据信号线Data沿第一方向D1延伸。数据信号线Data通过第六十八过孔与第四晶体管的第一极电连接。
在示例性实施方式中，如图52至图55所示，阳极连接电极VL沿第一方向D1延伸。阳极连接电极VL通过第七十过孔与第六晶体管的第二极(也是第七晶体管的第一极)电连接。
在示例性实施方式中，如图52和图53所示，平坦部BL与第一电源线VDD为一体结构。平坦部BL在基底上的正投影与发光器件的阳极在基底上的正投影至少部分交叠。
在示例性实施方式中，如图54和图55所示，平坦部BL与第二子电源线VDDB为一体结构。平坦部BL在基底上的正投影与发光器件的阳极在基底上的正投影至少部分交叠。
在示例性实施方式中，如图52和图53所示，第一电源线VDD沿第一方向D1延伸。第一电源线VDD通过第六十九过孔与第五晶体管的第一极电连接。
在示例性实施方式中，如图52和图53所示，第二子电源线VDD沿第一方向D1延伸。第二子电源线VDD通过第六十九过孔与第一子电源线电连接。
(9)形成第六绝缘层图案。在示例性实施方式中，形成平坦层可以包括：在形成前述图案的基底上，沉积第五绝缘薄膜和第五导电薄膜，采用图案化工艺对第五导电薄膜进行图案化，形成设置在第五绝缘层和设置在第五绝缘层上的第五导电层，在形成前述图案的基底上，沉积第六绝缘薄膜，采用图案化工艺对第六绝缘薄膜进行图案化，形成覆盖第五导电层图案的第六绝缘层。
在示例性实施方式中，第五导电层可以包括：阳极连接线。
至此，在基底上制备完成驱动结构层。在平行于显示基板的平面内，驱动结构层驱动结构层可以包括在基底上依次设置的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、平坦层、第四导电层、第五绝缘层、第五导电层和第六绝缘层。
在示例性实施方式中，半导体层可以为金属氧化物层。金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物或者包含铟或 镓和锌的氧化物。金属氧化物层可以单层，或者可以是双层，或者可以是多层。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
在示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在示例性实施方式中，第五导电层可以采用氧化铟锡(ITO)或氧化铟锌(IZO)材料。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层和第二绝缘层可以称为栅绝缘(GI)层，第三绝缘层可以称为层间绝缘(ILD)层。
在示例性实施方式中，平坦层可以采用有机材料，如树脂等。
在示例性实施方式中，制备完成驱动结构层后，在驱动结构层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
形成发光结构层。在示例性实施方式中，形成发光结构层可以包括：在形成前述图案上沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在平坦层上的阳极导电层，阳极导电层至少包括多个阳极图案，在形成前述图案的基底上，涂覆像素定义薄膜，采用图案化工艺对像素定义薄膜进行图案化，形成像素定义层，在形成前述图案的基底上，先采用蒸镀或喷墨打印工艺形成有机发光层，然后在有机发光层上形成阴极，然后形成封装结构层。
在示例性实施方式中，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，像素定义层的材料可以包括聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯。
在示例性实施方式中，阳极薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)。
在示例性实施方式中，阴极薄膜可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或多种，或采用上述金属中任意一种或多种制成的合金。
本公开中的静电释放电路与栅极驱动电路采用相同工艺形成，可以在保证显示基板的可靠性的同时，不增加工艺制程。
本公开实施例还提供了一种显示装置，该显示装置可以包括：显示基板和感光传感器。感光传感器位于显示基板内。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在示例性实施方式中，显示装置可以为液晶显示装置(Liquid Crystal Display，简称LCD)或有机发光二极管(Organic Light Emitting Diode，简称OLED)显示装置。该显示装置可以为：液晶面板、电子纸、OLED面板、有源矩阵有机发光二极管(active-matrix  organic light emitting diode，简称AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (21)

  1. 一种显示基板，包括：基底以及设置在基底上的驱动结构层，所述基底包括显示区域和非显示区域，所述驱动结构层包括：位于显示区域的多个像素电路和位于非显示区域的栅极驱动电路和静电释放电路，栅极驱动电路包括多个驱动电路，所述多个驱动电路和所述静电释放电路沿靠近所述显示区域的方向排列；
    所述静电释放电路设置在相邻的两个驱动电路之间，且与相邻的两个驱动电路中任一个电路的至少一条信号线电连接。
  2. 根据权利要求1所述的显示基板，其中，所述静电释放电路至少包括：第一释放晶体管和第二释放晶体管；
    第一释放晶体管的栅电极和第二极与第一信号端连接，第一释放晶体管的第一极与第二信号端连接；
    第二释放晶体管的栅电极和第一极与第三信号端连接，第二释放晶体管的第二极与第一信号端连接。
  3. 根据权利要求2所述的显示基板，其中，所述多个驱动电路包括：发光驱动电路和扫描驱动电路，所述扫描驱动电路位于所述发光驱动电路靠近显示区域的一侧；
    所述驱动结构层还包括：位于非显示区域的发光初始信号线、第一发光时钟信号线、第二发光时钟信号线、第一发光电源线、第二发光电源线，扫描初始信号线、第一扫描时钟信号线、第二扫描时钟信号线、第一扫描电源线和第二扫描电源线；发光初始信号线、第一发光时钟信号线、第二发光时钟信号线、第一发光电源线、第二发光电源线，扫描初始信号线、第一扫描时钟信号线、第二扫描时钟信号线、第一扫描电源线和第二扫描电源线中的任一条沿第一方向延伸；
    所述发光驱动电路分别与发光初始信号线、第一发光时钟信号线、第二发光时钟信号线、第一发光电源线和第二发光电源线电连接；所述扫描驱动电路分别与扫描初始信号线、第二扫描时钟信号线、第一扫描时钟信号线、第一扫描电源线和第二扫描电源线电连接；
    所述发光初始信号线、所述第一发光时钟信号线、所述第二发光时钟信号线、所述第一发光电源线、所述第二发光电源线、所述第一扫描电源线、所述第一扫描时钟信号线、所述第二扫描时钟信号线、所述扫描初始信号线和所述第二扫描电源线沿靠近所述显示区域的方向依次排列。
  4. 根据权利要求3所述的显示基板，其中，所述静电释放电路在基底上的正投影与所述第一扫描电源线和所述第二发光电源线部分交叠，且至少部分静电释放电路位于所述第二发光电源线和所述第一扫描电源线之间。
  5. 根据权利要求4所述的显示基板，其中，所述驱动结构层还包括：位于非显示区域的发光输出信号线和扫描输出信号线以及至少部分位于显示区域的发光信号线和扫描信号线；扫描输出信号线、发光信号线和扫描信号线中的任一条至少部分沿第二方向延伸，所述第一方向与所述第二方向相交；所述像素电路，分别与发光信号线和扫描信号线连接；
    所述发光驱动电路包括：多个级联的发光移位寄存器，所述扫描驱动电路包括：多个级联的扫描移位寄存器；
    所述发光输出信号线，分别与发光移位寄存器和至少一条发光信号线电连接；
    所述扫描输出信号线，分别与扫描移位寄存器和扫描信号线电连接。
  6. 根据权利要求5所述的显示基板，其中，所述静电释放电路的第一信号端与所述 发光输出信号线电连接，所述静电释放电路的第二信号端与所述第二发光电源线电连接，所述静电释放电路的第三信号端与所述第一扫描电源线电连接。
  7. 根据权利要求3至6任一项所述的显示基板，其中，所述第二发光电源线和所述第一扫描电源线之间的距离约为8微米至15微米。
  8. 根据权利要求6所述的显示基板，其中，所述发光移位寄存器包括多个发光晶体管和多个发光电容，所述扫描移位寄存器包括多个扫描晶体管和多个扫描电容，所述发光电容和所述扫描电容均包括第一极板和第二极板，所述驱动结构层包括：依次叠设的半导体层、第一导电层、第二导电层、第三导电层和第四导电层，所述第一扫描时钟信号线包括：相互电连接的第一子时钟信号线和第二子时钟信号线，所述第二扫描时钟信号线包括：相互电连接的第三子时钟信号线和第四子时钟信号线；
    所述半导体层至少包括：多个发光晶体管的有源层、多个扫描晶体管的有源层、第一释放晶体管的有源层和第二释放晶体管的有源层；
    所述第一导电层至少包括：发光信号线、扫描信号线、多个发光晶体管的栅电极、多个发光电容的第一极板，多个扫描晶体管的栅电极、多个扫描电容的第一极板、第一释放晶体管的栅电极和第二释放晶体管的栅电极；
    所述第二导电层至少包括：多个发光电容的第二极板、多个扫描电容的第二极板、扫描输出信号线和发光输出信号线；
    所述第三导电层至少包括：发光初始信号线、第一发光时钟信号线、第二发光时钟信号线、第一发光电源线、第二发光电源线，扫描初始信号线、第一扫描时钟信号线的第一子时钟信号线、第二扫描时钟信号线的第三子时钟信号线、第一扫描电源线、第二扫描电源线、多个发光晶体管的第一极和第二极、多个扫描晶体管的第一极和第二极、第一释放晶体管的第一极和第二极以及第二释放晶体管的第一极和第二极；
    所述第四导电层至少包括：第一扫描时钟信号线的第二子时钟信号线和第二扫描时钟信号线的第四子时钟信号线。
  9. 根据权利要求8所述的显示基板，其中，多个发光晶体管的第一极和第二极位于第一发光电源线和第二发光电源线之间，第一释放晶体管的第一极和第二极至第二释放晶体管的第一极和第二极位于第二发光电源线和第一扫描电源线之间，部分扫描晶体管的第一极和第二极位于扫描初始信号线和第二扫描电源线之间，另一部分扫描晶体管的第一极和第二极可以位于第二扫描电源线靠近显示区域的一侧。
  10. 根据权利要求8所述的显示基板，其中，至少一条所述发光输出信号线包括：输出连接部和至少一条输出线，所述输出连接部沿第一方向延伸，至少一条所述输出线沿第一方向排布；
    所述输出连接部，分别与发光移位寄存器和至少一条输出线电连接，所述输出线与发光输出信号线所连接的发光信号线一一对应，且与对应的发光信号线电连接。
  11. 根据权利要求10所述的显示基板，其中，所述输出线包括：至少部分沿第二方向延伸的输出主体部和沿第一方向延伸的输出连接部，所述输出主体部与所述输出连接部电连接；
    第一释放晶体管的第二极和第二释放晶体管的第二极为一体结构，且在基底上的正投影与输出连接部在基底上的正投影至少部分交叠，第一释放晶体管的第二极和第二释放晶体管的第二极的一体结构与输出连接部电连接。
  12. 根据权利要求11所述的显示基板，其中，第一释放晶体管的有源层和第二释放 晶体管的有源层为一体结构，且沿第二方向延伸；
    所述输出连接部在基底上的正投影与第一释放晶体管的有源层和第二释放晶体管的有源层的一体结构在基底上的正投影不交叠。
  13. 根据权利要求10所述的显示基板，其中，第一释放晶体管的有源层和第二释放晶体管的有源层为一体结构，且包括：有源主体部和有源连接部，有源主体部和有源连接部电连接，有源主体部和有源连接部沿第一方向排布；
    所述有源主体部沿第二方向延伸，所述有源连接部至少部分沿第一方向延伸；
    所述有源连接部的形状为折线形。
  14. 根据权利要求13所述的显示基板，其中，所述输出线至少部分沿第二方向延伸；第一释放晶体管的第二极和第二释放晶体管的第二极为一体结构；
    所述有源连接部在基底上的正投影与第一释放晶体管的第二极和第二释放晶体管的第二极的一体结构和输出线在基底上的正投影至少部分交叠，且分别与第一释放晶体管的第二极和第二释放晶体管的第二极的一体结构和输出线电连接。
  15. 根据权利要求13或14所述的显示基板，其中，所述有源连接部的宽度小于所述有源主体部的宽度。
  16. 根据权利要求8所述的显示基板，其中，所述扫描移位寄存器包括：第一扫描电容，第一扫描电容的第二极板与第一扫描电源线电连接，第一扫描电容的第二极板沿第二方向延伸；
    第一扫描电容的第二极板在基底上的正投影与第一扫描电源线、第二扫描电源线、第一扫描时钟信号线、第二扫描时钟信号线和扫描初始信号线在基底上的正投影至少部分交叠。
  17. 根据权利要求1所述的显示基板，其中，所述显示区域包括：第一显示区和位于所述第一显示区至少一侧的第二显示区，所述显示基板还包括：位于所述显示区域的发光器件和阳极连接线，像素电路与发光器件电连接；所述像素电路包括：位于所述第二显示区的第一像素电路和第二像素电路，所述发光器件包括：位于所述第一显示区的第一发光器件和位于第二显示区的第二发光器件，第一像素电路与第一发光器件电连接，第二像素电路与第二发光器件电连接；
    第一像素电路在基底上的正投影与第一像素电路所连接的第一发光器件在基底上的正投影至少部分交叠；
    所述阳极连接线分别与第二发光器件和与第二发光器件所连接的第二像素电路电连接。
  18. 根据权利要求17所述的显示基板，其中，所述驱动结构层还包括：至少部分位于显示区域的第一电源线、数据信号线和数据连接线；所述第一电源线和所述数据信号线至少部分沿第一方向延伸，所述数据连接线至少部分沿第二方向延伸；
    所述驱动结构层还包括：依次叠设在第三导电层上的第四导电层和第五导电层；
    所述第三导电层至少包括：数据连接线；
    所述第四导电层至少包括：第一电源线和数据信号线；
    所述第五导电层至少包括：阳极连接线；
    所述第五导电层为透明导电层。
  19. 根据权利要求18所述的显示基板，其中，所述驱动结构层还包括：位于所述第三导电层和所述第四导电之间的平坦层，所述平坦层设置有凹槽；
    所述静电释放电路在基底上的正投影与凹槽在基底上的正投影至少部分交叠。
  20. 根据权利要求19所述的显示基板，其中，所述驱动结构层还包括：位于非显示区域的至少一条初始供电线和至少部分位于显示区域的至少一条初始信号线；初始供电线位于扫描驱动电路靠近显示区域的一侧，初始供电线至少部分沿第一方向延伸，初始信号线至少部分沿第二方向延伸；所述初始供电线包括相互电连接的第一子初始供电线和第二子初始供电线；
    至少一条初始信号线与至少一条初始供电线一一对应，初始信号线，分别与像素电路和对应的初始供电线电连接；
    所述第二导电层至少包括：初始信号线；
    所述第三导电层至少包括：初始供电线的第一子初始供电线；
    所述第四导电层至少包括：初始供电线的第二子初始供电线。
  21. 一种显示装置，包括：如权利要求1至20任一项所述的显示基板和感光传感器，感光传感器位于所述显示基板内。
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