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WO2024187941A1 - Packaging structure and forming method - Google Patents

Packaging structure and forming method Download PDF

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Publication number
WO2024187941A1
WO2024187941A1 PCT/CN2024/071820 CN2024071820W WO2024187941A1 WO 2024187941 A1 WO2024187941 A1 WO 2024187941A1 CN 2024071820 W CN2024071820 W CN 2024071820W WO 2024187941 A1 WO2024187941 A1 WO 2024187941A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
inductor
chip
magnetic film
film layer
Prior art date
Application number
PCT/CN2024/071820
Other languages
French (fr)
Chinese (zh)
Inventor
陈海杰
刘涛
王长文
Original Assignee
江阴长电先进封装有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 江阴长电先进封装有限公司 filed Critical 江阴长电先进封装有限公司
Publication of WO2024187941A1 publication Critical patent/WO2024187941A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/20Inductors

Definitions

  • the present invention relates to the technical field of chip packaging, in particular to a packaging structure and a forming method.
  • chiplet packaging is becoming more and more widely used.
  • chiplet technology heterogeneous or homogeneous chips can be combined to ultimately achieve functional superposition or microsystem integration.
  • inductor devices are generally attached to a substrate or a printed circuit board as discrete devices. This installation method of inductor devices wastes packaging area and increases the size of the package structure after packaging.
  • the purpose of the present invention is to provide a packaging structure to solve the deficiencies in the prior art. It can combine the inductor coil with the chip rewiring process without affecting the performance of the inductor coil, thereby improving the integration of the chip packaging structure and reducing the overall size of the packaging structure.
  • the packaging structure provided by the present invention comprises: a rewiring structure having an insulator and a plurality of patterned metal layers embedded in the insulator, at least one of the patterned metal layers having a wiring circuit and an inductor circuit forming an inductor coil; the rewiring structure further comprises a magnetic film layer, and in the thickness direction of the rewiring structure, the magnetic film layer is arranged on at least one side of the inductor coil;
  • the chip is arranged on one side of the rewiring structure along the thickness direction and is electrically connected to the wiring line.
  • the position of the inductor coil is opposite to the position of the magnetic film layer.
  • the magnetic film layer is embedded in the insulator, and the magnetic film layer and the inductor coil are separated by a portion of the insulator.
  • the insulator has a first surface and a second surface disposed in opposite directions; the magnetic film layer is disposed on at least one of the first surface and the second surface.
  • the magnetic film layer is provided with at least two layers, and the inductor coil is provided between the two magnetic film layers.
  • the inductor coil is also provided with at least two layers;
  • the inductor coils and the magnetic film layers are arranged alternately.
  • the magnetic film layer is a superposition of one or more of an iron-containing metal film layer, a nickel-containing metal film layer, a cobalt-containing metal film layer, an iron-nickel alloy film layer, an iron-cobalt alloy film layer, a nickel-cobalt alloy film layer, or an iron-nickel-cobalt alloy film layer.
  • the packaging structure further comprises a metal bump, the metal bump is arranged on a side of the rewiring structure away from the chip, and the metal bump is electrically connected to the wiring line;
  • the packaging structure also has an inductor bump, which is arranged on a side of the rewiring structure away from the chip, and is electrically connected to the inductor coil; the inductor coil and the wiring line are separated by a portion of the insulator.
  • the chip includes a first chip and a second chip arranged in parallel on one side of the rewiring structure;
  • the packaging structure further includes:
  • a bridge chip arranged on a side of the rewiring structure away from the chip and electrically connected to the first chip and the second chip respectively;
  • a bridge chip protection layer is disposed on the second surface of the insulator and covers the bridge chip, and a protection layer through hole penetrating the bridge chip protection layer is disposed on the bridge chip protection layer;
  • a conductive bump is disposed in the through hole of the protection layer and electrically connected to the wiring line.
  • the packaging structure further comprises a metal bump, the metal bump is arranged on a side of the bridge chip protection layer away from the insulator, and the metal bump is electrically connected to the conductive bump.
  • packaging structure further includes:
  • a bottom rewiring layer is arranged on a side of the bridge chip protection layer away from the insulator and comprises a bottom insulating layer and a bottom metal layer arranged in the bottom insulating layer;
  • the metal bumps and the conductive bumps are arranged opposite to each other at two sides of the bottom redistribution layer and are electrically connected through the bottom metal layer.
  • Another embodiment of the present invention further discloses a method for forming the packaging structure, comprising the following steps:
  • the rewiring structure is formed on a side of the bonding layer away from the carrier substrate, wherein the rewiring structure comprises an insulator and a plurality of patterned metal layers embedded in the insulator, and at least one of the patterned metal layers comprises a wiring circuit and an inductor circuit forming an inductor coil;
  • the carrier substrate and the bonding layer are removed.
  • FIG1 is a schematic structural diagram of a first type of packaging structure of the present invention.
  • FIG2 is a schematic structural diagram of a second type of packaging structure of the present invention.
  • 3A-3E are schematic diagrams showing the formation process of the first type of packaging structure of the present invention.
  • FIGS. 4A-4G are schematic diagrams showing the formation process of the second type of packaging structure of the present invention.
  • Reference numerals Description of reference numerals: Description of reference numerals: 1-rewiring structure, 11-insulator, 111-first surface, 112-second surface, 12-patterned metal layer, 121-wiring line, 122-inductor coil, 123-coil connecting portion, 13-magnetic film layer,
  • the present invention discloses a packaging structure, which can integrate the passive components of an inductor device on a rewiring structure of the packaging structure, thereby realizing an integrated arrangement of the inductor device and a chip packaging structure.
  • the inductor device includes an inductor coil.
  • FIG. 1 is a complete structure of the packaging structure of the first embodiment of the present invention after packaging is completed.
  • FIG. 2 is a complete structure of the packaging structure of the second embodiment of the present invention after packaging is completed.
  • FIGS. 3A-3E it is a schematic diagram of the process structure formed by the packaging structure disclosed in the first embodiment of the present invention.
  • FIGS. 4A-4G it is a schematic diagram of the process structure formed by the packaging structure disclosed in the second embodiment of the present invention.
  • the packaging structure in the second embodiment is a stacked chip packaging structure.
  • the packaging structure disclosed in the first embodiment of the present invention includes a rewiring structure 1 and a chip 2 electrically connected to the rewiring structure 1 ;
  • the rewiring structure 1 includes an insulator 11 and a plurality of patterned metal layers 12 embedded in the insulator 11; the plurality of patterned metal layers 12 are arranged along the thickness direction of the rewiring structure 1 and are electrically connected to each other. It is understandable that different patterned metal layers 12 are extended at different heights, and the patterned metal layers 12 electrically connected to each other can be two adjacent patterned metal layers 12 electrically connected, or two cross-layer patterned metal layers 12 electrically connected. The layer 12 realizes electrical connection. The specific connection method and design method of the different patterned metal layers 12 in the rewiring structure 1 are carried out according to actual needs, and no excessive restrictions are made here.
  • At least one patterned metal layer 12 has a wiring circuit 121 and an inductor circuit forming an inductor coil 122.
  • some patterned metal layers 12 have inductor circuits formed therein, and the patterned metal layers 12 without inductor circuits have wiring circuits formed therein.
  • the wiring lines 121 of different patterned metal layers 12 are electrically connected to each other, and the wiring lines 121 are electrically connected to the pads of the chip 2.
  • the rewiring structure 1 further includes a magnetic film layer 13, which is disposed on at least one side of the inductor 122 in the thickness direction of the rewiring structure 1, so that at least a portion of the magnetic film layer 13 and at least a portion of the inductor 122 are opposite in the thickness direction of the rewiring structure 1;
  • the magnetic film layer 13 may be disposed on one side of the inductor 122 .
  • the magnetic film layer 13 may also be disposed on both sides of the inductor 122 at the same time.
  • the inductor coil 122 is configured to be formed simultaneously with the patterned metal layer 12 , so that the inductor coil 122 is a part of the patterned metal layer 12 , thereby improving the integration of the inductor coil and the rewiring structure 1 .
  • the embodiment of the present invention combines the inductor coil 122 with the rewiring process so that the inductor coil 122 is encapsulated in the insulator 11 of the rewiring structure 1, thereby realizing the integration of the inductor coil 122 and the chip packaging structure.
  • the signal of the inductor coil 122 is amplified, so that the inductor coil 122 is integrated in the rewiring structure 1 without affecting the performance of the inductor coil 122, thereby eliminating the weakening of the performance of the inductor coil 122 after the integrated setting, improving the integration of the packaging structure, and reducing the size of the packaging structure after packaging.
  • the embodiment of the present invention integrates the inductor 122 with the rewiring structure, thereby improving the integration of the device.
  • the position of the inductor 122 is opposite to the position of the magnetic film layer 13. After the magnetic film layer 13 is opposite to the inductor 122, it can amplify the signal of the inductor 122, thereby enhancing the working effect of the inductor 122.
  • the magnetic film layer 13 is located directly above or below the inductor 122; in the thickness direction of the rewiring structure 1, the projection pattern of the magnetic film layer 13 toward the plane where the inductor 122 is located completely covers the position of the inductor 122.
  • the size of the magnetic film layer 13 can be set to be the same as the size of the inductor coil 122 .
  • the magnetic film layer 13 and the inductor coil 122 are completely opposite to each other in the thickness direction of the rewiring structure 1 .
  • the size of the magnetic film layer 13 can also be set to be larger than the size of the inductor 122.
  • Such a structural setting can better realize the function of the magnetic film layer 13, so that in the thickness direction of the rewiring structure 1, the magnetic film layer 13 can completely cover the signal of the inductor 122, so that each inductor 122 has a corresponding magnetic film layer 13 opposite to it, so that the magnetic film layer 13 can have an effect on the inductor 122 at the corresponding position.
  • the magnetic film layer 13 is in a sheet shape as a whole and is arranged perpendicular to the thickness direction of the rewiring structure 1.
  • the inductor coil 122 is also in a sheet shape and is arranged perpendicular to the thickness direction of the rewiring structure 1.
  • the plane where the magnetic film layer 13 is located is arranged parallel to the plane where the inductor coil 122 is located.
  • the extended plane of the magnetic film layer 13 can also be arranged to be oblique to the extended plane of the inductor coil 122.
  • the magnetic film layer 13 and the inductor coil 122 may partially face each other in the thickness direction of the rewiring structure 1.
  • the projection pattern of the magnetic film layer 13 toward the plane where the inductor coil 122 is located partially falls into the location where the inductor coil 122 is located. In this case, only a portion of the magnetic film layer 13 plays a role in amplifying the signal of the inductor coil 122.
  • the magnetic film layer 13 is embedded in the insulator 11 , the insulator 11 wraps the magnetic film layer 13 , and the magnetic film layer 13 and the inductor 122 are separated by a portion of the insulator 11 .
  • the magnetic film layer 13 Since the inductor 122 and the magnetic film layer 13 are both embedded in the insulator 11, in order to avoid a short circuit between the magnetic film layer 13 and the inductor 122, the magnetic film layer 13 cannot be directly set on the surface of the inductor 122, and other components are required to separate the two to form a spacing setting.
  • a rewiring structure 1 is generally formed.
  • the insulator 11 that wraps the inductor 122 also wraps the magnetic film layer 13 , that is, the inductor 122 and the magnetic film layer 13 are arranged in the same insulator 11 .
  • the stacked packaging structure As shown in FIG2 , it is generally stacked with multiple layers of chips, and a multi-layer rewiring structure 1 is provided at this time, and accordingly, a plurality of insulators 11 are also provided. Since a plurality of insulators 11 are provided, the insulator 11 wrapping the inductor 122 can also wrap the magnetic film layer 13 (as shown in FIG2 ). Of course, the insulator 11 wrapping the inductor 122 and the insulator 11 wrapping the magnetic film layer 13 can also be two different insulators (not shown), that is, the inductor 122 and the magnetic film layer 13 can be provided in different rewiring structures 1.
  • the magnetic film layer 13 is arranged as close to the inductor 122 as possible. That is, even if multiple rewiring structures are provided, the insulator 11 wrapping the inductor 122 and the insulator 11 wrapping the magnetic film layer 13 are arranged as the same insulator 11 as possible.
  • part of the magnetic film layer 13 and part of the inductor 122 are positioned opposite to each other in the thickness direction of the rewiring structure 1 , so that the magnetic film layer 13 and the inductor 122 are matched.
  • the magnetic film layer 13 and the inductor 122 when the magnetic film layer 13 and the inductor 122 are arranged in the same rewiring structure 1, the magnetic film layer 13 and the inductor 122 may be separated by a portion of an insulator. In other embodiments, when the magnetic film layer 13 and the inductor 122 are arranged in different rewiring structures, the magnetic film layer 13 and the inductor 122 may also be separated by an insulator, a plastic layer, etc.
  • the insulator 11 has a first surface 111 and a second surface 112 disposed in opposite directions; the magnetic film layer 13 is disposed on at least one of the first surface 111 and the second surface 112 .
  • the magnetic film layer 13 When the magnetic film layer 13 is embedded in the insulator 11, the magnetic film layer 13 can be formed simultaneously with the patterned metal layer 12. When the magnetic film layer 13 is disposed on the surface of the insulator 11, the magnetic film layer 13 can be formed by attaching.
  • the magnetic film layer 13 can be a metallic soft magnetic material.
  • the magnetic film layer 13 is a metal film layer containing one of the elements such as iron, cobalt, and nickel, specifically an iron-containing metal film, or a nickel-containing metal film, or a cobalt-containing metal film, or an iron-nickel alloy film, or an iron-cobalt alloy film, or a nickel-cobalt alloy film, or an iron-nickel-cobalt alloy film.
  • Metallic soft magnetic materials have high saturation magnetization, high magnetic permeability, and low coercivity, and they can be prepared by sputtering, evaporation or electroplating, and are well compatible with current packaging processes.
  • the rewiring structure 1 disclosed in the embodiment of the present invention is formed by using a typical rewiring technology, using a multi-layer polyimide film layer with photosensitive properties as an insulating layer and forming the insulator 11 in the process of stacking the multi-layer insulating layers.
  • the insulating layer includes or is made of one or more polymer materials.
  • the polymer material may include polybenzoxazole (PBO), polyimide (PI), epoxy resin, one or more other suitable polymer materials or a combination thereof.
  • PBO polybenzoxazole
  • PI polyimide
  • epoxy resin epoxy resin
  • the polymer material used for the insulating layer is photosensitive. Therefore, a circuit pattern can be formed in the insulating layer using a photolithography process.
  • part or all of the insulating layer further includes or is made of a dielectric material other than the polymer material.
  • the dielectric material may include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or a combination thereof.
  • the insulating layer can be formed by coating, deposition and other methods, and then the insulating layer in the target area is etched to form insulating windows at the target position, and a circuit pattern is formed with all the insulating windows in the insulating layer. Then, electroplating and other methods are used to set the patterned metal layer 12 in the circuit pattern or on the upper surface of the corresponding insulating layer; the entire rewiring structure 1 needs to be finally formed through multiple coating, etching, electroplating and other process steps during the photolithography process.
  • the first insulating layer is arranged first, and a first circuit pattern is opened in the target area of the first insulating layer.
  • a first patterned metal layer is formed on the upper surface of the first insulating layer, and a portion of the first patterned metal layer is filled in the first circuit pattern;
  • a second insulating layer is arranged on the upper surface of the first insulating layer, a second circuit pattern is arranged in a target area of the second insulating layer, the second circuit pattern penetrates the second insulating layer, and a portion of the first patterned metal layer is exposed outward from the second circuit pattern; a second patterned metal layer is arranged on the upper surface of the second insulating layer, and a portion of the second patterned metal layer is arranged in the second circuit pattern and is electrically connected to the first patterned metal layer.
  • a coil opening can be arranged on the insulating layer at the same time to form an inductor circuit, and the inductor 122 is finally arranged in the coil opening.
  • the inductor 122 can also be directly arranged on the first surface of the insulating layer without the need to arrange a circuit pattern on the corresponding insulating layer.
  • the thickness of the inductor coil 122 can be the same as the thickness of the wiring line 121 of the patterned metal layer 12 of the corresponding insulating layer.
  • the depth of the coil opening opened on the insulating layer and the circuit pattern can be set to be consistent, and the inductor coil 122 and the wiring line 121 can be set at the same time.
  • the thickness of the inductor 122 can also be less than the thickness of the wiring line 121 in the corresponding patterned metal layer 12.
  • the depth of the coil window opened on the insulating layer can be less than the depth of the line pattern on the insulating layer, and the line pattern is used to form the wiring line 121.
  • the depth of the line pattern can also be made consistent with the depth of the coil window, but when the inductor 122 is set, since the thickness of the inductor 122 is less than the thickness of the wiring line 121, there is still space in the coil window located on the upper side of the inductor 122, and the space can be filled with insulating material.
  • the inductor coil 122 since the thickness of the inductor coil 122 is very thin, there is no need to open a coil window in the insulating layer, so the inductor coil 122 can be directly arranged on the first surface of the insulating layer.
  • the inductor coil 122 can be arranged on the first surface of the insulating layer in an attached manner, and in this case, the inductor coil 122 is arranged after the wiring line 121 corresponding to the insulating layer is formed.
  • the insulator 11 wraps the magnetic film layer 13, and the magnetic film layer 13 can also be arranged in any insulating layer or between any two insulating layers during the formation of the rewiring structure 1.
  • the extension plane of the magnetic film layer 13 and the extension plane of the patterned metal layer 12 in the corresponding insulating layer are located in the same plane.
  • the magnetic film layer 13 can be set simultaneously with the patterned metal layer 12 at the corresponding position.
  • a thin film window is set on the insulating layer at the same time.
  • the magnetic film layer 13 is set in the thin film window at the same time.
  • the magnetic film layer 13 since the thickness of the magnetic film layer 13 is very thin, there is no need to open a film window in the insulating layer, and therefore, the magnetic film layer 13 can be directly disposed on the first surface of the insulating layer. Specifically, the magnetic film layer 13 can be disposed on the first surface of the insulating layer in an attached manner, and in this case, the magnetic film layer 13 is disposed after the patterned metal layer 12 corresponding to the insulating layer is disposed.
  • the inductor coil 122 and the magnetic film layer 13 are both provided after the corresponding insulating layer is provided, and the inductor coil 122 and the magnetic film layer 13 may be separated by the insulating layer.
  • the inductor coil 122 is provided close to the magnetic film layer 13, and only one insulating layer is provided between the inductor coil 122 and the magnetic film layer 13.
  • the number of magnetic film layers 13 can be at least two, and the magnetic film layers 13 can be disposed on both the first surface 111 and the second surface 112 of the insulator 11.
  • the inductor 122 is relatively disposed between the two magnetic film layers 13, and the inductor 122 and the magnetic film layers 13 are arranged along the thickness direction of the rewiring structure 1.
  • the inductor coil 122 can be provided in one layer, two layers, or even multiple layers. When the inductor coil 122 is provided in two layers, the inductor circuit needs to be provided in the process of forming the two patterned metal layers 12. Similarly, when the inductor coil 122 is provided in multiple layers, the inductor circuit needs to be provided in the process of forming each corresponding patterned metal layer 12.
  • the inductor 122 When the inductor 122 is provided with two or more layers, the inductor 122 and the magnetic film layer 13 are alternately provided.
  • the alternate arrangement here can be that a layer of magnetic film layer 13 is provided on a layer of inductor 122, and then another layer of inductor 12 is formed on the magnetic film layer 13, and they are arranged along the thickness direction of the rewiring according to the above rule.
  • the inductor coil 122 is provided with two layers, the two layers of inductor coils 122 are parallel to each other, and the two layers of inductor coils 122 are respectively a first coil and a second coil arranged in the thickness direction of the rewiring structure 1.
  • the first coil and the second coil are separated by a part of the insulator 11.
  • the magnetic film layer 13 is also provided with two layers, and the two layers of inductor coils 122 are arranged between the two layers of magnetic film layers 13.
  • the two layers of inductor coils 122 and the two layers of magnetic film layers 13 may be interlaced with each other, so that one layer of inductor coil 122 is disposed oppositely between the two layers of magnetic film layers 13 , and one layer of magnetic film layer 13 is disposed oppositely between the two layers of inductor coils 122 .
  • two magnetic film layers 13 and one inductor 122 may be arranged in coordination.
  • the two magnetic film layers 13 may be arranged on opposite sides of the inductor 122 or on the same side of the inductor 122 .
  • three magnetic film layers 13 may be arranged to cooperate with two inductor coils 122 .
  • the three magnetic film layers 13 are arranged at intervals, and the two inductor coils 122 are inserted between the three magnetic film layers 13 .
  • the ratio between the thickness of the insulating layer where the inductor coil 122 is located and the thickness of the insulating layer where the magnetic film layer 13 is located is in the range of 0.5-2.
  • the packaging structure further comprises a metal bump 3, which is arranged on a side of the rewiring structure 1 away from the chip 2, and the metal bump 3 is electrically connected to the wiring line 121.
  • the side of the rewiring structure 1 away from the chip 2 may be provided with other electrical connection structures, such as other rewiring layers.
  • the inductor 122 can be configured to be electrically connected to the wiring line 121 of the patterned metal layer 12.
  • the inductor 122 needs to conduct current signals to the outside with the help of the wiring line 121, and the wiring line 121 finally conducts current signals to the outside with the help of the metal bump 3.
  • a separate inductor bump 4 may be provided to be electrically connected to the inductor coil 122.
  • the inductor bump 4 is provided on the second surface of the rewiring structure 1 and is electrically connected to the inductor coil 122.
  • the inductor bump 4 is used to lead out the inductor coil 122.
  • the inductor bump 4 and the metal bump 3 may be formed using the same structure and the same process.
  • the chip 2 is a bare chip.
  • the chip 2 is electrically connected to the rewiring structure 1 via a plurality of conductive pillars 5 .
  • the conductive pillars 5 are located between the rewiring structure and the chip 2 to achieve electrical connection between the chip 2 and the rewiring structure 1 .
  • the packaging structure further comprises a filling layer 6, which is filled in the area between the rewiring structure 1 and the chip 2, and the filling layer 6 surrounds the conductive pillar 5.
  • the filling layer 6 is a whole layer structure, which is filled between the plurality of chips 2 and the rewiring structure 1.
  • the filling layer 6 is also filled between two adjacent chips 2.
  • the filling layer 6 is provided to surround and protect the conductive pillars 5 between the chip 2 and the rewiring structure 1. In addition, the filling layer 6 can also strengthen the connection between the chip 2 and the rewiring structure 1.
  • the filling layer 6 may include or be made of an insulating material, such as a thermosetting adhesive.
  • the packaging structure further includes a first protective layer 7, which covers the chip 2 and protects the chip 2.
  • the first protective layer 7 may be a plastic sealing layer, and the material constituting the first protective layer 7 may be an epoxy resin adhesive prepared by a film sealing process.
  • the elastic modulus of the material constituting the first protective layer 7 is greater than the elastic modulus of the material constituting the filling layer.
  • the chip 2 includes a first chip 21 and a second chip 22 arranged in parallel on one side of the rewiring structure; the packaging structure further includes a bridge chip 8, a bridge chip protection layer 9 and a conductive bump 10.
  • the bridge chip 8 is provided on a side of the rewiring structure 1 away from the chip 2 and is electrically connected to the first chip 21 and the second chip 22 respectively.
  • the bridge chip protection layer 9 is disposed on the second surface 112 of the insulator 11 and covers the bridge chip 8.
  • the bridge chip protection layer 9 is provided with a protection layer through hole 90 penetrating the bridge chip protection layer 9.
  • the conductive bump 10 is disposed in the protective layer through hole 90 and electrically connected to the wiring line 121 .
  • the packaging structure further has a metal bump 3 , which is disposed on a side of the bridge chip protection layer 9 away from the insulator 11 , and is electrically connected to the conductive bump 10 .
  • the packaging structure further includes a bottom rewiring layer 2020, which is disposed on a side of the bridge chip protection layer 9 away from the insulator 11 and includes a bottom insulating layer 201 and a bottom metal layer 202 disposed in the bottom insulating layer 201;
  • the metal bumps 3 and the conductive bumps 10 are disposed opposite to each other on two sides of the bottom redistribution layer 2020 and are electrically connected through the bottom metal layer 202 .
  • the rewiring structure is formed on a side of the bonding layer away from the carrier substrate, wherein the rewiring structure comprises an insulator and a plurality of patterned metal layers embedded in the insulator, at least one of the patterned metal layers comprises a wiring line and an inductor line forming an inductor coil; the rewiring structure further comprises a magnetic film layer arranged on at least one side of the inductor coil in a thickness direction of the rewiring structure;
  • the carrier substrate and the bonding layer are removed.
  • packaging structure of the first embodiment of the present application is formed as follows:
  • S100 As shown in FIG. 3A , providing a carrier substrate 100 , and disposing a bonding layer 200 on a first surface of the carrier substrate 100 ;
  • the carrier substrate 100 may be a glass carrier or any suitable carrier applicable to the manufacturing method of the packaging structure; in a specific embodiment, the carrier substrate 100 is a silicon substrate, which is used to assist in setting the packaging structure and needs to be removed later;
  • a bonding layer 200 is arranged on the first surface of the carrier substrate 100.
  • the bonding layer 200 also serves as an auxiliary layer in the formation process of the rewiring structure 1 and needs to be removed after the packaging is completed; the bonding layer 200 can be an adhesive layer.
  • a rewiring structure 1 is arranged on the surface of the bonding layer 200 away from the carrier substrate 100, and an inductor 122 is formed in the rewiring structure during the process of the rewiring structure 1 being arranged; at the same time, a magnetic film layer 13 is arranged in the rewiring structure 1 during the process of forming the rewiring structure 1; wherein the magnetic film layer 13 is arranged on one side of the inductor 122 in the thickness direction;
  • the magnetic film layer 13 can be arranged in the rewiring structure 1 when the rewiring structure 1 is formed, and the inductor 122 can be arranged in the rewiring structure 1 when the rewiring structure 1 is formed; the magnetic film layer 13 can be formed simultaneously with the patterned metal layer 12 by electroplating;
  • the chip 2 is electrically connected to the rewiring structure 1 through the conductive pillar 5; in the embodiment of the present invention, the chip 2 is combined with the rewiring structure 1 by flip-chip packaging, and the conductive pillar 5 can be a copper pillar, which is arranged on the first surface of the rewiring structure 1 and faces one side of the chip 2; the conductive pillar 5 is opposite to the patterned metal layer 12 in the rewiring structure 1 and is electrically connected;
  • the difference from the above embodiment is that the rewiring structure 1 is disposed on the side of the bonding layer 200 away from the carrier substrate 100, and the inductor 122 is disposed in the process of disposing the rewiring structure 1 so that the inductor 122 is disposed in the rewiring structure 1, specifically, the inductor 122 is disposed in the insulator 11; at the same time, after the rewiring structure 1 is disposed, the magnetic film layer 13 is disposed so that the magnetic film layer 13 is disposed on the first surface of the rewiring structure 1 away from the bonding layer 200, specifically, the magnetic film layer 13 is disposed on the first surface of the insulator 11;
  • the magnetic film layer 13 described in the above embodiment is formed after the rewiring structure 1 is formed; the magnetic film layer 13 can be directly attached to the first surface of the rewiring structure 1 by means of attachment, and can also be provided by means of electroplating. Before electroplating, an insulating layer can be provided on the first surface of the rewiring structure 1 away from the bonding layer 200, and a thin film window can be provided on the insulating layer, and the magnetic film layer 13 is formed by electroplating in the thin film window;
  • a magnetic film layer 13 may be provided on the bonding layer 200 before the rewiring structure 1 is provided; specifically, the rewiring structure 1 is provided on the first surface of the bonding layer 200 away from the carrier substrate 100, and in the process of providing the rewiring structure 1, an inductor 122 is provided so that the inductor 122 is provided in the rewiring structure 1, specifically, the inductor 122 is provided in the insulator 11; at the same time, before providing the rewiring structure 1, a magnetic film layer 13 is provided on the first surface of the bonding layer 200 away from the carrier substrate 100; similarly, the magnetic film layer 13 may be directly attached to the first surface of the bonding layer 200 by means of attachment, and of course, may be provided by means of electroplating, and before electroplating, an insulating layer may be provided on the first surface of the bonding layer 200 away from the carrier substrate, and a thin film window may be provided in the insulating layer, and the magnetic film layer 13 may be formed by electroplating in the
  • insulating layers are sequentially stacked on the bonding layer 200 , a circuit pattern is etched in a target area of each insulating layer, a patterned metal layer 12 is disposed between adjacent insulating layers, and a portion of the patterned metal layer 12 is disposed within the circuit pattern to be electrically connected to the adjacent patterned metal layer 12 ;
  • a circuit pattern is provided on a certain insulating layer
  • a coil window is provided on the insulating layer
  • a patterned metal layer 12 is provided in the circuit pattern
  • an inductor coil 122 is provided in the coil window; it should be noted that both the circuit pattern and the coil window penetrate the insulating layer in a direction perpendicular to the extension plane of the insulating layer, and both the circuit pattern and the coil window can be formed by an etching process.
  • the magnetic film layer 13 is disposed simultaneously with the patterned metal layer 12 in a certain insulating layer located above the inductor 122 ; or the magnetic film layer 13 is disposed simultaneously with the patterned metal layer 12 in a certain insulating layer located below the inductor 122 .
  • the process also includes setting a filling layer 6 between the chip 2 and the rewiring structure 1; setting a first protective layer 7 on the surface of the chip 2 facing away from the rewiring structure 1 and on the first surface 111 of the rewiring structure 1, and the first protective layer 7 covers the chip 2 and the rewiring structure 1.
  • the method for forming the packaging structure in the second embodiment includes the following steps:
  • S100 As shown in FIG. 4A , providing a carrier substrate 100 , and disposing a bonding layer 200 on a first surface of the carrier substrate 100 ;
  • a bottom insulating layer 201 is provided on the first surface of the bonding layer 200, the bottom insulating layer 201 is etched to form a circuit pattern, a bottom metal layer 202 is provided in the circuit pattern to form a bottom rewiring layer 20; a conductive bump 10 is provided on the bottom metal layer 202, and the conductive bump 10 protrudes out of the first surface of the bottom insulating layer; the conductive bump 10 serves to electrically connect the rewiring structure 1 and the bottom rewiring layer 20; the conductive bump 10 can be provided on the corresponding bottom metal layer 202 by welding, and of course the conductive bump 10 can also be provided by conventional electroplating.
  • the bottom insulating layer 201 is formed by a layer of insulating material, and the bottom metal layer 202 is stacked by a layer of metal layers; of course, in other embodiments, the bottom insulating layer 201 can also be formed by stacking multiple insulating layers, and correspondingly, the bottom metal layer 202 is also formed by stacking multiple metal layers; it can be understood that the number of insulating layers stacked in the bottom rewiring layer 20 can be set according to actual needs;
  • a bridge chip 8 is disposed on the bottom insulating layer, wherein the pads of the bridge chip 8 are disposed in a direction away from the bottom insulating layer 201 ; and chip bumps are disposed on the pads of the bridge chip 8 ; the bridge chip 8 can be attached to the bottom insulating layer 201 by using colloid;
  • a bridge chip protection layer 9 is provided on the first surface of the bridge chip 8 and the bottom rewiring layer 20, the bridge chip protection layer 9 covers the bridge chip 8, and the bridge chip protection layer 9 covers the bottom rewiring layer 20, and a portion of the bridge chip protection layer 9 is removed to allow the chip bumps and the conductive bumps 10 to be
  • the first surface of the bridge chip protection layer 9 is exposed outward; specifically, a grinding process can be used to remove the top surface of the bridge chip protection layer 9 so that the chip bumps and the conductive bumps 10 are flush and exposed outward at the same time; the bridge chip protection layer 9 can be a plastic packaging layer, and the specific structure and material are consistent with the first protection layer 7, which will not be repeated here.
  • an insulating layer is firstly provided on the first surface of the bridge chip protection layer 9; the insulating layer in the target area is etched to form a circuit pattern on the insulating layer; a patterned metal layer 12 is provided in the circuit pattern and part of the patterned metal layer 12 covers the first surface of the insulating layer, and multiple insulating layers are stacked and multiple metal layers are staggered to form the rewiring structure 1;
  • a circuit pattern is provided on a certain insulating layer, and a coil opening is provided on the insulating layer at the same time, and a wiring line 121 is provided in the circuit pattern and an inductor coil 122 is provided in the coil opening;
  • the magnetic film layer 13 is provided at the same time; or when the patterned metal layer 12 in a certain insulating layer on the lower side of the inductor 122 is provided, the magnetic film layer 13 is provided at the same time;
  • an insulating layer is set on the first surface of the bridge chip protection layer 9.
  • a thin film window is also opened on the insulating layer;
  • a magnetic thin film layer 13 is also set in the thin film window, and then the inductor 122 is set in the above manner.
  • the magnetic thin film layer 13 is set on the upper side of the inductor 122. The two layers of magnetic thin film layers 13 are set to enhance the stability of the inductor 122.
  • a filling layer 6 is provided between the chip 2 and the rewiring structure 1 ;
  • a first protective layer 7 is provided on the first surface of the rewiring structure 1 to plastic-encapsulate the chip 2 and the rewiring structure 1 ;
  • S900 As shown in FIG. 4G , the carrier substrate 100 and the bonding layer 200 are removed, and a metal bump 3 is disposed on the second surface of the bottom insulating layer, and the metal bump 3 is electrically connected to the bottom metal layer 202 .

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Abstract

Disclosed in the present invention are a packaging structure and a forming method. The packaging structure comprises: a redistribution structure and a chip; the redistribution structure is provided with an insulator and a plurality of patterned metal layers embedded inside the insulator; at least one patterned metal layer is provided with a wiring line and an inductance line forming an inductance coil; the redistribution structure further comprises magnetic thin film layers; in the thickness direction of the redistribution structure, the magnetic thin film layers are arranged on at least one side of the inductance coils; and the chip is arranged on one side of the redistribution structure in the thickness direction and is electrically connected to the wiring lines. The embodiments of the present invention combine the inductance coils with the redistribution process to package the inductance coils inside the insulator of the redistribution structure, so as to achieve integration of the inductance coils and the chip packaging structure, and provide the magnetic thin film layers to eliminate performance reduction of the inductance coils after the integration, thus improving the integration level of the packaging structure, and reducing the size of the packaging structure after packaging.

Description

封装结构及形成方法Packaging structure and forming method 技术领域Technical Field

本发明涉及芯片封装技术领域,特别是封装结构及形成方法。The present invention relates to the technical field of chip packaging, in particular to a packaging structure and a forming method.

背景技术Background Art

随着先进封装技术的不断演进,chiplet(芯粒)封装越来越得到广泛的应用。通过chiplet技术,可以把异质或者同质芯片进行组合,最终实现功能叠加或者微系统集成。With the continuous evolution of advanced packaging technology, chiplet packaging is becoming more and more widely used. Through chiplet technology, heterogeneous or homogeneous chips can be combined to ultimately achieve functional superposition or microsystem integration.

在chiplet封装时,电感类器件一般作为分立器件贴附在基板或印刷电路板上,这种电感类器件的安装方式浪费封装面积,使封装后的封装结构的尺寸增大。During chiplet packaging, inductor devices are generally attached to a substrate or a printed circuit board as discrete devices. This installation method of inductor devices wastes packaging area and increases the size of the package structure after packaging.

发明内容Summary of the invention

本发明的目的是提供一种封装结构,以解决现有技术中的不足,它能够在不影响电感线圈性能的前提下将电感线圈与芯片的再布线工艺进行结合,从而提升了芯片封装结构的集成度,减少了封装结构的整体尺寸。The purpose of the present invention is to provide a packaging structure to solve the deficiencies in the prior art. It can combine the inductor coil with the chip rewiring process without affecting the performance of the inductor coil, thereby improving the integration of the chip packaging structure and reducing the overall size of the packaging structure.

本发明提供的封装结构,包括:再布线结构,具有绝缘体和嵌设于绝缘体内的若干图案化金属层,至少一所述图案化金属层具有布线线路和形成电感线圈的电感线路;所述再布线结构还包括磁性薄膜层,在再布线结构厚度方向上,所述磁性薄膜层设置于电感线圈的至少一侧;The packaging structure provided by the present invention comprises: a rewiring structure having an insulator and a plurality of patterned metal layers embedded in the insulator, at least one of the patterned metal layers having a wiring circuit and an inductor circuit forming an inductor coil; the rewiring structure further comprises a magnetic film layer, and in the thickness direction of the rewiring structure, the magnetic film layer is arranged on at least one side of the inductor coil;

芯片,设置于所述再布线结构沿厚度方向的一侧并与所述布线线路电性连接。The chip is arranged on one side of the rewiring structure along the thickness direction and is electrically connected to the wiring line.

进一步的,在再布线结构的厚度方向上,所述电感线圈的位置与所述磁性薄膜层位置相对。Furthermore, in the thickness direction of the rewiring structure, the position of the inductor coil is opposite to the position of the magnetic film layer.

进一步的,所述磁性薄膜层嵌设于所述绝缘体内,所述磁性薄膜层与所述电感线圈之间通过部分所述绝缘体分隔。Furthermore, the magnetic film layer is embedded in the insulator, and the magnetic film layer and the inductor coil are separated by a portion of the insulator.

进一步的,所述绝缘体具有背向设置的第一表面和第二表面;所述磁性薄膜层设置于所述第一表面、所述第二表面中的至少一个。Furthermore, the insulator has a first surface and a second surface disposed in opposite directions; the magnetic film layer is disposed on at least one of the first surface and the second surface.

进一步的,所述磁性薄膜层设置有至少两层,所述电感线圈设置在两层所述磁性薄膜层之间。Furthermore, the magnetic film layer is provided with at least two layers, and the inductor coil is provided between the two magnetic film layers.

进一步的,所述电感线圈也设置有至少两层;Furthermore, the inductor coil is also provided with at least two layers;

在再布线结构厚度方向上,所述电感线圈与所述磁性薄膜层交替设置。In the thickness direction of the rewiring structure, the inductor coils and the magnetic film layers are arranged alternately.

进一步的,所述磁性薄膜层为含铁金属薄膜层、或含镍金属薄膜层、或含钴金属薄膜层、或含铁镍合金薄膜层、或含铁钴合金薄膜层、或含镍钴合金薄膜层、或含铁镍钴合金薄膜层中的一种或多种的叠加。 Furthermore, the magnetic film layer is a superposition of one or more of an iron-containing metal film layer, a nickel-containing metal film layer, a cobalt-containing metal film layer, an iron-nickel alloy film layer, an iron-cobalt alloy film layer, a nickel-cobalt alloy film layer, or an iron-nickel-cobalt alloy film layer.

进一步的,所述封装结构还具有金属凸块,所述金属凸块设置在所述再布线结构背离所述芯片的一侧,所述金属凸块与所述布线线路电性连接;Furthermore, the packaging structure further comprises a metal bump, the metal bump is arranged on a side of the rewiring structure away from the chip, and the metal bump is electrically connected to the wiring line;

所述封装结构还具有电感凸块,所述电感凸块设置在所述再布线结构背离所述芯片的一侧,所述电感凸块与所述电感线圈电性连接;所述电感线圈与所述布线线路之间通过部分所述绝缘体分隔。The packaging structure also has an inductor bump, which is arranged on a side of the rewiring structure away from the chip, and is electrically connected to the inductor coil; the inductor coil and the wiring line are separated by a portion of the insulator.

进一步的,所述芯片包括并列设置在所述再布线结构一侧的第一芯片和第二芯片;Further, the chip includes a first chip and a second chip arranged in parallel on one side of the rewiring structure;

所述封装结构还包括:The packaging structure further includes:

桥接芯片,设置在所述再布线结构背离所述芯片的一侧并分别与所述第一芯片、所述第二芯片电性连接;A bridge chip, arranged on a side of the rewiring structure away from the chip and electrically connected to the first chip and the second chip respectively;

桥接芯片保护层,设置在所述绝缘体的第二表面并覆盖所述桥接芯片,所述桥接芯片保护层上设置有贯穿所述桥接芯片保护层的保护层通孔;A bridge chip protection layer is disposed on the second surface of the insulator and covers the bridge chip, and a protection layer through hole penetrating the bridge chip protection layer is disposed on the bridge chip protection layer;

导电凸块,设置在所述保护层通孔内并电性连接所述布线线路。A conductive bump is disposed in the through hole of the protection layer and electrically connected to the wiring line.

进一步的,所述封装结构还具有金属凸块,所述金属凸块设置在所述桥接芯片保护层背离所述绝缘体的一侧,所述金属凸块与所述导电凸块电性连接。Furthermore, the packaging structure further comprises a metal bump, the metal bump is arranged on a side of the bridge chip protection layer away from the insulator, and the metal bump is electrically connected to the conductive bump.

进一步的,所述封装结构还包括:Furthermore, the packaging structure further includes:

底部再布线层,设置在所述桥接芯片保护层背离所述绝缘体的一侧,并具有底绝缘层和设置在底绝缘层内的底金属层;A bottom rewiring layer is arranged on a side of the bridge chip protection layer away from the insulator and comprises a bottom insulating layer and a bottom metal layer arranged in the bottom insulating layer;

所述金属凸块与所述导电凸块相对设置在所述底部再布线层的两侧并通过所述底金属层电性连接。The metal bumps and the conductive bumps are arranged opposite to each other at two sides of the bottom redistribution layer and are electrically connected through the bottom metal layer.

本发明另一实施例还公开了一种所述的封装结构的形成方法,包括如下步骤:Another embodiment of the present invention further discloses a method for forming the packaging structure, comprising the following steps:

提供承载基板,并在所述承载基板的一侧设置结合层;Providing a carrier substrate, and disposing a bonding layer on one side of the carrier substrate;

在所述结合层背离所述承载基板的一侧形成所述再布线结构,其中,所述再布线结构具有绝缘体和嵌设于绝缘体内的若干图案化金属层,至少一所述图案化金属层包括布线线路和形成电感线圈的电感线路;The rewiring structure is formed on a side of the bonding layer away from the carrier substrate, wherein the rewiring structure comprises an insulator and a plurality of patterned metal layers embedded in the insulator, and at least one of the patterned metal layers comprises a wiring circuit and an inductor circuit forming an inductor coil;

将芯片与所述布线线路电性连接;electrically connecting the chip to the wiring line;

去除所述承载基板及所述结合层。The carrier substrate and the bonding layer are removed.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

图1是本发明第一种类型的封装结构的结构示意图;FIG1 is a schematic structural diagram of a first type of packaging structure of the present invention;

图2是本发明第二种类型的封装结构的结构示意图;FIG2 is a schematic structural diagram of a second type of packaging structure of the present invention;

图3A-3E是本发明第一种类型的封装结构的形成过程示意图;3A-3E are schematic diagrams showing the formation process of the first type of packaging structure of the present invention;

图4A-4G是本发明第二种类型的封装结构的形成过程示意图; 4A-4G are schematic diagrams showing the formation process of the second type of packaging structure of the present invention;

附图标记说明:附图标记说明:1-再布线结构,11-绝缘体,111-第一表面,112-第二表面,12-图案化金属层,121-布线线路,122-电感线圈,123-线圈连接部,13-磁性薄膜层,Description of reference numerals: Description of reference numerals: 1-rewiring structure, 11-insulator, 111-first surface, 112-second surface, 12-patterned metal layer, 121-wiring line, 122-inductor coil, 123-coil connecting portion, 13-magnetic film layer,

2-芯片,21-第一芯片,22-第二芯片,2-chip, 21-first chip, 22-second chip,

3-金属凸块,4-电感凸块,5-导电柱,6-填充层,7-第一保护层,8-桥接芯片,9-桥接芯片保护层,90-保护层通孔,10-导电凸块,20-底部再布线层,201-底绝缘层,202-底金属层,3-metal bump, 4-inductor bump, 5-conductive column, 6-filling layer, 7-first protective layer, 8-bridge chip, 9-bridge chip protective layer, 90-protective layer through hole, 10-conductive bump, 20-bottom rewiring layer, 201-bottom insulation layer, 202-bottom metal layer,

100-承载基板,200-结合层。100-carrying substrate, 200-bonding layer.

具体实施方式DETAILED DESCRIPTION

以下的公开内容提供许多不同的实施例或范例以实施本案的不同特征。以下描述具体的构件及其排列方式的实施例以阐述本公开。当然,这些实施例仅作为范例,而不该以此限定本公开的范围。对于空间相关用语,例如“上”、“下”及类似的用语,是为了便于描述图示中一个元件或特征与另一个元件或特征之间的关系。除了在附图中绘示的方位外,这些空间相关用语意欲包含使用中或操作中的装置的不同方位。设备可能被转向不同方位(旋转90度或其他方位),则在此使用的空间相关词也可依此相同解释。The following disclosure provides many different embodiments or examples to implement different features of the present invention. The following describes embodiments of specific components and their arrangements to illustrate the present invention. Of course, these embodiments are only examples and should not be used to limit the scope of the present invention. For spatially related terms, such as "upper", "lower" and similar terms, it is to facilitate the description of the relationship between one element or feature and another element or feature in the diagram. In addition to the orientations shown in the accompanying drawings, these spatially related terms are intended to include different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related words used here may also be interpreted in the same way.

本发明公开了一种封装结构,该封装结构能够将电感类器件的被动元件集成在封装结构的再布线结构上,从而实现了电感类器件与芯片封装结构的集成化设置,相比于,现有技术中将电感类器件贴附在封装基板外表面的封装方案,使整体封装后的尺寸减小,在本发明实施例中电感类器件包括电感线圈。The present invention discloses a packaging structure, which can integrate the passive components of an inductor device on a rewiring structure of the packaging structure, thereby realizing an integrated arrangement of the inductor device and a chip packaging structure. Compared with the packaging solution in the prior art in which the inductor device is attached to the outer surface of a packaging substrate, the size of the entire package is reduced. In an embodiment of the present invention, the inductor device includes an inductor coil.

具体的,图1为本发明第一种实施例的封装结构在封装完成后的完整结构。图2为本发明第二种实施例的封装结构在封装完成后的完整结构。如图3A-3E所示是本发明第一种实施例公开的封装结构形成的流程结构示意图。如图4A-4G所示是本发明第二种实施例公开的封装结构形成的流程结构示意图。其中,第二种实施例中的封装结构为堆叠式芯片封装结构。Specifically, FIG. 1 is a complete structure of the packaging structure of the first embodiment of the present invention after packaging is completed. FIG. 2 is a complete structure of the packaging structure of the second embodiment of the present invention after packaging is completed. As shown in FIGS. 3A-3E, it is a schematic diagram of the process structure formed by the packaging structure disclosed in the first embodiment of the present invention. As shown in FIGS. 4A-4G, it is a schematic diagram of the process structure formed by the packaging structure disclosed in the second embodiment of the present invention. Among them, the packaging structure in the second embodiment is a stacked chip packaging structure.

如图1所示,在本发明第一种实施例中公开的封装结构包括再布线结构1和与再布线结构1电性连接的芯片2;As shown in FIG. 1 , the packaging structure disclosed in the first embodiment of the present invention includes a rewiring structure 1 and a chip 2 electrically connected to the rewiring structure 1 ;

所述再布线结构1包括绝缘体11、嵌入在所述绝缘体11内的若干图案化金属层12;若干图案化金属层12沿再布线结构1的厚度方向排列并相互电性连接。可以理解的是,不同的图案化金属层12在不同的高度延伸设置,相互电性连接的图案化金属层12可以是上下相邻的两层图案化金属层12电性连接,也可以是跨层的两层图案化金属 层12实现电性连接。再布线结构1中的不同图案化金属层12的具体连接方式及设计方式根据实际需要进行,在此不做过多限制。The rewiring structure 1 includes an insulator 11 and a plurality of patterned metal layers 12 embedded in the insulator 11; the plurality of patterned metal layers 12 are arranged along the thickness direction of the rewiring structure 1 and are electrically connected to each other. It is understandable that different patterned metal layers 12 are extended at different heights, and the patterned metal layers 12 electrically connected to each other can be two adjacent patterned metal layers 12 electrically connected, or two cross-layer patterned metal layers 12 electrically connected. The layer 12 realizes electrical connection. The specific connection method and design method of the different patterned metal layers 12 in the rewiring structure 1 are carried out according to actual needs, and no excessive restrictions are made here.

具体实施例中至少一图案化金属层12具有布线线路121和形成电感线圈122的电感线路。在若干图案化金属层12中部分图案化金属层12中形成有电感线路,未设置电感线路的图案化金属层12则整层形成布线线路。In the specific embodiment, at least one patterned metal layer 12 has a wiring circuit 121 and an inductor circuit forming an inductor coil 122. In the patterned metal layers 12, some patterned metal layers 12 have inductor circuits formed therein, and the patterned metal layers 12 without inductor circuits have wiring circuits formed therein.

不同的图案化金属层12的布线线路121之间相互电性连接,且布线线路121与芯片2的焊盘电性连接。所述芯片2的数量可以设置有多个,多个芯片并列排布并位于再布线结构1的同侧。The wiring lines 121 of different patterned metal layers 12 are electrically connected to each other, and the wiring lines 121 are electrically connected to the pads of the chip 2. There can be multiple chips 2, which are arranged in parallel and located on the same side of the rewiring structure 1.

所述再布线结构1还包括磁性薄膜层13,在再布线结构1厚度方向上,所述磁性薄膜层13设置于电感线圈122的至少一侧,以使至少部分磁性薄膜层13与至少部分电感线圈122在再布线结构1的厚度方向上位置相对;The rewiring structure 1 further includes a magnetic film layer 13, which is disposed on at least one side of the inductor 122 in the thickness direction of the rewiring structure 1, so that at least a portion of the magnetic film layer 13 and at least a portion of the inductor 122 are opposite in the thickness direction of the rewiring structure 1;

磁性薄膜层13可以在所述电感线圈122的一侧进行设置,当然磁性薄膜层13也可以在电感线圈122的两侧同时设置。The magnetic film layer 13 may be disposed on one side of the inductor 122 . Of course, the magnetic film layer 13 may also be disposed on both sides of the inductor 122 at the same time.

具体实施例中电感线圈122设置成与图案化金属层12同时成型,使电感线圈122作为图案化金属层12的一部分,提高了电感线圈与再布线结构1的集成度。In a specific embodiment, the inductor coil 122 is configured to be formed simultaneously with the patterned metal layer 12 , so that the inductor coil 122 is a part of the patterned metal layer 12 , thereby improving the integration of the inductor coil and the rewiring structure 1 .

本发明的实施例将电感线圈122与再布线工艺结合,使电感线圈122封装在再布线结构1的绝缘体11内,从而实现了电感线圈122与芯片封装结构的集成,通过在电感线圈122的一侧设置磁性薄膜层13实现对电感线圈122的信号放大,从而在不影响电感线圈122性能的前提下,将电感线圈122集成在再布线结构1,消除了电感线圈122在集成设置后性能的减弱,提高了封装结构的集成度,减少了封装后封装结构的尺寸。The embodiment of the present invention combines the inductor coil 122 with the rewiring process so that the inductor coil 122 is encapsulated in the insulator 11 of the rewiring structure 1, thereby realizing the integration of the inductor coil 122 and the chip packaging structure. By setting a magnetic film layer 13 on one side of the inductor coil 122, the signal of the inductor coil 122 is amplified, so that the inductor coil 122 is integrated in the rewiring structure 1 without affecting the performance of the inductor coil 122, thereby eliminating the weakening of the performance of the inductor coil 122 after the integrated setting, improving the integration of the packaging structure, and reducing the size of the packaging structure after packaging.

相比于现有技术中电感线圈122作为独立的器件装配到封装基板上,本发明实施例将电感线圈122与再布线结构进行集成设置,提高了器件的集成度。Compared with the prior art in which the inductor 122 is assembled on the packaging substrate as an independent device, the embodiment of the present invention integrates the inductor 122 with the rewiring structure, thereby improving the integration of the device.

在具体实施例中,在再布线结构1的厚度方向上,所述电感线圈122的位置与所述磁性薄膜层13位置相对。磁性薄膜层13与电感线圈122位置相对后能够对电感线圈122的信号起到放大作用,从而增强电感线圈122的工作效果。In a specific embodiment, in the thickness direction of the rewiring structure 1, the position of the inductor 122 is opposite to the position of the magnetic film layer 13. After the magnetic film layer 13 is opposite to the inductor 122, it can amplify the signal of the inductor 122, thereby enhancing the working effect of the inductor 122.

在具体实施例中,所述磁性薄膜层13位于电感线圈122的正上方或者正下方;在再布线结构1的厚度方向上,所述磁性薄膜层13朝电感线圈122所在平面的投影图案完全覆盖所述电感线圈122所在的位置。In a specific embodiment, the magnetic film layer 13 is located directly above or below the inductor 122; in the thickness direction of the rewiring structure 1, the projection pattern of the magnetic film layer 13 toward the plane where the inductor 122 is located completely covers the position of the inductor 122.

具体的,所述磁性薄膜层13的尺寸可以设置成与所述电感线圈122的尺寸相同,此时,所述磁性薄膜层13与所述电感线圈122在再布线结构1的厚度方向上位置完全相对。 Specifically, the size of the magnetic film layer 13 can be set to be the same as the size of the inductor coil 122 . In this case, the magnetic film layer 13 and the inductor coil 122 are completely opposite to each other in the thickness direction of the rewiring structure 1 .

当然,所述磁性薄膜层13的尺寸也可以设置成大于电感线圈122的尺寸,这样结构的设置能更好的实现磁性薄膜层13的作用,从而在再布线结构1的厚度方向上,实现磁性薄膜层13对电感线圈122信号的完全覆盖,使每一处电感线圈122都有相应的磁性薄膜层13与之相对,以使磁性薄膜层13对相应位置的电感线圈122产生作用。Of course, the size of the magnetic film layer 13 can also be set to be larger than the size of the inductor 122. Such a structural setting can better realize the function of the magnetic film layer 13, so that in the thickness direction of the rewiring structure 1, the magnetic film layer 13 can completely cover the signal of the inductor 122, so that each inductor 122 has a corresponding magnetic film layer 13 opposite to it, so that the magnetic film layer 13 can have an effect on the inductor 122 at the corresponding position.

在具体实施例中,所述磁性薄膜层13整体呈片状,并垂直于再布线结构1厚度方向设置,所述电感线圈122也呈片状,并垂直于再布线结构1的厚度方向设置,所述磁性薄膜层13所在平面与所述电感线圈122所在平面平行设置。在其他实施例中也可以使磁性薄膜层13延展平面设置成与电感线圈122延展平面斜交。In a specific embodiment, the magnetic film layer 13 is in a sheet shape as a whole and is arranged perpendicular to the thickness direction of the rewiring structure 1. The inductor coil 122 is also in a sheet shape and is arranged perpendicular to the thickness direction of the rewiring structure 1. The plane where the magnetic film layer 13 is located is arranged parallel to the plane where the inductor coil 122 is located. In other embodiments, the extended plane of the magnetic film layer 13 can also be arranged to be oblique to the extended plane of the inductor coil 122.

在其他实施例中,所述磁性薄膜层13与所述电感线圈122在再布线结构1的厚度方向上可以部分位置相对。沿再布线结构1的厚度方向,磁性薄膜层13朝电感线圈122所在平面的投影图案部分落入到电感线圈122所在位置。在这种情况下磁性薄膜层13只是部分位置起到放大电感线圈122信号的作用。In other embodiments, the magnetic film layer 13 and the inductor coil 122 may partially face each other in the thickness direction of the rewiring structure 1. Along the thickness direction of the rewiring structure 1, the projection pattern of the magnetic film layer 13 toward the plane where the inductor coil 122 is located partially falls into the location where the inductor coil 122 is located. In this case, only a portion of the magnetic film layer 13 plays a role in amplifying the signal of the inductor coil 122.

在一种实施例中所述磁性薄膜层13嵌设于所述绝缘体11内,绝缘体11包裹所述磁性薄膜层13,且所述磁性薄膜层13与所述电感线圈122之间通过部分所述绝缘体11分隔。In one embodiment, the magnetic film layer 13 is embedded in the insulator 11 , the insulator 11 wraps the magnetic film layer 13 , and the magnetic film layer 13 and the inductor 122 are separated by a portion of the insulator 11 .

由于电感线圈122和磁性薄膜层13都嵌入在绝缘体11内,为了避免磁性薄膜层13与电感线圈122之间产生短路,所述磁性薄膜层13不能直接设置在电感线圈122的表面,两者之间需要有其他部件分隔以形成间隔设置。Since the inductor 122 and the magnetic film layer 13 are both embedded in the insulator 11, in order to avoid a short circuit between the magnetic film layer 13 and the inductor 122, the magnetic film layer 13 cannot be directly set on the surface of the inductor 122, and other components are required to separate the two to form a spacing setting.

对于非堆叠式封装结构如图1所示,一般形成有一层再布线结构1,此时,对电感线圈122形成包裹的绝缘体11同时对所述磁性薄膜层13形成包裹,也就是电感线圈122和磁性薄膜层13设置于相同的绝缘体11内。For the non-stacked packaging structure as shown in FIG1 , a rewiring structure 1 is generally formed. At this time, the insulator 11 that wraps the inductor 122 also wraps the magnetic film layer 13 , that is, the inductor 122 and the magnetic film layer 13 are arranged in the same insulator 11 .

对于堆叠式封装结构,如图2所示,一般由多层芯片堆叠,此时设置有多层再布线结构1,相应的,绝缘体11也设置有多个。由于设置有多个绝缘体11,包裹所以电感线圈122的绝缘体11可以同时包裹所述磁性薄膜层13(图2所示),当然也可以使包裹电感线圈122的绝缘体11与包裹磁性薄膜层13的绝缘体11是两个不同的绝缘体(图未示),也就是电感线圈122和磁性薄膜层13可以设置于不同的再布线结构1。For the stacked packaging structure, as shown in FIG2 , it is generally stacked with multiple layers of chips, and a multi-layer rewiring structure 1 is provided at this time, and accordingly, a plurality of insulators 11 are also provided. Since a plurality of insulators 11 are provided, the insulator 11 wrapping the inductor 122 can also wrap the magnetic film layer 13 (as shown in FIG2 ). Of course, the insulator 11 wrapping the inductor 122 and the insulator 11 wrapping the magnetic film layer 13 can also be two different insulators (not shown), that is, the inductor 122 and the magnetic film layer 13 can be provided in different rewiring structures 1.

为了更好的提升电感线圈122的性能,磁性薄膜层13尽可能的设置在靠近电感线圈122的位置,也就是即便设置有多个再布线结构,包裹电感线圈122的绝缘体11与包裹磁性薄膜层13的绝缘体11尽可能的设置为同一绝缘体11。In order to better improve the performance of the inductor 122, the magnetic film layer 13 is arranged as close to the inductor 122 as possible. That is, even if multiple rewiring structures are provided, the insulator 11 wrapping the inductor 122 and the insulator 11 wrapping the magnetic film layer 13 are arranged as the same insulator 11 as possible.

无论电感线圈122和磁性薄膜层13是否设置在同一绝缘体11内,都有部分所述磁性薄膜层13与部分所述电感线圈122在再布线结构1的厚度方向上位置相对,从而使磁性薄膜层13与电感线圈122形成配合。 Regardless of whether the inductor 122 and the magnetic film layer 13 are arranged in the same insulator 11 , part of the magnetic film layer 13 and part of the inductor 122 are positioned opposite to each other in the thickness direction of the rewiring structure 1 , so that the magnetic film layer 13 and the inductor 122 are matched.

在具体实施例中,当磁性薄膜层13与电感线圈122设置在同一再布线结构1的时候,磁性薄膜层13与电感线圈122可以通过部分绝缘体分隔。在其他实施例中当磁性薄膜层13与电感线圈122设置在不同的再布线结构的时候磁性薄膜层13与电感线圈122之间还可以通过绝缘体、塑封层等进行分隔。In a specific embodiment, when the magnetic film layer 13 and the inductor 122 are arranged in the same rewiring structure 1, the magnetic film layer 13 and the inductor 122 may be separated by a portion of an insulator. In other embodiments, when the magnetic film layer 13 and the inductor 122 are arranged in different rewiring structures, the magnetic film layer 13 and the inductor 122 may also be separated by an insulator, a plastic layer, etc.

在另一种实施例中所述绝缘体11具有背向设置的第一表面111和第二表面112;所述磁性薄膜层13设置于所述第一表面111、所述第二表面112中的至少一个。In another embodiment, the insulator 11 has a first surface 111 and a second surface 112 disposed in opposite directions; the magnetic film layer 13 is disposed on at least one of the first surface 111 and the second surface 112 .

在所述磁性薄膜层13嵌设于所述绝缘体11内的时候,磁性薄膜层13可以与一所述图案化金属层12同时形成。在所述磁性薄膜层13设置在所述绝缘体11的表面的时候,磁性薄膜层13可以采用贴附的方式形成。When the magnetic film layer 13 is embedded in the insulator 11, the magnetic film layer 13 can be formed simultaneously with the patterned metal layer 12. When the magnetic film layer 13 is disposed on the surface of the insulator 11, the magnetic film layer 13 can be formed by attaching.

所述磁性薄膜层13可以为金属软磁材料,在具体实施例中所述磁性薄膜层13为含铁钴镍等元素之一的金属薄膜层,具体为含铁金属薄膜、或含镍金属薄膜、或含钴金属薄膜、或含铁镍合金薄膜、或铁钴合金薄膜、或含镍钴合金薄膜、或含铁镍钴合金薄膜。The magnetic film layer 13 can be a metallic soft magnetic material. In a specific embodiment, the magnetic film layer 13 is a metal film layer containing one of the elements such as iron, cobalt, and nickel, specifically an iron-containing metal film, or a nickel-containing metal film, or a cobalt-containing metal film, or an iron-nickel alloy film, or an iron-cobalt alloy film, or a nickel-cobalt alloy film, or an iron-nickel-cobalt alloy film.

金属软磁材料具有高饱和磁化强度,高磁导率,低矫顽力,并且其可以通过溅射、蒸发或电镀来制备,能较好的与当前封装工艺很好的兼容。Metallic soft magnetic materials have high saturation magnetization, high magnetic permeability, and low coercivity, and they can be prepared by sputtering, evaporation or electroplating, and are well compatible with current packaging processes.

本发明实施例公开的再布线结构1采用典型的再布线技术形成,采用具有感光性能的多层聚酰亚胺胶膜层作为绝缘层并在多层绝缘层堆叠设置的过程中形成所述绝缘体11。The rewiring structure 1 disclosed in the embodiment of the present invention is formed by using a typical rewiring technology, using a multi-layer polyimide film layer with photosensitive properties as an insulating layer and forming the insulator 11 in the process of stacking the multi-layer insulating layers.

所述绝缘层包括或由一或多种聚合物材料制成。聚合物材料可以包括聚苯恶唑(polybenzoxazole,PBO)、聚酰亚胺(polyimide,PI)、环氧基树脂、一种或多种其他合适的聚合物材料或其组合。在具体实施例中,绝缘层所使用的聚合物材料是光敏性的。因此,可以使用光刻工艺在绝缘层中形成线路图形。The insulating layer includes or is made of one or more polymer materials. The polymer material may include polybenzoxazole (PBO), polyimide (PI), epoxy resin, one or more other suitable polymer materials or a combination thereof. In a specific embodiment, the polymer material used for the insulating layer is photosensitive. Therefore, a circuit pattern can be formed in the insulating layer using a photolithography process.

在一些其他实施例中,部分或全部的绝缘层还包括或由聚合物材料以外的介电材料制成。介电材料可以包括氧化硅、碳化硅、氮化硅、氮氧化硅、一种或多种其他合适的材料或其组合。In some other embodiments, part or all of the insulating layer further includes or is made of a dielectric material other than the polymer material. The dielectric material may include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or a combination thereof.

在具体形成过程中,可以通过涂覆、沉积等方法形成所述绝缘层,然后刻蚀目标区域的绝缘层以在目标位置形成绝缘开窗,以绝缘层内的所有绝缘开窗形成线路图形,然后采用电镀等的方式在线路图形内或者在相应的绝缘层上表面设置所以图案化金属层12;整个再布线结构1需要在光刻工艺过程中通过多次的涂覆、刻蚀、电镀等工艺步骤最终形成。In the specific formation process, the insulating layer can be formed by coating, deposition and other methods, and then the insulating layer in the target area is etched to form insulating windows at the target position, and a circuit pattern is formed with all the insulating windows in the insulating layer. Then, electroplating and other methods are used to set the patterned metal layer 12 in the circuit pattern or on the upper surface of the corresponding insulating layer; the entire rewiring structure 1 needs to be finally formed through multiple coating, etching, electroplating and other process steps during the photolithography process.

以相邻的第一绝缘层和第二绝缘层为例,其中第二绝缘层设置在第一绝缘层的上表面,先设置第一绝缘层,在第一绝缘层的目标区域开设第一线路图形,第一线路图 形贯穿所述第一绝缘层,然后设置第一图案化金属层,第一图案化金属层设置在第一绝缘层的上表面,且部分第一图案化金属层填充在第一线路图形内;Taking the adjacent first insulating layer and the second insulating layer as an example, wherein the second insulating layer is arranged on the upper surface of the first insulating layer, the first insulating layer is arranged first, and a first circuit pattern is opened in the target area of the first insulating layer. A first patterned metal layer is formed on the upper surface of the first insulating layer, and a portion of the first patterned metal layer is filled in the first circuit pattern;

在第一绝缘层的上表面设置第二绝缘层,在第二绝缘层的目标区域设置第二线路图形,第二线路图形贯穿第二绝缘层,部分第一图案化金属层自第二线路图形向外暴露;在第二绝缘层上表面设置第二图案化金属层,部分第二图案化金属层设置在第二线路图形内并与第一图案化金属层电性连接。A second insulating layer is arranged on the upper surface of the first insulating layer, a second circuit pattern is arranged in a target area of the second insulating layer, the second circuit pattern penetrates the second insulating layer, and a portion of the first patterned metal layer is exposed outward from the second circuit pattern; a second patterned metal layer is arranged on the upper surface of the second insulating layer, and a portion of the second patterned metal layer is arranged in the second circuit pattern and is electrically connected to the first patterned metal layer.

可以理解的是在设置图案化金属层的时候,如果采用电镀方式,在电镀前还需要在绝缘层上表面设置种子层以及在种子层上表面涂覆光阻层,然后对设置金属层的区域所对应的光阻层进行曝光显影,以形成光阻窗格,在光阻窗格内电镀形成所述图案化金属层12。It is understandable that when setting the patterned metal layer, if electroplating is used, it is also necessary to set a seed layer on the upper surface of the insulating layer and coat a photoresist layer on the upper surface of the seed layer before electroplating, and then expose and develop the photoresist layer corresponding to the area where the metal layer is set to form a photoresist window pane, and electroplate the patterned metal layer 12 in the photoresist window pane.

在某一绝缘层上设置线路图形的时候,可以在该绝缘层上同时设置线圈开窗以形成电感线路,电感线圈122最终设置在线圈开窗内。当然在其他实施例中也可以直接将电感线圈122设置在绝缘层的第一表面,无需在相应的绝缘层设置线路图形。When a circuit pattern is arranged on a certain insulating layer, a coil opening can be arranged on the insulating layer at the same time to form an inductor circuit, and the inductor 122 is finally arranged in the coil opening. Of course, in other embodiments, the inductor 122 can also be directly arranged on the first surface of the insulating layer without the need to arrange a circuit pattern on the corresponding insulating layer.

电感线圈122的厚度可以与所对应的绝缘层的图案化金属层12的布线线路121厚度相同,在绝缘层上开设的线圈开窗与所述线路图形的深度可以设置成一致,可以同时设置电感线圈122与布线线路121。The thickness of the inductor coil 122 can be the same as the thickness of the wiring line 121 of the patterned metal layer 12 of the corresponding insulating layer. The depth of the coil opening opened on the insulating layer and the circuit pattern can be set to be consistent, and the inductor coil 122 and the wiring line 121 can be set at the same time.

当然电感线圈122的厚度也可以小于所对应的图案化金属层12中布线线路121的厚度,此时在设置电感线圈122的时候绝缘层上开设的线圈开窗的深度可以小于该绝缘层上线路图形的深度,线路图形内用于成型布线线路121。当然也可以使线路图形的深度与线圈开窗的深度一致,但在设置电感线圈122的时候,由于电感线圈122的厚度小于布线线路121的厚度,在线圈开窗内位于电感线圈122的上侧还留有空间,该空间内可以通过绝缘材料进行填充。Of course, the thickness of the inductor 122 can also be less than the thickness of the wiring line 121 in the corresponding patterned metal layer 12. In this case, when the inductor 122 is set, the depth of the coil window opened on the insulating layer can be less than the depth of the line pattern on the insulating layer, and the line pattern is used to form the wiring line 121. Of course, the depth of the line pattern can also be made consistent with the depth of the coil window, but when the inductor 122 is set, since the thickness of the inductor 122 is less than the thickness of the wiring line 121, there is still space in the coil window located on the upper side of the inductor 122, and the space can be filled with insulating material.

当然在其它实施例中由于电感线圈122的厚度非常薄无需在绝缘层内开设线圈开窗,因此,可以在绝缘层的第一表面直接设置所述电感线圈122。电感线圈122可以采用贴附的方式设置在绝缘层的第一表面,此时电感线圈122在该绝缘层所对应的布线线路121形成后再设置。Of course, in other embodiments, since the thickness of the inductor coil 122 is very thin, there is no need to open a coil window in the insulating layer, so the inductor coil 122 can be directly arranged on the first surface of the insulating layer. The inductor coil 122 can be arranged on the first surface of the insulating layer in an attached manner, and in this case, the inductor coil 122 is arranged after the wiring line 121 corresponding to the insulating layer is formed.

相应的,在具体实施例中所述绝缘体11包裹磁性薄膜层13,磁性薄膜层13也可以设置在再布线结构1形成过程中的任一绝缘层内或者设置在任意两个绝缘层之间,Accordingly, in a specific embodiment, the insulator 11 wraps the magnetic film layer 13, and the magnetic film layer 13 can also be arranged in any insulating layer or between any two insulating layers during the formation of the rewiring structure 1.

磁性薄膜层13延展平面与相应绝缘层内的图案化金属层12延展平面位于同一平面,磁性薄膜层13可以与相应位置的图案化金属层12同时设置,绝缘层设置线路图形的时候同时在绝缘层上设置薄膜开窗,在设置图案化金属层12的时候同时在薄膜开窗内设置磁性薄膜层13。 The extension plane of the magnetic film layer 13 and the extension plane of the patterned metal layer 12 in the corresponding insulating layer are located in the same plane. The magnetic film layer 13 can be set simultaneously with the patterned metal layer 12 at the corresponding position. When the circuit pattern is set on the insulating layer, a thin film window is set on the insulating layer at the same time. When the patterned metal layer 12 is set, the magnetic film layer 13 is set in the thin film window at the same time.

当然在其它实施例中由于磁性薄膜层13的厚度非常薄无需在绝缘层内开设薄膜开窗,因此,可以在绝缘层的第一表面直接设置所述磁性薄膜层13。具体的,磁性薄膜层13可以采用贴附的方式设置在绝缘层的第一表面,此时磁性薄膜层13在该绝缘层所对应的图案化金属层12设置后再设置。Of course, in other embodiments, since the thickness of the magnetic film layer 13 is very thin, there is no need to open a film window in the insulating layer, and therefore, the magnetic film layer 13 can be directly disposed on the first surface of the insulating layer. Specifically, the magnetic film layer 13 can be disposed on the first surface of the insulating layer in an attached manner, and in this case, the magnetic film layer 13 is disposed after the patterned metal layer 12 corresponding to the insulating layer is disposed.

在具体实施例中电感线圈122和所述磁性薄膜层13均在相应的绝缘层设置后设置,电感线圈122与磁性薄膜层13之间可以通过绝缘层分隔。为了更好的实现增强效果,所述电感线圈122被设置成与磁性薄膜层13紧邻,电感线圈122与磁性薄膜层13之间仅设置一层绝缘层。In a specific embodiment, the inductor coil 122 and the magnetic film layer 13 are both provided after the corresponding insulating layer is provided, and the inductor coil 122 and the magnetic film layer 13 may be separated by the insulating layer. In order to better achieve the enhancement effect, the inductor coil 122 is provided close to the magnetic film layer 13, and only one insulating layer is provided between the inductor coil 122 and the magnetic film layer 13.

磁性薄膜层13的数量可以设置有至少两层,在绝缘体11的第一表面111和第二表面112都可以设置所述磁性薄膜层13。此时电感线圈122相对设置在两个磁性薄膜层13之间,电感线圈122和磁性薄膜层13沿再布线结构1的厚度方向排列。The number of magnetic film layers 13 can be at least two, and the magnetic film layers 13 can be disposed on both the first surface 111 and the second surface 112 of the insulator 11. In this case, the inductor 122 is relatively disposed between the two magnetic film layers 13, and the inductor 122 and the magnetic film layers 13 are arranged along the thickness direction of the rewiring structure 1.

所述电感线圈122可以设置一层也可以设置两层,甚至可以设置成多层,在电感线圈122设置成两层的时候需要在两层图案化金属层12形成过程中设置电感线路。同样的,在电感线圈122设置多层的时候需要在每一相应的图案化金属层12形成过程中都设置电感线路。The inductor coil 122 can be provided in one layer, two layers, or even multiple layers. When the inductor coil 122 is provided in two layers, the inductor circuit needs to be provided in the process of forming the two patterned metal layers 12. Similarly, when the inductor coil 122 is provided in multiple layers, the inductor circuit needs to be provided in the process of forming each corresponding patterned metal layer 12.

在电感线圈122设置有两层或多层时,所述电感线圈122与所述磁性薄膜层13交替设置。这里的交替设置可以是一层电感线圈122上设置一层磁性薄膜层13,然后再在磁性薄膜层13上形成另一层电感线圈12,以上述规律沿再布线的厚度方向排列。When the inductor 122 is provided with two or more layers, the inductor 122 and the magnetic film layer 13 are alternately provided. The alternate arrangement here can be that a layer of magnetic film layer 13 is provided on a layer of inductor 122, and then another layer of inductor 12 is formed on the magnetic film layer 13, and they are arranged along the thickness direction of the rewiring according to the above rule.

具体的,在本发明的实施例中所述电感线圈122则设置有两层,两层电感线圈122相互平行,两层电感线圈122分别是在再布线结构1的厚度方向上排布的第一线圈和第二线圈。第一线圈和第二线圈之间通过部分绝缘体11分隔。所述磁性薄膜层13也设置有两层,两层电感线圈122设置在两层磁性薄膜层13之间。Specifically, in the embodiment of the present invention, the inductor coil 122 is provided with two layers, the two layers of inductor coils 122 are parallel to each other, and the two layers of inductor coils 122 are respectively a first coil and a second coil arranged in the thickness direction of the rewiring structure 1. The first coil and the second coil are separated by a part of the insulator 11. The magnetic film layer 13 is also provided with two layers, and the two layers of inductor coils 122 are arranged between the two layers of magnetic film layers 13.

当然在其他实施例中也可以使两层电感线圈122与两层磁性薄膜层13相互穿插设置,以使两层磁性薄膜层13之间相对设置一层电感线圈122,两层电感线圈122之间相对设置一层磁性薄膜层13。Of course, in other embodiments, the two layers of inductor coils 122 and the two layers of magnetic film layers 13 may be interlaced with each other, so that one layer of inductor coil 122 is disposed oppositely between the two layers of magnetic film layers 13 , and one layer of magnetic film layer 13 is disposed oppositely between the two layers of inductor coils 122 .

在其他实施例中还可以设置成两层磁性薄膜层13与一层电感线圈122配合的方式,两层磁性薄膜层13可以相对设置在电感线圈122的相对两侧,也可以设置在电感线圈122的同一侧。In other embodiments, two magnetic film layers 13 and one inductor 122 may be arranged in coordination. The two magnetic film layers 13 may be arranged on opposite sides of the inductor 122 or on the same side of the inductor 122 .

当然在其他实施例中还可以设置成三层磁性薄膜层13与两层电感线圈122配合的方式,具体的,三层磁性薄膜层13间隔设置,两层电感线圈122穿插在三层磁性薄膜层13之间。 Of course, in other embodiments, three magnetic film layers 13 may be arranged to cooperate with two inductor coils 122 . Specifically, the three magnetic film layers 13 are arranged at intervals, and the two inductor coils 122 are inserted between the three magnetic film layers 13 .

在本发明中电感线圈122所在绝缘层的厚度与磁性薄膜层13所在绝缘层的厚度之间的比值范围在0.5-2之间,这样结构的设置使封装结构能够在不改变现有形成工艺及形成设备的前提下形成,从而避免对形成工艺造成太大的影响,避免了生产成本的增加。In the present invention, the ratio between the thickness of the insulating layer where the inductor coil 122 is located and the thickness of the insulating layer where the magnetic film layer 13 is located is in the range of 0.5-2. Such a structural setting enables the packaging structure to be formed without changing the existing formation process and formation equipment, thereby avoiding too much impact on the formation process and avoiding an increase in production costs.

所述封装结构还具有金属凸块3,所述金属凸块3设置在所述再布线结构1背离所述芯片2的一侧,金属凸块3与所述布线线路121电性连接。当然在其他实施例中再布线结构1背离芯片2的一侧可以设置有其他的电联结构,如其他再布线层。The packaging structure further comprises a metal bump 3, which is arranged on a side of the rewiring structure 1 away from the chip 2, and the metal bump 3 is electrically connected to the wiring line 121. Of course, in other embodiments, the side of the rewiring structure 1 away from the chip 2 may be provided with other electrical connection structures, such as other rewiring layers.

电感线圈122可以设置成与所在图案化金属层12的布线线路121电性连接。在电感线圈122与所在图案化金属层12的布线线路121电性连接的时候,电感线圈122需要借助布线线路121向外传导电流信号,布线线路121最终借助金属凸块3向外传导电流信号。The inductor 122 can be configured to be electrically connected to the wiring line 121 of the patterned metal layer 12. When the inductor 122 is electrically connected to the wiring line 121 of the patterned metal layer 12, the inductor 122 needs to conduct current signals to the outside with the help of the wiring line 121, and the wiring line 121 finally conducts current signals to the outside with the help of the metal bump 3.

在其他实施例中还可设置单独的电感凸块4以用于与电感线圈122电性连接,具体的,电感凸块4设置在所述再布线结构1的第二表面并与所述电感线圈122电性连接。所述电感凸块4用于将电感线圈122引出,电感凸块4与金属凸块3可以采用相同结构及相同工艺形成。In other embodiments, a separate inductor bump 4 may be provided to be electrically connected to the inductor coil 122. Specifically, the inductor bump 4 is provided on the second surface of the rewiring structure 1 and is electrically connected to the inductor coil 122. The inductor bump 4 is used to lead out the inductor coil 122. The inductor bump 4 and the metal bump 3 may be formed using the same structure and the same process.

在具体实施例中芯片2为裸芯片,所述芯片2与再布线结构1之间通过多个导电柱5电性连接,导电柱5位于再布线结构与芯片2之间,实现芯片2与再布线结构1的电性连接。In a specific embodiment, the chip 2 is a bare chip. The chip 2 is electrically connected to the rewiring structure 1 via a plurality of conductive pillars 5 . The conductive pillars 5 are located between the rewiring structure and the chip 2 to achieve electrical connection between the chip 2 and the rewiring structure 1 .

所述封装结构还具有填充层6,所述填充层6填充于再布线结构1、芯片2之间的区域,且填充层6包围所述导电柱5。填充层6为整层结构,填充于多个芯片2与再布线结构1之间。在相邻的两个芯片2之间也填充有所述填充层6。The packaging structure further comprises a filling layer 6, which is filled in the area between the rewiring structure 1 and the chip 2, and the filling layer 6 surrounds the conductive pillar 5. The filling layer 6 is a whole layer structure, which is filled between the plurality of chips 2 and the rewiring structure 1. The filling layer 6 is also filled between two adjacent chips 2.

设置的填充层6以包围和保护芯片2与再布线结构1之间的导电柱5,此外,填充层6的设置还能够强化芯片2与再布线结构1之间的连接。填充层6可以包括或由绝缘材料制成,例如可以是热固胶。The filling layer 6 is provided to surround and protect the conductive pillars 5 between the chip 2 and the rewiring structure 1. In addition, the filling layer 6 can also strengthen the connection between the chip 2 and the rewiring structure 1. The filling layer 6 may include or be made of an insulating material, such as a thermosetting adhesive.

所述封装结构还包括第一保护层7,第一保护层7覆盖所述芯片2并对芯片2形成保护。第一保护层7可以为塑封层,构成第一保护层7的材料可以为环氧树脂胶粘剂通过膜封工艺制备形成。其中,构成第一保护层7的材料的弹性模量大于构成填充层的材料的弹性模量。The packaging structure further includes a first protective layer 7, which covers the chip 2 and protects the chip 2. The first protective layer 7 may be a plastic sealing layer, and the material constituting the first protective layer 7 may be an epoxy resin adhesive prepared by a film sealing process. The elastic modulus of the material constituting the first protective layer 7 is greater than the elastic modulus of the material constituting the filling layer.

在第二种实施例是堆叠式的封装结构,如图2所示,所述芯片2包括并列设置在所述再布线结构一侧的第一芯片21和第二芯片22;所述封装结构还包括桥接芯片8、桥接芯片保护层9和导电凸块10,所述桥接芯片8设置在所述再布线结构1背离所述芯片2的一侧并分别与所述第一芯片21、所述第二芯片22电性连接; In the second embodiment, a stacked packaging structure is provided. As shown in FIG2 , the chip 2 includes a first chip 21 and a second chip 22 arranged in parallel on one side of the rewiring structure; the packaging structure further includes a bridge chip 8, a bridge chip protection layer 9 and a conductive bump 10. The bridge chip 8 is provided on a side of the rewiring structure 1 away from the chip 2 and is electrically connected to the first chip 21 and the second chip 22 respectively.

桥接芯片保护层9设置在所述绝缘体11的第二表面112并覆盖所述桥接芯片8,所述桥接芯片保护层9上设置有贯穿所述桥接芯片保护层9的保护层通孔90;The bridge chip protection layer 9 is disposed on the second surface 112 of the insulator 11 and covers the bridge chip 8. The bridge chip protection layer 9 is provided with a protection layer through hole 90 penetrating the bridge chip protection layer 9.

导电凸块10设置在所述保护层通孔90内并电性连接所述布线线路121。The conductive bump 10 is disposed in the protective layer through hole 90 and electrically connected to the wiring line 121 .

所述封装结构还具有金属凸块3,所述金属凸块3设置在所述桥接芯片保护层9背离所述绝缘体11的一侧,所述金属凸块3与所述导电凸块10电性连接。The packaging structure further has a metal bump 3 , which is disposed on a side of the bridge chip protection layer 9 away from the insulator 11 , and is electrically connected to the conductive bump 10 .

所述封装结构还包括底部再布线层2020,所述底部再布线层2020设置在所述桥接芯片保护层9背离所述绝缘体11的一侧,并具有底绝缘层201和设置在底绝缘层201内的底金属层202;The packaging structure further includes a bottom rewiring layer 2020, which is disposed on a side of the bridge chip protection layer 9 away from the insulator 11 and includes a bottom insulating layer 201 and a bottom metal layer 202 disposed in the bottom insulating layer 201;

所述金属凸块3与所述导电凸块10相对设置在所述底部再布线层2020的两侧并通过所述底金属层202电性连接。The metal bumps 3 and the conductive bumps 10 are disposed opposite to each other on two sides of the bottom redistribution layer 2020 and are electrically connected through the bottom metal layer 202 .

上述实施例公开的封装结构的形成方法包括如下步骤:The method for forming the packaging structure disclosed in the above embodiment includes the following steps:

提供承载基板,并在所述承载基板的一侧设置结合层;Providing a carrier substrate, and disposing a bonding layer on one side of the carrier substrate;

在所述结合层背离所述承载基板的一侧形成所述再布线结构,其中,所述再布线结构具有绝缘体和嵌设于绝缘体内的若干图案化金属层,至少一所述图案化金属层包括布线线路和形成电感线圈的电感线路;所述再布线结构还包括在再布线结构厚度方向上设置于电感线圈至少一侧的磁性薄膜层;The rewiring structure is formed on a side of the bonding layer away from the carrier substrate, wherein the rewiring structure comprises an insulator and a plurality of patterned metal layers embedded in the insulator, at least one of the patterned metal layers comprises a wiring line and an inductor line forming an inductor coil; the rewiring structure further comprises a magnetic film layer arranged on at least one side of the inductor coil in a thickness direction of the rewiring structure;

将芯片与所述布线线路电性连接;electrically connecting the chip to the wiring line;

去除所述承载基板及所述结合层。The carrier substrate and the bonding layer are removed.

结合具体实施例,本申请的第一种方式的封装结构的形成方式如下:In combination with the specific embodiment, the packaging structure of the first embodiment of the present application is formed as follows:

S100:如图3A所示,提供承载基板100,并在所述承载基板100第一表面设置结合层200;S100: As shown in FIG. 3A , providing a carrier substrate 100 , and disposing a bonding layer 200 on a first surface of the carrier substrate 100 ;

所述承载基板100可以是玻璃载体或可适用于封装结构的制造方法的任何合适的载体;在具体实施例中,所述承载基板100是硅基板,承载基板100在封装结构设置的时候用于辅佐,后期需要将承载基板100去除;The carrier substrate 100 may be a glass carrier or any suitable carrier applicable to the manufacturing method of the packaging structure; in a specific embodiment, the carrier substrate 100 is a silicon substrate, which is used to assist in setting the packaging structure and needs to be removed later;

为了更好的实现再布线结构1在承载基板100上的设置,在承载基板100第一表面设置结合层200,结合层200也作为再布线结构1形成过程的辅助层,在封装完成后需要去除;所述结合层200可以为胶层。In order to better realize the arrangement of the rewiring structure 1 on the carrier substrate 100, a bonding layer 200 is arranged on the first surface of the carrier substrate 100. The bonding layer 200 also serves as an auxiliary layer in the formation process of the rewiring structure 1 and needs to be removed after the packaging is completed; the bonding layer 200 can be an adhesive layer.

S200:如图3B所示,在所述结合层200背离所述承载基板100的表面设置再布线结构1,在再布线结构1设置的过程中在再布线结构内形成电感线圈122;同时,在再布线结构1形成过程中在再布线结构1内设置磁性薄膜层13;其中,所述磁性薄膜层13设置在所述电感线圈122在厚度方向的一侧; S200: As shown in FIG3B , a rewiring structure 1 is arranged on the surface of the bonding layer 200 away from the carrier substrate 100, and an inductor 122 is formed in the rewiring structure during the process of the rewiring structure 1 being arranged; at the same time, a magnetic film layer 13 is arranged in the rewiring structure 1 during the process of forming the rewiring structure 1; wherein the magnetic film layer 13 is arranged on one side of the inductor 122 in the thickness direction;

对于第一种实施例由于再布线结构1包裹磁性薄膜层13且再布线结构1也同时包裹电感线圈122,因此在形成再布线结构1的时候可以在再布线结构1内设置所述磁性薄膜层13,在形成再布线结构1的时候也同时在再布线结构1内设置电感线圈122;磁性薄膜层13可以采用电镀的方式与图案化金属层12同时形成;For the first embodiment, since the rewiring structure 1 wraps the magnetic film layer 13 and the rewiring structure 1 also wraps the inductor 122, the magnetic film layer 13 can be arranged in the rewiring structure 1 when the rewiring structure 1 is formed, and the inductor 122 can be arranged in the rewiring structure 1 when the rewiring structure 1 is formed; the magnetic film layer 13 can be formed simultaneously with the patterned metal layer 12 by electroplating;

S300:如图3C所示,通过导电柱5将芯片2与所述再布线结构1电性连接;本发明实施例中芯片2采用覆晶封装的方式结合到再布线结构1上,导电柱5可以为铜柱,铜柱设置在再布线结构1的第一表面并朝向芯片2的一侧;导电柱5与再布线结构1内的图案化金属层12位置相对并电性连接;S300: As shown in FIG3C , the chip 2 is electrically connected to the rewiring structure 1 through the conductive pillar 5; in the embodiment of the present invention, the chip 2 is combined with the rewiring structure 1 by flip-chip packaging, and the conductive pillar 5 can be a copper pillar, which is arranged on the first surface of the rewiring structure 1 and faces one side of the chip 2; the conductive pillar 5 is opposite to the patterned metal layer 12 in the rewiring structure 1 and is electrically connected;

S400:如图3D所示,去除所述承载基板100及所述结合层200,并在再布线结构1背离所述芯片2的一侧设置金属凸块3(图3E所示)。S400: As shown in FIG. 3D , the carrier substrate 100 and the bonding layer 200 are removed, and a metal bump 3 is provided on a side of the rewiring structure 1 away from the chip 2 (as shown in FIG. 3E ).

在其他实施例中,如果磁性薄膜层13设置在再布线结构1的第一表面或第二表面,与上述实施例不同的是在所述结合层200背离所述承载基板100的一侧设置再布线结构1,并在设置再布线结构1的过程中设置电感线圈122以使电感线圈122设置在再布线结构1内,具体的,电感线圈122设置在绝缘体11内;同时,在设置再布线结构1之后设置磁性薄膜层13,以使磁性薄膜层13设置在再布线结构1背离结合层200的第一表面,具体的,磁性薄膜层13设置在绝缘体11的第一表面;In other embodiments, if the magnetic film layer 13 is disposed on the first surface or the second surface of the rewiring structure 1, the difference from the above embodiment is that the rewiring structure 1 is disposed on the side of the bonding layer 200 away from the carrier substrate 100, and the inductor 122 is disposed in the process of disposing the rewiring structure 1 so that the inductor 122 is disposed in the rewiring structure 1, specifically, the inductor 122 is disposed in the insulator 11; at the same time, after the rewiring structure 1 is disposed, the magnetic film layer 13 is disposed so that the magnetic film layer 13 is disposed on the first surface of the rewiring structure 1 away from the bonding layer 200, specifically, the magnetic film layer 13 is disposed on the first surface of the insulator 11;

上述实施例中所述磁性薄膜层13是在再布线结构1形成后;磁性薄膜层13具体可以采用贴附的方式直接贴附在再布线结构1的第一表面,当然也可以采用电镀的方式设置,在电镀之前可以在再布线结构1背离结合层200的第一表面设置绝缘层,并在绝缘层开设薄膜开窗,磁性薄膜层13电镀成型在薄膜开窗内;The magnetic film layer 13 described in the above embodiment is formed after the rewiring structure 1 is formed; the magnetic film layer 13 can be directly attached to the first surface of the rewiring structure 1 by means of attachment, and can also be provided by means of electroplating. Before electroplating, an insulating layer can be provided on the first surface of the rewiring structure 1 away from the bonding layer 200, and a thin film window can be provided on the insulating layer, and the magnetic film layer 13 is formed by electroplating in the thin film window;

在其他实施例中还可以在再布线结构1设置之前在所述结合层200上设置磁性薄膜层13;具体的,在所述结合层200背离所述承载基板100的第一表面设置再布线结构1,并在设置再布线结构1的过程中设置电感线圈122以使电感线圈122设置在再布线结构1内,具体的,电感线圈122设置在绝缘体11内;同时,在设置再布线结构1之前,在结合层200背离所述承载基板100的第一表面设置磁性薄膜层13;同样的,磁性薄膜层13可以采用贴附的方式直接贴附在结合层200的第一表面,当然也可以采用电镀的方式设置,在电镀之前可以在结合层200背离承载基板的第一表面设置绝缘层,并在绝缘层开设薄膜开窗,磁性薄膜层13电镀成型在薄膜开窗内。In other embodiments, a magnetic film layer 13 may be provided on the bonding layer 200 before the rewiring structure 1 is provided; specifically, the rewiring structure 1 is provided on the first surface of the bonding layer 200 away from the carrier substrate 100, and in the process of providing the rewiring structure 1, an inductor 122 is provided so that the inductor 122 is provided in the rewiring structure 1, specifically, the inductor 122 is provided in the insulator 11; at the same time, before providing the rewiring structure 1, a magnetic film layer 13 is provided on the first surface of the bonding layer 200 away from the carrier substrate 100; similarly, the magnetic film layer 13 may be directly attached to the first surface of the bonding layer 200 by means of attachment, and of course, may be provided by means of electroplating, and before electroplating, an insulating layer may be provided on the first surface of the bonding layer 200 away from the carrier substrate, and a thin film window may be provided in the insulating layer, and the magnetic film layer 13 may be formed by electroplating in the thin film window.

其中,S200:中“在所述结合层背离所述承载基板的一侧形成所述再布线结构”具体包括如下步骤: Wherein, in S200: “forming the rewiring structure on a side of the bonding layer away from the carrier substrate” specifically includes the following steps:

如图3E所示,在结合层200上依次堆叠若干绝缘层,在每一绝缘层的目标区域刻蚀出线路图形,在相邻绝缘层之间设置图案化金属层12,部分图案化金属层12设置在线路图形内以与相邻的图案化金属层12电性连接;As shown in FIG. 3E , several insulating layers are sequentially stacked on the bonding layer 200 , a circuit pattern is etched in a target area of each insulating layer, a patterned metal layer 12 is disposed between adjacent insulating layers, and a portion of the patterned metal layer 12 is disposed within the circuit pattern to be electrically connected to the adjacent patterned metal layer 12 ;

在某一绝缘层上设置线路图形的同时,在该绝缘层上设置线圈开窗,在线路图形内设置图案化金属层12的同时,在线圈开窗内设置电感线圈122;需要说明的是线路图形和线圈开窗均沿垂直于绝缘层延展平面的方向贯穿所在的绝缘层,线路图形和线圈开窗都可以采用刻蚀工艺形成。While a circuit pattern is provided on a certain insulating layer, a coil window is provided on the insulating layer; while a patterned metal layer 12 is provided in the circuit pattern, an inductor coil 122 is provided in the coil window; it should be noted that both the circuit pattern and the coil window penetrate the insulating layer in a direction perpendicular to the extension plane of the insulating layer, and both the circuit pattern and the coil window can be formed by an etching process.

在位于电感线圈122上侧的某一绝缘层内的图案化金属层12设置的同时设置磁性薄膜层13;或者在位于电感线圈122下侧的某一绝缘层内的图案化金属层12设置的时候,同时设置磁性薄膜层13。The magnetic film layer 13 is disposed simultaneously with the patterned metal layer 12 in a certain insulating layer located above the inductor 122 ; or the magnetic film layer 13 is disposed simultaneously with the patterned metal layer 12 in a certain insulating layer located below the inductor 122 .

在“S300:通过电连接件将芯片2与所述再布线结构1电性连接”之后还包括在芯片2与再布线结构1之间设置填充层6;在芯片2背离再布线结构1的表面及再布线结构1的第一表面111设置第一保护层7,第一保护层7覆盖所述芯片2及所述再布线结构1。After "S300: electrically connecting the chip 2 to the rewiring structure 1 through an electrical connector", the process also includes setting a filling layer 6 between the chip 2 and the rewiring structure 1; setting a first protective layer 7 on the surface of the chip 2 facing away from the rewiring structure 1 and on the first surface 111 of the rewiring structure 1, and the first protective layer 7 covers the chip 2 and the rewiring structure 1.

如图4A-4G所示,第二种实施例中的封装结构的形成方法包括如下步骤:As shown in FIGS. 4A-4G , the method for forming the packaging structure in the second embodiment includes the following steps:

S100:如图4A所示,提供承载基板100,并在所述承载基板100第一表面设置结合层200;S100: As shown in FIG. 4A , providing a carrier substrate 100 , and disposing a bonding layer 200 on a first surface of the carrier substrate 100 ;

S200:如图4A所示,在所述结合层200第一表面设置底绝缘层201,刻蚀所述底绝缘层201以形成线路图形,在线路图形内设置底部金属层202,以形成底部再布线层20;在所述底部金属层202上设置导电凸块10,导电凸块10凸伸出所述底绝缘层的第一表面;导电凸块10作为电连接再布线结构1和底部再布线层20;导电凸块10可以采用焊接的方式设置在相应的底部金属层202上,当然导电凸块10也可以采用常规的电镀方式设置。在具体实施例中底绝缘层201由一层绝缘材料形成,底金属层202由一层金属层堆叠;当然在其他实施例中,底绝缘层201还可以由多层绝缘层堆叠形成,相应的,底部金属层202也相应的由多层金属层堆叠形成;可以理解的是,可以根据实际需要对底部再布线层20中堆叠的绝缘层的数量进行设置;S200: As shown in FIG4A , a bottom insulating layer 201 is provided on the first surface of the bonding layer 200, the bottom insulating layer 201 is etched to form a circuit pattern, a bottom metal layer 202 is provided in the circuit pattern to form a bottom rewiring layer 20; a conductive bump 10 is provided on the bottom metal layer 202, and the conductive bump 10 protrudes out of the first surface of the bottom insulating layer; the conductive bump 10 serves to electrically connect the rewiring structure 1 and the bottom rewiring layer 20; the conductive bump 10 can be provided on the corresponding bottom metal layer 202 by welding, and of course the conductive bump 10 can also be provided by conventional electroplating. In a specific embodiment, the bottom insulating layer 201 is formed by a layer of insulating material, and the bottom metal layer 202 is stacked by a layer of metal layers; of course, in other embodiments, the bottom insulating layer 201 can also be formed by stacking multiple insulating layers, and correspondingly, the bottom metal layer 202 is also formed by stacking multiple metal layers; it can be understood that the number of insulating layers stacked in the bottom rewiring layer 20 can be set according to actual needs;

S300:如图4B所示,在底绝缘层上设置桥接芯片8,其中,桥接芯片8的焊盘朝背离底绝缘层201的方向设置;且桥接芯片8的焊盘上设置有芯片凸块;桥接芯片8可以采用胶体贴附在所述底绝缘层201之上;S300: As shown in FIG4B , a bridge chip 8 is disposed on the bottom insulating layer, wherein the pads of the bridge chip 8 are disposed in a direction away from the bottom insulating layer 201 ; and chip bumps are disposed on the pads of the bridge chip 8 ; the bridge chip 8 can be attached to the bottom insulating layer 201 by using colloid;

S400:如图4B所示,在桥接芯片8及所述底部再布线层20第一表面设置桥接芯片保护层9,桥接芯片保护层9对桥接芯片8形成覆盖,同时桥接芯片保护层9对底部再布线层20形成覆盖,去除部分桥接芯片保护层9以使芯片凸块及所述导电凸块10 自所述桥接芯片保护层9的第一表面向外暴露;具体的,可以采用研磨工艺去除桥接芯片保护层9的顶面部分以使芯片凸块及导电凸块10齐平并同时向外暴露;桥接芯片保护层9可以为塑封层,具体结构和材质与所述第一保护层7相一致,在此不再赘述。S400: As shown in FIG4B , a bridge chip protection layer 9 is provided on the first surface of the bridge chip 8 and the bottom rewiring layer 20, the bridge chip protection layer 9 covers the bridge chip 8, and the bridge chip protection layer 9 covers the bottom rewiring layer 20, and a portion of the bridge chip protection layer 9 is removed to allow the chip bumps and the conductive bumps 10 to be The first surface of the bridge chip protection layer 9 is exposed outward; specifically, a grinding process can be used to remove the top surface of the bridge chip protection layer 9 so that the chip bumps and the conductive bumps 10 are flush and exposed outward at the same time; the bridge chip protection layer 9 can be a plastic packaging layer, and the specific structure and material are consistent with the first protection layer 7, which will not be repeated here.

S500:如图4C-4D所示,在所述桥接芯片保护层9的第一表面先设置一层绝缘层;刻蚀目标区域的所述绝缘层以在该绝缘层形成线路图形;在线路图形内设置图案化金属层12且部分图案化金属层12覆盖在绝缘层的第一表面,多层绝缘层堆叠及多层金属层交错堆叠后形成所述再布线结构1;S500: As shown in FIGS. 4C-4D , an insulating layer is firstly provided on the first surface of the bridge chip protection layer 9; the insulating layer in the target area is etched to form a circuit pattern on the insulating layer; a patterned metal layer 12 is provided in the circuit pattern and part of the patterned metal layer 12 covers the first surface of the insulating layer, and multiple insulating layers are stacked and multiple metal layers are staggered to form the rewiring structure 1;

在形成所述再布线结构1的过程中在某一绝缘层设置线路图形的同时,在该绝缘层同时设置线圈开窗,在线路图形内设置布线线路121的同时在线圈开窗内设置电感线圈122;In the process of forming the rewiring structure 1, a circuit pattern is provided on a certain insulating layer, and a coil opening is provided on the insulating layer at the same time, and a wiring line 121 is provided in the circuit pattern and an inductor coil 122 is provided in the coil opening;

在位于电感线圈122上侧某一绝缘层内的图案化金属层12设置的时候同时设置磁性薄膜层13;或者在位于电感线圈122下侧的某一绝缘层内的图案化金属层12设置的时候,同时设置磁性薄膜层13;When the patterned metal layer 12 in a certain insulating layer on the upper side of the inductor 122 is provided, the magnetic film layer 13 is provided at the same time; or when the patterned metal layer 12 in a certain insulating layer on the lower side of the inductor 122 is provided, the magnetic film layer 13 is provided at the same time;

对于具体实施例在桥接芯片保护层9的第一表面设置绝缘层,在刻蚀绝缘层形成线路图形的时候,在该绝缘层上还同时开设有薄膜开窗;在线路图形内设置图案化金属层12的时候,同时在薄膜开窗内设置磁性薄膜层13,之后按照上述方式设置电感线圈122,在电感线圈122设置后在电感线圈122的上侧在设置磁性薄膜层13,通过两层磁性薄膜层13的设置以增强电感线圈122的使用稳定性。For the specific embodiment, an insulating layer is set on the first surface of the bridge chip protection layer 9. When the insulating layer is etched to form a circuit pattern, a thin film window is also opened on the insulating layer; when the patterned metal layer 12 is set in the circuit pattern, a magnetic thin film layer 13 is also set in the thin film window, and then the inductor 122 is set in the above manner. After the inductor 122 is set, the magnetic thin film layer 13 is set on the upper side of the inductor 122. The two layers of magnetic thin film layers 13 are set to enhance the stability of the inductor 122.

S600:如图4E所示,通过导电柱5将芯片2与再布线结构1电性连接;S600: As shown in FIG4E , the chip 2 is electrically connected to the rewiring structure 1 through the conductive pillars 5;

S700:如图4F所示,在芯片2与再布线结构1之间设置填充层6;S700: As shown in FIG4F , a filling layer 6 is provided between the chip 2 and the rewiring structure 1 ;

S800:如图4F所示,在再布线结构1的第一表面设置第一保护层7,以将所述芯片2及所述再布线结构1塑封;S800: As shown in FIG. 4F , a first protective layer 7 is provided on the first surface of the rewiring structure 1 to plastic-encapsulate the chip 2 and the rewiring structure 1 ;

S900:如图4G所示,去除所述承载基板100及所述结合层200,并在底绝缘层的第二表面设置金属凸块3,金属凸块3与底部金属层202电性连接。S900 : As shown in FIG. 4G , the carrier substrate 100 and the bonding layer 200 are removed, and a metal bump 3 is disposed on the second surface of the bottom insulating layer, and the metal bump 3 is electrically connected to the bottom metal layer 202 .

以上依据图式所示的实施例详细说明了本发明的构造、特征及作用效果,以上所述仅为本发明的较佳实施例,但本发明不以图面所示限定实施范围,凡是依照本发明的构想所作的改变,或修改为等同变化的等效实施例,仍未超出说明书与图示所涵盖的精神时,均应在本发明的保护范围内。 The above describes in detail the structure, features and effects of the present invention based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the drawings. Any changes made according to the concept of the present invention, or modified into equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and the drawings, should be within the protection scope of the present invention.

Claims (12)

一种封装结构,其特征在于,包括:A packaging structure, characterized by comprising: 再布线结构,具有绝缘体和嵌设于绝缘体内的若干图案化金属层,至少一所述图案化金属层具有布线线路和形成电感线圈的电感线路;所述再布线结构还包括磁性薄膜层,在再布线结构厚度方向上,所述磁性薄膜层设置于电感线圈的至少一侧;A rewiring structure comprises an insulator and a plurality of patterned metal layers embedded in the insulator, at least one of the patterned metal layers comprises a wiring circuit and an inductor circuit forming an inductor coil; the rewiring structure further comprises a magnetic film layer, and in the thickness direction of the rewiring structure, the magnetic film layer is arranged on at least one side of the inductor coil; 芯片,设置于所述再布线结构沿厚度方向的一侧并与所述布线线路电性连接。The chip is arranged on one side of the rewiring structure along the thickness direction and is electrically connected to the wiring line. 根据权利要求1所述的封装结构,其特征在于,在再布线结构的厚度方向上,所述电感线圈的位置与所述磁性薄膜层位置相对。The packaging structure according to claim 1 is characterized in that, in the thickness direction of the rewiring structure, the position of the inductor coil is opposite to the position of the magnetic film layer. 根据权利要求1所述的封装结构,其特征在于,所述磁性薄膜层嵌设于所述绝缘体内,所述磁性薄膜层与所述电感线圈之间通过部分所述绝缘体分隔。The packaging structure according to claim 1 is characterized in that the magnetic film layer is embedded in the insulator, and the magnetic film layer and the inductor coil are separated by a portion of the insulator. 根据权利要求1所述的封装结构,其特征在于,所述绝缘体具有背向设置的第一表面和第二表面;所述磁性薄膜层设置于所述第一表面、所述第二表面中的至少一个。The packaging structure according to claim 1 is characterized in that the insulator has a first surface and a second surface arranged in opposite directions; and the magnetic film layer is arranged on at least one of the first surface and the second surface. 根据权利要求1至4任一项所述的封装结构,其特征在于,所述磁性薄膜层设置有至少两层,所述电感线圈设置在两层所述磁性薄膜层之间。The packaging structure according to any one of claims 1 to 4 is characterized in that the magnetic film layer is provided with at least two layers, and the inductor coil is provided between the two magnetic film layers. 根据权利要求5所述的封装结构,其特征在于,所述电感线圈也设置有至少两层;The packaging structure according to claim 5, characterized in that the inductor coil is also provided with at least two layers; 在再布线结构厚度方向上,所述电感线圈与所述磁性薄膜层交替设置。In the thickness direction of the rewiring structure, the inductor coils and the magnetic film layers are arranged alternately. 根据权利要求1至4任一项所述的封装结构,其特征在于,所述磁性薄膜层为含铁金属薄膜层、或含镍金属薄膜层、或含钴金属薄膜层、或含铁镍合金薄膜层、或含铁钴合金薄膜层、或含镍钴合金薄膜层、或含铁镍钴合金薄膜层中的一种或多种的叠加。The packaging structure according to any one of claims 1 to 4 is characterized in that the magnetic film layer is a superposition of one or more of an iron-containing metal film layer, a nickel-containing metal film layer, a cobalt-containing metal film layer, an iron-nickel alloy film layer, an iron-cobalt alloy film layer, a nickel-cobalt alloy film layer, or an iron-nickel-cobalt alloy film layer. 根据权利要求1所述的封装结构,其特征在于,所述封装结构还具有金属凸块,所述金属凸块设置在所述再布线结构背离所述芯片的一侧,所述金属凸块与所述布线线路电性连接;The packaging structure according to claim 1, characterized in that the packaging structure further comprises a metal bump, the metal bump is arranged on a side of the rewiring structure away from the chip, and the metal bump is electrically connected to the wiring line; 所述封装结构还具有电感凸块,所述电感凸块设置在所述再布线结构背离所述芯片的一侧,所述电感凸块与所述电感线圈电性连接;所述电感线圈与所述布线线路之间通过部分所述绝缘体分隔。The packaging structure also has an inductor bump, which is arranged on a side of the rewiring structure away from the chip, and is electrically connected to the inductor coil; the inductor coil and the wiring line are separated by a portion of the insulator. 根据权利要求1所述的封装结构,其特征在于,所述芯片包括并列设置在所述再布线结构一侧的第一芯片和第二芯片;The packaging structure according to claim 1, characterized in that the chip comprises a first chip and a second chip arranged in parallel on one side of the rewiring structure; 所述封装结构还包括: The packaging structure further includes: 桥接芯片,设置在所述再布线结构背离所述芯片的一侧并分别与所述第一芯片、所述第二芯片电性连接;A bridge chip, arranged on a side of the rewiring structure away from the chip and electrically connected to the first chip and the second chip respectively; 桥接芯片保护层,设置在所述绝缘体的第二表面并覆盖所述桥接芯片,所述桥接芯片保护层上设置有贯穿所述桥接芯片保护层的保护层通孔;A bridge chip protection layer is disposed on the second surface of the insulator and covers the bridge chip, and a protection layer through hole penetrating the bridge chip protection layer is disposed on the bridge chip protection layer; 导电凸块,设置在所述保护层通孔内并电性连接所述布线线路。A conductive bump is disposed in the through hole of the protection layer and electrically connected to the wiring line. 根据权利要求9所述的封装结构,其特征在于,所述封装结构还具有金属凸块,所述金属凸块设置在所述桥接芯片保护层背离所述绝缘体的一侧,所述金属凸块与所述导电凸块电性连接。The packaging structure according to claim 9 is characterized in that the packaging structure further comprises a metal bump, the metal bump is arranged on a side of the bridge chip protection layer away from the insulator, and the metal bump is electrically connected to the conductive bump. 根据权利要求10所述的封装结构,其特征在于,所述封装结构还包括:The packaging structure according to claim 10, characterized in that the packaging structure further comprises: 底部再布线层,设置在所述桥接芯片保护层背离所述绝缘体的一侧,并具有底绝缘层和设置在底绝缘层内的底金属层;A bottom rewiring layer is arranged on a side of the bridge chip protection layer away from the insulator and comprises a bottom insulating layer and a bottom metal layer arranged in the bottom insulating layer; 所述金属凸块与所述导电凸块相对设置在所述底部再布线层的两侧并通过所述底金属层电性连接。The metal bumps and the conductive bumps are arranged opposite to each other at two sides of the bottom redistribution layer and are electrically connected through the bottom metal layer. 一种如权利要求1至11任一项所述的封装结构的形成方法,其特征在于,包括如下步骤:A method for forming a packaging structure according to any one of claims 1 to 11, characterized in that it comprises the following steps: 提供承载基板,并在所述承载基板的一侧设置结合层;Providing a carrier substrate, and disposing a bonding layer on one side of the carrier substrate; 在所述结合层背离所述承载基板的一侧形成所述再布线结构,其中,所述再布线结构具有绝缘体和嵌设于绝缘体内的若干图案化金属层,至少一所述图案化金属层包括布线线路和形成电感线圈的电感线路;The rewiring structure is formed on a side of the bonding layer away from the carrier substrate, wherein the rewiring structure comprises an insulator and a plurality of patterned metal layers embedded in the insulator, and at least one of the patterned metal layers comprises a wiring circuit and an inductor circuit forming an inductor coil; 将芯片与所述布线线路电性连接;electrically connecting the chip to the wiring circuit; 去除所述承载基板及所述结合层。 The carrier substrate and the bonding layer are removed.
PCT/CN2024/071820 2023-03-13 2024-01-11 Packaging structure and forming method WO2024187941A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103247606A (en) * 2013-04-16 2013-08-14 江阴长电先进封装有限公司 High-inductance-value silica-based planar spiral inductor structure
CN107492437A (en) * 2017-08-11 2017-12-19 华进半导体封装先导技术研发中心有限公司 A kind of glass base high Q value inductance and preparation method thereof
US20180174994A1 (en) * 2016-12-16 2018-06-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
CN109904083A (en) * 2017-12-08 2019-06-18 应用材料公司 Method and apparatus for wafer-level die bridge
CN116344506A (en) * 2023-03-13 2023-06-27 江阴长电先进封装有限公司 Packaging structure and forming method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103247606A (en) * 2013-04-16 2013-08-14 江阴长电先进封装有限公司 High-inductance-value silica-based planar spiral inductor structure
US20180174994A1 (en) * 2016-12-16 2018-06-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
CN107492437A (en) * 2017-08-11 2017-12-19 华进半导体封装先导技术研发中心有限公司 A kind of glass base high Q value inductance and preparation method thereof
CN109904083A (en) * 2017-12-08 2019-06-18 应用材料公司 Method and apparatus for wafer-level die bridge
CN116344506A (en) * 2023-03-13 2023-06-27 江阴长电先进封装有限公司 Packaging structure and forming method

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