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WO2024177189A1 - Temperature sensor - Google Patents

Temperature sensor Download PDF

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Publication number
WO2024177189A1
WO2024177189A1 PCT/KR2023/003369 KR2023003369W WO2024177189A1 WO 2024177189 A1 WO2024177189 A1 WO 2024177189A1 KR 2023003369 W KR2023003369 W KR 2023003369W WO 2024177189 A1 WO2024177189 A1 WO 2024177189A1
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WIPO (PCT)
Prior art keywords
mos transistor
mos
temperature
voltage
temperature sensor
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PCT/KR2023/003369
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French (fr)
Korean (ko)
Inventor
남재원
유현영
김주성
Original Assignee
한밭대학교 산학협력단
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Publication of WO2024177189A1 publication Critical patent/WO2024177189A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G01K7/01—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using semiconducting elements having PN junctions
    • G01K7/015—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using semiconducting elements having PN junctions using microstructures, e.g. made of silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Definitions

  • the present invention relates to a temperature sensor, and more particularly, to a temperature sensor that measures temperature with a voltage output from an N-MOS and P-MOS transistor having a stack structure.
  • Thermistors are typically used as temperature sensors, but since they have process constraints when trying to unify the chips to which they are applied, they are not suitable for single chips.
  • MOS Metal Oxide Silicon
  • the use of MOS transistors is mainly used in hybrid ICs that mix digital and analog circuits, which have been widely used recently, so there are limits to the use of bipolar transistors.
  • DTCXO digital temperature compensation oscillator
  • the MOS transistor process must be used, so a temperature sensor circuit using a MOS transistor element is absolutely necessary.
  • Temperature sensors using MOS transistors detect temperature by measuring the voltage or current output that changes depending on the temperature.
  • the voltage or current output is proportional to the temperature, it has the characteristic of changing rapidly in a certain section like an exponential function. Since the signal output from the temperature sensor is more linear, it is easier to change it into a digital signal, so temperature sensors using conventional MOS transistors require postprocessing such as taking an inverse function to convert it into a digital signal. Therefore, temperature sensors using conventional MOS transistors have problems such as postprocessing costs.
  • temperature sensors using existing MOS transistors have a very low output voltage range.
  • the output voltage range of the MOS transistor according to temperature change is directly related to the sensitivity of detecting temperature, and the lower the output voltage range, the more sensitive the temperature detection becomes, which makes it easy for errors to occur. Therefore, it is necessary to increase the output voltage range of the MOS transistor according to temperature change, and previously, post-processing work such as amplifying the output voltage using an amplifier, etc. was performed. Such post-processing work not only requires additional cost and time, but also has the problem that noise may occur depending on the performance of the amplifier.
  • the present invention is to solve the above-mentioned problems, and the purpose of the present invention is to configure MOS transistors of the same type in a stack structure to output a voltage that is linear with respect to temperature, and to calculate the difference between the voltage output from an N-MOS transistor that is proportional to the temperature and the voltage output from a P-MOS transistor that is inversely proportional to the temperature, thereby widening the range of the output voltage.
  • a temperature sensor comprising: a first MOS transistor having one end connected to a power source, a second MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to ground, and a temperature detection unit providing temperature information based on a voltage of a node where the other end of the first MOS transistor and one end of the second MOS transistor are connected, wherein the first and second MOS transistors are N-MOS transistors or P-MOS transistors, are of the same type, and gates of the first and second MOS transistors are commonly connected.
  • a first MOS transistor and a second MOS transistor of the same type are connected in a stack structure, and the gates of the first MOS transistor and the second MOS transistor are commonly connected, so that an output voltage can be generated according to a temperature change even when the first MOS transistor and the second MOS transistor are in an OFF state.
  • a voltage that varies depending on temperature may be generated at a node where the other end of the first MOS transistor and one end of the second MOS transistor are connected due to leakage current generated in the second MOS transistor.
  • temperature information can be provided based on a voltage that changes depending on temperature at a node connected between the other end of the first MOS transistor and one end of the second MOS transistor.
  • a voltage proportional to temperature and linearly can be output through a plurality of N-MOS transistors configured in a stack structure.
  • the range of the output voltage can be widened by making at least one of the gate oxide capacitance per unit area and the channel width of the first MOS transistor larger than that of the second MOS transistor.
  • At least one of the gate oxide capacitance per unit area and the channel width of the first MOS transistor can be made larger than that of the second MOS transistor, thereby outputting a more linear voltage.
  • a voltage that is inversely proportional to temperature and linear can be output through a plurality of P-MOS transistors configured in a stack structure.
  • temperature information can be provided based on the voltage difference between the voltage of a node connected between the other terminal of the first MOS transistor and one terminal of the second MOS transistor and the voltage of a node connected between the other terminal of the third MOS transistor and one terminal of the fourth MOS transistor.
  • the range of output voltage according to temperature can be expanded by utilizing the difference between the voltage of the node connected between the other terminal of the first MOS transistor and one terminal of the second MOS transistor and the voltage of the node connected between the other terminal of the third MOS transistor and one terminal of the fourth MOS transistor.
  • the temperature detection unit can convert an output voltage according to a temperature change into a digital signal to provide processed temperature information.
  • FIG. 1 is a circuit diagram of a temperature sensor composed of an N-MOS transistor according to an embodiment of the present invention.
  • FIG. 2 is a circuit diagram of a temperature sensor composed of a P-MOS transistor according to an embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a temperature sensor configured by merging an N-MOS transistor and a P-MOS transistor according to an embodiment of the present invention.
  • FIG. 4 is a graph showing a measurement voltage in a temperature sensor composed of an N-MOS transistor according to an embodiment of the present invention.
  • FIG. 5 is a graph showing a measurement voltage in a temperature sensor composed of a P-MOS transistor according to an embodiment of the present invention.
  • FIG. 6 is a graph showing a measured voltage as the physical characteristics of a first MOS transistor (N-MOS) increase according to one embodiment of the present invention.
  • FIG. 7 is a graph showing a measured voltage as the physical characteristics of a first MOS transistor (P-MOS) increase according to one embodiment of the present invention.
  • a temperature sensor comprising: a first MOS transistor having one end connected to a power source, a second MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to ground, and a temperature detection unit providing temperature information based on a voltage of a node where the other end of the first MOS transistor and one end of the second MOS transistor are connected, wherein the first and second MOS transistors are N-MOS transistors or P-MOS transistors, are of the same type, and gates of the first and second MOS transistors are commonly connected.
  • a temperature sensor wherein the first MOS transistor is different from the second MOS transistor in at least one of a gate oxide capacitance per unit area and a channel width.
  • a temperature sensor is disclosed, characterized in that a gate oxide capacitance per unit area of the first MOS transistor is greater than a gate oxide capacitance per unit area of the second MOS transistor.
  • the channel width of the first MOS transistor is greater than the channel width of the second MOS transistor.
  • a temperature sensor characterized by is disclosed.
  • a temperature sensor characterized in that the first and second MOS transistors are N-MOS transistors and the gates are commonly connected to the ground.
  • a temperature sensor characterized in that the first and second MOS transistors are P-MOS transistors and the gates are commonly connected to the power supply.
  • a temperature sensor characterized in that the temperature detection unit includes an amplifier that amplifies a voltage output from a node where the other end of the first MOS transistor and one end of the second MOS transistor are connected, an ADC that converts the voltage output from the amplifier into a digital signal and outputs it, and a digital compensation circuit that linearizes and outputs the digital signal.
  • a temperature sensor characterized in that the temperature detection unit provides temperature information based on the digital signal.
  • a temperature sensor comprising: a first MOS transistor having one end connected to a power source, a second MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to ground, a third MOS transistor having one end connected to the power source, a fourth MOS transistor having one end connected to the other end of the third MOS transistor and the other end connected to ground, and a temperature detection unit providing temperature information based on a voltage difference between a voltage of a node to which the other end of the first MOS transistor and one end of the second MOS transistor are connected and a voltage of a node to which the other end of the third MOS transistor and one end of the fourth MOS transistor are connected, wherein the first and second MOS transistors are N-MOS transistors, the third and fourth MOS transistors are P-MOS transistors, and gates of the first and second MOS transistors are commonly connected to ground, and gates of the third and fourth MOS transistors are commonly connected to a power source
  • a temperature sensor wherein the first MOS transistor has at least one different gate oxide capacitance per unit area and/or channel width from the second MOS transistor, and the third MOS transistor has at least one different gate oxide capacitance per unit area and/or channel width from the fourth MOS transistor.
  • a temperature sensor characterized in that a gate oxide capacitance per unit area of the first MOS transistor is greater than a gate oxide capacitance per unit area of the second MOS transistor, and a gate oxide capacitance per unit area of the third MOS transistor is greater than a gate oxide capacitance per unit area of the fourth MOS transistor.
  • a temperature sensor characterized in that a channel width of the first MOS transistor is larger than a channel width of the second MOS transistor, and a channel width of the third MOS transistor is larger than a channel width of the fourth MOS transistor.
  • a temperature sensor characterized in that the temperature detection unit includes a differential amplifier that amplifies and outputs a difference between a voltage of a node where the other terminal of the first MOS transistor and one terminal of the second MOS transistor are connected and a voltage of a node where the other terminal of the third MOS transistor and one terminal of the fourth MOS transistor are connected, an ADC that converts the voltage output from the amplifier into a digital signal and outputs the digital signal, and a digital compensation circuit that linearizes and outputs the digital signal.
  • a differential amplifier that amplifies and outputs a difference between a voltage of a node where the other terminal of the first MOS transistor and one terminal of the second MOS transistor are connected and a voltage of a node where the other terminal of the third MOS transistor and one terminal of the fourth MOS transistor are connected
  • an ADC that converts the voltage output from the amplifier into a digital signal and outputs the digital signal
  • a digital compensation circuit that linearizes and outputs the digital signal.
  • a temperature sensor characterized in that the temperature detection unit provides temperature information based on the digital signal.
  • the first component may be called the second component, and similarly, the second component may also be called the first component.
  • the first component may be called the second component, and similarly, the second component may also be called the first component.
  • the second component When a component is mentioned as being connected or connected to another component, it should be understood that it may be directly connected or connected to the other component, but there may be other components in between.
  • a component when a component is mentioned as being directly connected or directly connected to another component, it should be understood that there are no other components in between.
  • Other expressions used to describe the relationship between components such as between and directly between or adjacent to and directly adjacent to, should also be interpreted in the same way.
  • FIG. 1 is a circuit diagram of a temperature sensor composed of N-MOS transistors (101, 102) according to an embodiment of the present invention.
  • a temperature sensor may include a first MOS transistor (M1), a second MOS transistor (M2), and a temperature detection unit (110).
  • the first MOS transistor (M1) and the second MOS transistor (M2) are configured as at least one of an N-MOS transistor and a P-MOS transistor, and are configured as the same type.
  • An N-MOS transistor (hereinafter, the first N-MOS transistor) (101) corresponding to the first MOS transistor (M1) may have one end connected to a power supply (V DD ).
  • One end of the first N-MOS transistor (101) may be a drain terminal of the first N-MOS transistor (101).
  • An N-MOS transistor (hereinafter, referred to as a second N-MOS transistor) (102) corresponding to the second MOS transistor (M2) may have one end connected to the other end of the first N-MOS transistor (101).
  • One end of the second N-MOS transistor (102) may be a drain end of the second N-MOS transistor (102), and the other end of the first N-MOS transistor (101) may be a source end of the first N-MOS transistor (101).
  • the other terminal of the second N-MOS transistor (102) is connected to ground, and the other terminal of the second N-MOS transistor (102) may be a source terminal.
  • the gates of the first N-MOS transistor (101) and the second N-MOS transistor (102) can be commonly connected to ground.
  • a leakage current (I s ) may occur in the second N-MOS transistor (102).
  • the leakage current (I s ) is defined by the following [Mathematical Formula 1].
  • A is a parameter determined by the physical characteristics of the transistor, q is the charge, n is the subthreshold slope coefficient, k is the Boltzmann constant, T is the absolute temperature, V TH0 is the threshold voltage, is the DIBL (Drain-Induced Barrier Lowering) coefficient.
  • the parameter (A) determined by the physical characteristics of the transistor is is defined as (where C ox is the zero-bias mobility, W eff is the transistor width, L eff is the transistor length, q is the charge, k is the Boltzmann constant, and T is the absolute temperature.
  • An output voltage (V OUT1 ) may be generated at a node where the other end of the first N-MOS transistor (101) and one end of the second N-MOS transistor (102) are connected due to a leakage current (I s ) generated in the second N-MOS transistor (102) as described above. If the [Mathematical Expression 1] for the leakage current (I s ) is rearranged into an expression for the output voltage ( V OUT1 ) , it can be expressed as the following [Mathematical Expression 2].
  • A1 is a parameter according to the physical characteristics of the first N-MOS transistor (101)
  • A2 is a parameter according to the physical characteristics of the second N-MOS transistor (102)
  • V DD is an input voltage
  • the temperature sensor according to the present invention can set at least one of the gate oxide capacitance per unit area (C ox ) and the transistor channel width (W eff ) of the first N-MOS transistor (101) and the second N-MOS transistor (102) differently.
  • at least one of the gate oxide capacitance per unit area (C ox ) and the transistor channel width (W eff ) of the first N-MOS transistor (101) can be set to be larger than that of the second N-MOS transistor (102).
  • the temperature sensor according to the present invention may include a temperature detection unit (110).
  • the temperature detection unit (110) may provide temperature information based on the voltage (V OUT1 ) of a node to which the other end of the first N-MOS transistor (101) and one end of the second N-MOS transistor (102) are connected.
  • the temperature detection unit (110) may include an amplifier (111) that amplifies a voltage (V OUT1 ) output from a node where the other end of the first N-MOS transistor (101) and one end of the second N-MOS transistor (102) are connected, an ADC (112) that converts the voltage output from the amplifier (111) into a digital signal and outputs it, and a digital compensation circuit (113) that linearizes the digital signal and outputs it.
  • the temperature detection unit (110) may provide temperature information based on the digital signal output from the digital compensation circuit (113).
  • FIG. 2 is a circuit diagram of a temperature sensor composed of P-MOS transistors (103, 104) according to an embodiment of the present invention.
  • the first MOS transistor (M1) and the second MOS transistor (M2) are configured as at least one of an N-MOS transistor and a P-MOS transistor, and are configured as the same type.
  • Fig. 2 a case is described where the first MOS transistor (M1) and the second MOS transistor (M2) are P-MOS transistors (103, 104).
  • a P-MOS transistor (hereinafter, the first P-MOS transistor) (103) corresponding to the first MOS transistor (M1) may have one end connected to a power supply (V DD ).
  • One end of the first P-MOS transistor (103) may be a source terminal of the first P-MOS transistor (103).
  • a P-MOS transistor (hereinafter, referred to as a second P-MOS transistor) (104) corresponding to the second MOS transistor (M2) may have one end connected to the other end of the first P-MOS transistor (103).
  • One end of the second P-MOS transistor (104) may be a source end of the second P-MOS transistor (104), and the other end of the first P-MOS transistor (103) may be a drain end of the first P-MOS transistor (103).
  • the other terminal of the second P-MOS transistor (104) is connected to ground, and the other terminal of the second P-MOS transistor (104) may be a drain terminal.
  • the gates of the first P-MOS transistor (103) and the second P-MOS transistor (104) can be commonly connected to a power supply (V DD ).
  • a leakage current (I s ) may occur in the second P-MOS transistor (104). Similar to the configuration of the N-MOS transistor described with reference to Fig. 1, the leakage current (I s ) is defined by the above [Mathematical Formula 1].
  • An output voltage (V OUT2 ) may be generated at a node where the other end of the first P-MOS transistor (103) and one end of the second P-MOS transistor (104) are connected by a leakage current (I s ) generated by the second P-MOS transistor ( 104).
  • the output voltage (V OUT2 ) is defined by [Mathematical Formula 2]. However, unlike the structure of the N-MOS transistor, in the P-MOS transistor structure, [Mathematical Formula 2] The value has a negative constant value (-C3). If is defined as a positive constant value (C4), the output voltage (V OUT2 ) is It can be summarized as follows.
  • the voltage (V OUT2 ) output from the node where the other end of the first P-MOS transistor (103) and one end of the second P-MOS transistor (104) are connected can obtain a result that is linearly inversely proportional to the temperature (T).
  • T temperature
  • the temperature sensor according to the present invention can set at least one of the gate oxide capacitance per unit area (C ox ) and the transistor channel width (W eff ) of the first P-MOS transistor (103) and the second P-MOS transistor (104) differently.
  • at least one of the gate oxide capacitance per unit area (C ox ) and the transistor channel width (W eff ) of the first P-MOS transistor (103) can be set to be larger than that of the second P-MOS transistor (102).
  • the temperature sensor according to the present invention may include a temperature detection unit (110).
  • the temperature detection unit (110) may provide temperature information based on the voltage (V OUT2 ) of a node to which the other end of the first P-MOS transistor (103) and one end of the second P-MOS transistor (104) are connected.
  • the temperature detection unit (110) may include an amplifier (111) that amplifies a voltage (V OUT2 ) output from a node where the other end of the first P-MOS transistor (103) and one end of the second P-MOS transistor (104) are connected, an ADC (112) that converts the voltage output from the amplifier (111) into a digital signal and outputs it, and a digital compensation circuit (113) that linearizes the digital signal and outputs it.
  • the temperature detection unit (110) may provide temperature information based on the digital signal output from the digital compensation circuit (113).
  • FIG. 3 is a circuit diagram of a temperature sensor configured by merging N-MOS transistors (201, 202) and P-MOS transistors (203, 204) according to an embodiment of the present invention.
  • the temperature sensor of the present invention may include a first MOS transistor (MN1) and a second MOS transistor (MN2) which are N-MOS transistors, a third MOS transistor (MP3) and a fourth MOS transistor (MP4) which are P-MOS transistors, and a temperature detection unit (210).
  • MN1 first MOS transistor
  • MN2 second MOS transistor
  • MP3 third MOS transistor
  • MP4 fourth MOS transistor
  • 210 a temperature detection unit
  • the structure of the N-MOS transistor (201, 202) is the same as that described with reference to Fig. 1, and the structure of the P-MOS transistor (203, 204) is the same as that described with reference to Fig. 2.
  • the temperature detection unit (210) can provide temperature information based on the voltage difference between the voltage of the node connected between the other terminal of the first MOS transistor (MN1) and one terminal of the second MOS transistor (MN2) (hereinafter, the first output voltage (V OUT1 )) and the voltage of the node connected between the other terminal of the third MOS transistor (MP3) and one terminal of the fourth MOS transistor (MP4) (hereinafter, the second output voltage (V OUT2 )).
  • the first output voltage (V OUT1 ) is linearly proportional to the temperature (T)
  • the second output voltage (V OUT2 ) is linearly inversely proportional to the temperature (T), so they are complementary to each other. Therefore, the temperature detection unit (210) can further expand the range of the output voltage according to the temperature (T) by utilizing the difference between the first output voltage (V OUT1 ) and the second output voltage (V OUT2 ).
  • the temperature detection unit (210) may include a differential amplifier (211), an ADC (212), and a digital compensation circuit (213).
  • the differential amplifier (211) may calculate the difference between the first output voltage (V OUT1 ) and the second output voltage (V OUT2 ) and may amplify and output the difference.
  • the ADC (212) may convert the voltage output from the differential amplifier (211) into a digital signal and output it.
  • the digital compensation circuit (213) may linearize and output the digital signal output from the ADC (212).
  • the temperature detection unit (210) may provide temperature information based on the digital signal output from the digital compensation circuit (213).
  • FIG. 4 is a graph showing a measurement voltage in a temperature sensor composed of an N-MOS transistor according to an embodiment of the present invention.
  • the output voltage value according to the threshold voltage (V TH ) of the N-MOS transistor is disclosed.
  • they can be classified into n-lvt (low threshold voltage, Low Voltage Transistor), n-rvt (reference threshold voltage, Regular Voltage Transistor), and n-hvt (high threshold voltage, High Voltage Transistor).
  • the output voltage (V OUT1 ) according to the temperature (T) of the n-lvt corresponds to GN1 as shown in FIG. 4.
  • the output voltage (V OUT1 ) of the n-lvt changes from about 145 mV to 245 mV.
  • the output voltage (V OUT1 ) according to the temperature (T) of n-rvt corresponds to GN2 as shown in Fig. 4.
  • the output voltage (V OUT1 ) of n-rvt changes from about 130 mV to 255 mV.
  • the output voltage (V OUT1 ) according to the temperature (T) of the n-hvt corresponds to GN3 as shown in Fig. 4.
  • the output voltage (V OUT1 ) of the n-hvt changes from about 90mV to 240mV.
  • the output voltage value according to the threshold voltage (V TH ) of the P-MOS transistor is disclosed. Depending on the size of the threshold voltage (V TH ), they can be classified into p-lvt (low threshold voltage, Low Voltage Transistor), p-rvt (reference threshold voltage, Regular Voltage Transistor), and p-hvt (high threshold voltage, High Voltage Transistor).
  • the output voltage (V OUT2 ) according to the temperature (T) of the p-lvt corresponds to GP1 as shown in FIG. 5.
  • the output voltage (V OUT2 ) of the p-lvt changes from about 1000mV to 860mV.
  • the output voltage (V OUT2 ) according to the temperature (T) of the p-rvt corresponds to GP2 as shown in Fig. 5.
  • the output voltage (V OUT2 ) of the p-rvt changes from about 1060mV to 900mV.
  • the output voltage (V OUT2 ) according to the temperature (T) of the p-hvt corresponds to GP3 as shown in Fig. 4.
  • the output voltage (V OUT2 ) of the p-hvt changes from about 1120mV to 950mV.
  • FIG. 6 is a graph showing a measured voltage (V OUT1 ) as the physical characteristics of a first MOS transistor (N-MOS) increase according to one embodiment of the present invention.
  • each output voltage (V OUT1 ) is illustrated.
  • the physical characteristic (A1) is defined as described with reference to FIG. 1.
  • FIG. 6 shows the characteristics of the output voltage (V OUT1 ) when the channel width (transistor width, W eff ) of the transistor is changed among the physical characteristics (A1).
  • NW4 corresponds to the case where the channel width (W1) of the first N-MOS transistor (101) is the largest
  • NW1 corresponds to the case where the channel width (W1) of the first N-MOS transistor (101) is the smallest. It can be confirmed that as the channel width (W1) of the first N-MOS transistor (101) increases, the range of the output voltage (V OUT1 ) according to the change in temperature (T) is wider and more linearly illustrated.
  • FIG. 7 is a graph showing a measured voltage (V OUT2 ) as the physical characteristics of a first MOS transistor (P-MOS) increase according to one embodiment of the present invention.
  • each output voltage (V OUT2 ) is shown when only the physical characteristic (A1) of the first P-MOS transistor (103) is changed.
  • the physical characteristic (A1) is as described with reference to FIG. 1. is defined as.
  • Fig. 7 shows the characteristics of the output voltage (V OUT2 ) when the channel width (transistor width, W eff ) of the transistor among the physical characteristics (A1) is changed.
  • PW4 corresponds to the case where the channel width (W1) of the first P-MOS transistor (103) is the largest
  • PW1 corresponds to the case where the channel width (W1) of the first P-MOS transistor (103) is the smallest. It can be confirmed that as the channel width (W1) of the first P-MOS transistor (103) increases, the range of the output voltage (V OUT2 ) according to the change in temperature (T) becomes wider and more linearly depicted.
  • the temperature sensor according to the present invention has a wider output range of voltage according to temperature change and is more linear, unlike a temperature sensor using a transistor used in the past, it can be used in an environment requiring more precise temperature measurement.

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Abstract

The present invention relates to a temperature sensor that measures temperatures using voltages output from N-MOS and P-MOS transistors having a stack structure. The objective of the present invention is to constitute MOS transistors of the same type to have a stack structure so as to output voltages linear to temperature and to calculate a difference between a voltage that is output from an N-MOS transistor and is proportional to temperature and a voltage that is output from a P-MOS transistor and is inversely proportional to temperature, thereby widening the range of output voltages.

Description

온도 센서Temperature sensor
본 발명은 온도 센서에 관한 것으로, 보다 상세하게는 스택 구조를 갖는 N-MOS 및 P-MOS 트랜지스터에서 출력되는 전압으로 온도를 측정하는 온도 센서에 관한 것이다.The present invention relates to a temperature sensor, and more particularly, to a temperature sensor that measures temperature with a voltage output from an N-MOS and P-MOS transistor having a stack structure.
일반적으로 온도센서로 사용되는 소자로는 써미스터가 대표적이지만 이것은 적용되는 칩을 단일화하고자 하는 경우 공정상 제약을 갖게되므로 단일칩에는 적합하지 않다. 그리고 바이폴라 트랜지스터와 같은 경우에는 IC회로의 설계가 가능하지만 근래에 널리 적용되는 디지털과 아날로그의 회로들이 혼재된 형태의 혼합 IC에는 MOS(Metal Oxide Silicon) 트랜지스터 공정을 주로 사용하므로 바이폴라 트랜지스터의 사용에도 한계가 있다. 특히 디지털온도보상발진기(DTCXO)와 같이 EPROM이 내장된 IC를 설계하고자 할 경우 MOS 트랜지스터 공정을 반드시 사용해야하므로 MOS 트랜지스터 소자를 사용한 온도센서 회로가 절대적으로 필요하다. Thermistors are typically used as temperature sensors, but since they have process constraints when trying to unify the chips to which they are applied, they are not suitable for single chips. In addition, although IC circuit design is possible with bipolar transistors, the use of MOS (Metal Oxide Silicon) transistors is mainly used in hybrid ICs that mix digital and analog circuits, which have been widely used recently, so there are limits to the use of bipolar transistors. In particular, when designing an IC with a built-in EPROM, such as a digital temperature compensation oscillator (DTCXO), the MOS transistor process must be used, so a temperature sensor circuit using a MOS transistor element is absolutely necessary.
MOS 트랜지스터를 이용한 온도센서는 온도에 따라 변화하여 출력되는 전압 또는 전류를 측정하는 것으로 온도를 감지한다. 그러나, 기존의 MOS 트랜지스터를 이용한 온도 센서의 경우 전압 또는 전류의 출력이 온도에 비례하기는 하나 지수함수와 같이 일정 구간에서 급격하게 변화하는 특성을 갖게 된다. 온도 센서에서 출력된 신호는 선형적일수록 디지털 신호로 변화하는 것이 용이하기 때문에 기존 MOS 트랜지스터를 이용한 온도 센서는 디지털 신호로 변환하기 위해 역함수를 취하는 후처리 등이 필요하다. 따라서, 기존 MOS 트랜지스터를 이용한 온도 센서는 후처리 비용이 발생하는 문제 등이 있다. Temperature sensors using MOS transistors detect temperature by measuring the voltage or current output that changes depending on the temperature. However, in the case of temperature sensors using conventional MOS transistors, although the voltage or current output is proportional to the temperature, it has the characteristic of changing rapidly in a certain section like an exponential function. Since the signal output from the temperature sensor is more linear, it is easier to change it into a digital signal, so temperature sensors using conventional MOS transistors require postprocessing such as taking an inverse function to convert it into a digital signal. Therefore, temperature sensors using conventional MOS transistors have problems such as postprocessing costs.
또한, 기존 MOS 트랜지스터를 이용한 온도 센서는 출력 전압의 범위가 굉장히 낮다. 온도 변화에 따른 MOS 트랜지스터의 출력 전압 범위는 온도를 감지하는 감도와 직결되고 출력 전압의 범위가 낮을수록 온도 감지가 예민해져 오차가 발생하기 쉽다. 따라서 온도 변화에 따른 MOS 트랜지스터의 출력 전압 범위를 높일 필요가 있고 기존에는 증폭기 등을 이용하여 출력된 전압을 증폭시키는 등의 후처리 작업을 진행하고 있다. 이러한 후처리 작업은 추가 비용 및 시간이 소요될 뿐만 아니라, 증폭기 성능에 따라 노이즈가 발생할 수 있는 문제점이 있다.In addition, temperature sensors using existing MOS transistors have a very low output voltage range. The output voltage range of the MOS transistor according to temperature change is directly related to the sensitivity of detecting temperature, and the lower the output voltage range, the more sensitive the temperature detection becomes, which makes it easy for errors to occur. Therefore, it is necessary to increase the output voltage range of the MOS transistor according to temperature change, and previously, post-processing work such as amplifying the output voltage using an amplifier, etc. was performed. Such post-processing work not only requires additional cost and time, but also has the problem that noise may occur depending on the performance of the amplifier.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 본 발명의 목적은 동일한 타입의 MOS 트랜지스터를 스택 구조로 구성하여 온도에 선형적인 전압을 출력하고, 온도에 비례하는 N-MOS 트랜지스터에서 출력된 전압과 온도에 반비례하는 P-MOS 트랜지스터에서 출력된 전압 간 차이를 연산하여 출력 전압의 범위를 보다 넓게 하는 것이다.The present invention is to solve the above-mentioned problems, and the purpose of the present invention is to configure MOS transistors of the same type in a stack structure to output a voltage that is linear with respect to temperature, and to calculate the difference between the voltage output from an N-MOS transistor that is proportional to the temperature and the voltage output from a P-MOS transistor that is inversely proportional to the temperature, thereby widening the range of the output voltage.
본 발명의 일 측면에 따르면, 일단이 전원에 연결된 제1 MOS 트랜지스터, 일단이 상기 제1 MOS 트랜지스터의 타단과 연결되고, 타단이 그라운드와 연결된 제2 MOS 트랜지스터, 및 상기 제1 MOS 트랜지스터의 타단과 제2 MOS 트랜지스터의 일단이 연결된 노드의 전압에 기초하여 온도 정보를 제공하는 온도 검출부를 포함하되, 상기 제1 및 제2 MOS 트랜지스터는 N-MOS 트랜지스터 또는 P-MOS 트랜지스터이되, 동일한 타입이고, 상기 제1 및 제2 MOS 트랜지스터의 게이트는 공통으로 연결된 것을 특징으로 하는 온도 센서가 개시된다.According to one aspect of the present invention, a temperature sensor is disclosed, comprising: a first MOS transistor having one end connected to a power source, a second MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to ground, and a temperature detection unit providing temperature information based on a voltage of a node where the other end of the first MOS transistor and one end of the second MOS transistor are connected, wherein the first and second MOS transistors are N-MOS transistors or P-MOS transistors, are of the same type, and gates of the first and second MOS transistors are commonly connected.
본 발명에 따르면, 동일한 타입의 제1 MOS 트랜지스터와 제2 MOS 트랜지스터가 스택구조로 연결되고 제1 MOS 트랜지스터와 제2 MOS 트랜지스터의 게이트가 공통으로 연결되어 제1 MOS 트랜지스터 및 제2 MOS 트랜지스터가 OFF 상태여도 온도 변화에 따른 출력 전압이 발생할 수 있다.According to the present invention, a first MOS transistor and a second MOS transistor of the same type are connected in a stack structure, and the gates of the first MOS transistor and the second MOS transistor are commonly connected, so that an output voltage can be generated according to a temperature change even when the first MOS transistor and the second MOS transistor are in an OFF state.
또한, 본 발명에 따르면, 제2 MOS 트랜지스터에서 발생한 누설전류에 의해 제1 MOS 트랜지스터의 타단과 제2 MOS 트랜지스터의 일단이 연결된 노드에서 온도에 따라 변화하는 전압이 발생할 수 있다.In addition, according to the present invention, a voltage that varies depending on temperature may be generated at a node where the other end of the first MOS transistor and one end of the second MOS transistor are connected due to leakage current generated in the second MOS transistor.
또한, 본 발명에 따르면, 제1 MOS 트랜지스터의 타단과 제2 MOS 트랜지스터의 일단이 연결된 노드에서 온도에 따라 변화하는 전압에 기초하여 온도 정보를 제공할 수 있다.In addition, according to the present invention, temperature information can be provided based on a voltage that changes depending on temperature at a node connected between the other end of the first MOS transistor and one end of the second MOS transistor.
또한, 본 발명에 따르면, 스택구조로 구성되는 복수의 N-MOS 트랜지스터를 통해 온도에 비례하고 선형적인 전압을 출력할 수 있다.In addition, according to the present invention, a voltage proportional to temperature and linearly can be output through a plurality of N-MOS transistors configured in a stack structure.
또한, 본 발명에 따르면, 제1 MOS 트랜지스터의 타단과 제2 MOS 트랜지스터의 일단이 연결된 노드의 전압이 선형적이므로 후처리 비용을 절약할 수 있다.In addition, according to the present invention, since the voltage of the node where the other end of the first MOS transistor and one end of the second MOS transistor are connected is linear, post-processing costs can be saved.
또한, 본 발명에 따르면, 제1 MOS 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area) 내지 채널 폭(Transistor width) 중 적어도 하나를 제2 MOS 트랜지스터 보다 크게 하여 출력 전압의 범위를 넓힐 수 있다.In addition, according to the present invention, the range of the output voltage can be widened by making at least one of the gate oxide capacitance per unit area and the channel width of the first MOS transistor larger than that of the second MOS transistor.
또한, 본 발명에 따르면, 제1 MOS 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area) 내지 채널 폭(Transistor width) 중 적어도 하나를 제2 MOS 트랜지스터 보다 크게 하여 보다 선형적인 전압을 출력할 수 있다.In addition, according to the present invention, at least one of the gate oxide capacitance per unit area and the channel width of the first MOS transistor can be made larger than that of the second MOS transistor, thereby outputting a more linear voltage.
또한, 본 발명에 따르면, 스택구조로 구성되는 복수의 P-MOS 트랜지스터를 통해 온도에 반비례하고 선형적인 전압을 출력할 수 있다.In addition, according to the present invention, a voltage that is inversely proportional to temperature and linear can be output through a plurality of P-MOS transistors configured in a stack structure.
또한, 본 발명에 따르면, 제1 MOS 트랜지스터의 타단과 제2 MOS 트랜지스터의 일단이 연결된 노드의 전압과 제3 MOS 트랜지스터의 타단과 제4 MOS 트랜지스터의 일단이 연결된 노드의 전압 간의 전압 차에 기초하여 온도 정보를 제공할 수 있다.In addition, according to the present invention, temperature information can be provided based on the voltage difference between the voltage of a node connected between the other terminal of the first MOS transistor and one terminal of the second MOS transistor and the voltage of a node connected between the other terminal of the third MOS transistor and one terminal of the fourth MOS transistor.
또한, 본 발명에 따르면, 제1 MOS 트랜지스터의 타단과 제2 MOS 트랜지스터의 일단이 연결된 노드의 전압과 제3 MOS 트랜지스터의 타단과 제4 MOS 트랜지스터의 일단이 연결된 노드의 전압 간의 차이를 이용하여 온도에 따른 출력 전압의 범위를 넓힐 수 있다.In addition, according to the present invention, the range of output voltage according to temperature can be expanded by utilizing the difference between the voltage of the node connected between the other terminal of the first MOS transistor and one terminal of the second MOS transistor and the voltage of the node connected between the other terminal of the third MOS transistor and one terminal of the fourth MOS transistor.
또한, 본 발명에 따르면, 온도 검출부는 온도 변화에 따른 출력 전압을 디지털 신호로 변환하여 가공된 온도 정보를 제공할 수 있다.In addition, according to the present invention, the temperature detection unit can convert an output voltage according to a temperature change into a digital signal to provide processed temperature information.
도 1은 본 발명의 실시예에 따라 N-MOS 트랜지스터로 구성되는 온도 센서의 회로도.FIG. 1 is a circuit diagram of a temperature sensor composed of an N-MOS transistor according to an embodiment of the present invention.
도 2는 본 발명의 실시예에 따라 P-MOS 트랜지스터로 구성되는 온도 센서의 회로도.FIG. 2 is a circuit diagram of a temperature sensor composed of a P-MOS transistor according to an embodiment of the present invention.
도 3은 본 발명의 실시예에 따라 N-MOS 트랜지스터 및 P-MOS 트랜지스터를 병합하여 구성되는 온도 센서의 회로도.FIG. 3 is a circuit diagram of a temperature sensor configured by merging an N-MOS transistor and a P-MOS transistor according to an embodiment of the present invention.
도 4는 본 발명의 실시예에 따라 N-MOS 트랜지스터로 구성되는 온도 센서에 있어서 측정 전압을 나타내는 그래프.FIG. 4 is a graph showing a measurement voltage in a temperature sensor composed of an N-MOS transistor according to an embodiment of the present invention.
도 5는 본 발명의 실시예에 따라 P-MOS 트랜지스터로 구성되는 온도 센서에 있어서 측정 전압을 나타내는 그래프.FIG. 5 is a graph showing a measurement voltage in a temperature sensor composed of a P-MOS transistor according to an embodiment of the present invention.
도 6은 본 발명의 일 실시예에 따라 제1 MOS 트랜지스터(N-MOS)의 물적 특성이 증가함에 따른 측정 전압을 나타내는 그래프.FIG. 6 is a graph showing a measured voltage as the physical characteristics of a first MOS transistor (N-MOS) increase according to one embodiment of the present invention.
도 7은 본 발명의 일 실시예에 따라 제1 MOS 트랜지스터(P-MOS)의 물적 특성이 증가함에 따른 측정 전압을 나타내는 그래프.FIG. 7 is a graph showing a measured voltage as the physical characteristics of a first MOS transistor (P-MOS) increase according to one embodiment of the present invention.
본 발명의 일 측면에 따르면, 일단이 전원에 연결된 제1 MOS 트랜지스터, 일단이 상기 제1 MOS 트랜지스터의 타단과 연결되고, 타단이 그라운드와 연결된 제2 MOS 트랜지스터, 및 상기 제1 MOS 트랜지스터의 타단과 제2 MOS 트랜지스터의 일단이 연결된 노드의 전압에 기초하여 온도 정보를 제공하는 온도 검출부를 포함하되, 상기 제1 및 제2 MOS 트랜지스터는 N-MOS 트랜지스터 또는 P-MOS 트랜지스터이되, 동일한 타입이고, 상기 제1 및 제2 MOS 트랜지스터의 게이트는 공통으로 연결된 것을 특징으로 하는 온도 센서가 개시된다.According to one aspect of the present invention, a temperature sensor is disclosed, comprising: a first MOS transistor having one end connected to a power source, a second MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to ground, and a temperature detection unit providing temperature information based on a voltage of a node where the other end of the first MOS transistor and one end of the second MOS transistor are connected, wherein the first and second MOS transistors are N-MOS transistors or P-MOS transistors, are of the same type, and gates of the first and second MOS transistors are commonly connected.
실시예에 따라서, 상기 제1 MOS 트랜지스터는, 상기 제2 MOS 트랜지스터와 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area) 내지 채널 폭(Transistor width) 중 적어도 하나가 서로 상이한 것을 특징으로 하는 온도 센서가 개시된다.According to an embodiment, a temperature sensor is disclosed, wherein the first MOS transistor is different from the second MOS transistor in at least one of a gate oxide capacitance per unit area and a channel width.
실시예에 따라서, 상기 제1 MOS 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area)은 상기 제2 MOS 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area) 보다 큰 것을 특징으로 하는 온도 센서가 개시된다.According to an embodiment, a temperature sensor is disclosed, characterized in that a gate oxide capacitance per unit area of the first MOS transistor is greater than a gate oxide capacitance per unit area of the second MOS transistor.
실시예에 따라서, 상기 제1 MOS 트랜지스터의 채널 폭(Transistor width)은 상기 제2 MOS 트랜지스터의 채널 폭(Transistor width) 보다 큰 것According to an embodiment, the channel width of the first MOS transistor is greater than the channel width of the second MOS transistor.
을 특징으로 하는 온도 센서가 개시된다.A temperature sensor characterized by is disclosed.
실시예에 따라서, 상기 제1 및 제2 MOS 트랜지스터는, N-MOS 트랜지스터이고, 상기 게이트가 공통으로 상기 그라운드에 연결된 것을 특징으로 하는 온도 센서가 개시된다.According to an embodiment, a temperature sensor is disclosed, characterized in that the first and second MOS transistors are N-MOS transistors and the gates are commonly connected to the ground.
실시예에 따라서, 상기 제1 및 제2 MOS 트랜지스터는, P-MOS 트랜지스터이고, 상기 게이트가 공통으로 상기 전원에 연결된 것을 특징으로 하는 온도 센서가 개시된다.According to an embodiment, a temperature sensor is disclosed, characterized in that the first and second MOS transistors are P-MOS transistors and the gates are commonly connected to the power supply.
실시예에 따라서, 상기 온도 검출부는, 상기 제1 MOS 트랜지스터의 타단과 제2 MOS 트랜지스터의 일단이 연결된 노드에서 출력된 전압을 증폭하는 증폭기, 상기 증폭기에서 출력된 전압을 디지털 신호로 변환하여 출력하는 ADC 및 상기 디지털 신호를 선형화하여 출력하는 디지털 보정 회로를 포함하는 것을 특징으로 하는 온도 센서가 개시된다.According to an embodiment, a temperature sensor is disclosed, characterized in that the temperature detection unit includes an amplifier that amplifies a voltage output from a node where the other end of the first MOS transistor and one end of the second MOS transistor are connected, an ADC that converts the voltage output from the amplifier into a digital signal and outputs it, and a digital compensation circuit that linearizes and outputs the digital signal.
실시예에 따라서, 상기 온도 검출부는, 상기 디지털 신호에 기초하여 온도 정보를 제공하는 것을 특징으로 하는 온도 센서가 개시된다. According to an embodiment, a temperature sensor is disclosed, characterized in that the temperature detection unit provides temperature information based on the digital signal.
본 발명의 다른 측면에 따르면, 일단이 전원에 연결된 제1 MOS 트랜지스터, 일단이 상기 제1 MOS 트랜지스터의 타단과 연결되고, 타단이 그라운드와 연결된 제2 MOS 트랜지스터, 일단이 전원에 연결된 제3 MOS 트랜지스터, 일단이 상기 제3 MOS 트랜지스터의 타단과 연결되고, 타단이 그라운드와 연결된 제4 MOS 트랜지스터 및 상기 제1 MOS 트랜지스터의 타단과 제2 MOS 트랜지스터의 일단이 연결된 노드의 전압과 상기 제3 MOS 트랜지스터의 타단과 제4 MOS 트랜지스터의 일단이 연결된 노드의 전압 간의 전압차에 기초하여 온도 정보를 제공하는 온도 검출부를 포함하되, 상기 제1 및 제2 MOS 트랜지스터는 N-MOS 트랜지스터이고, 상기 제3 및 제4 MOS 트랜지스터는 P-MOS 트랜지스터이며, 상기 제1 및 제2 MOS 트랜지스터의 게이트는 공통으로 그라운드에 연결되고, 상기 제3 및 제4 MOS 트랜지스터의 게이트는 공통으로 전원에 연결된 것을 특징으로 하는 온도 센서가 개시된다.According to another aspect of the present invention, a temperature sensor is disclosed, comprising: a first MOS transistor having one end connected to a power source, a second MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to ground, a third MOS transistor having one end connected to the power source, a fourth MOS transistor having one end connected to the other end of the third MOS transistor and the other end connected to ground, and a temperature detection unit providing temperature information based on a voltage difference between a voltage of a node to which the other end of the first MOS transistor and one end of the second MOS transistor are connected and a voltage of a node to which the other end of the third MOS transistor and one end of the fourth MOS transistor are connected, wherein the first and second MOS transistors are N-MOS transistors, the third and fourth MOS transistors are P-MOS transistors, and gates of the first and second MOS transistors are commonly connected to ground, and gates of the third and fourth MOS transistors are commonly connected to a power source.
실시예에 따라서, 상기 제1 MOS 트랜지스터는, 상기 제2 MOS 트랜지스터와 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area) 내지 채널 폭(Transistor width) 중 적어도 하나가 서로 상이하고, 상기 제3 MOS 트랜지스터는, 상기 제4 MOS 트랜지스터와 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area) 내지 채널 폭(Transistor width) 중 적어도 하나가 서로 상이한 것을 특징으로 하는 온도 센서가 개시된다.According to an embodiment, a temperature sensor is disclosed, wherein the first MOS transistor has at least one different gate oxide capacitance per unit area and/or channel width from the second MOS transistor, and the third MOS transistor has at least one different gate oxide capacitance per unit area and/or channel width from the fourth MOS transistor.
실시예에 따라서, 상기 제1 MOS 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area)은 상기 제2 MOS 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area) 보다 크고, 상기 제3 MOS 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area)은 상기 제4 MOS 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area) 보다 큰 것을 특징으로 하는 온도 센서가 개시된다.According to an embodiment, a temperature sensor is disclosed, characterized in that a gate oxide capacitance per unit area of the first MOS transistor is greater than a gate oxide capacitance per unit area of the second MOS transistor, and a gate oxide capacitance per unit area of the third MOS transistor is greater than a gate oxide capacitance per unit area of the fourth MOS transistor.
실시예에 따라서, 상기 제1 MOS 트랜지스터의 채널 폭(Transistor width)은 상기 제2 MOS 트랜지스터의 채널 폭(Transistor width) 보다 크고, 상기 제3 MOS 트랜지스터의 채널 폭(Transistor width)은 상기 제4 MOS 트랜지스터의 채널 폭(Transistor width) 보다 큰 것을 특징으로 하는 온도 센서가 개시된다.According to an embodiment, a temperature sensor is disclosed, characterized in that a channel width of the first MOS transistor is larger than a channel width of the second MOS transistor, and a channel width of the third MOS transistor is larger than a channel width of the fourth MOS transistor.
실시예에 따라서, 상기 온도 검출부는, 상기 제1 MOS 트랜지스터의 타단과 제2 MOS 트랜지스터의 일단이 연결된 노드의 전압과 상기 제3 MOS 트랜지스터의 타단과 제4 MOS 트랜지스터의 일단이 연결된 노드의 전압 간의 차이를 증폭하여 출력하는 차동증폭기, 상기 증폭기에서 출력된 전압을 디지털 신호로 변환하여 출력하는 ADC 및 상기 디지털 신호를 선형화하여 출력하는 디지털 보정 회로를 포함하는 것을 특징으로 하는 온도 센서가 개시된다.According to an embodiment, a temperature sensor is disclosed, characterized in that the temperature detection unit includes a differential amplifier that amplifies and outputs a difference between a voltage of a node where the other terminal of the first MOS transistor and one terminal of the second MOS transistor are connected and a voltage of a node where the other terminal of the third MOS transistor and one terminal of the fourth MOS transistor are connected, an ADC that converts the voltage output from the amplifier into a digital signal and outputs the digital signal, and a digital compensation circuit that linearizes and outputs the digital signal.
실시예에 따라서, 상기 온도 검출부는, 상기 디지털 신호에 기초하여 온도 정보를 제공하는 것을 특징으로 하는 온도 센서가 개시된다.According to an embodiment, a temperature sensor is disclosed, characterized in that the temperature detection unit provides temperature information based on the digital signal.
상술한 본 발명의 목적, 특징 및 장점은 첨부된 도면과 관련한 다음의 실시예를 통하여 보다 분명해질 것이다. 이하의 특정한 구조 내지 기능적 설명들은 단지 본 발명의 개념에 다른 실시예를 설명하기 위한 목적으로 예시된 것으로, 본 발명의 개념에 따른 실시예들은 다양한 형태로 실시될 수 있으며 본 명세서 또는 출원에 설명된 실시예들에 한정되는 것으로 해석되어서는 아니 된다. 본 발명의 개념에 따른 실시예는 다양한 변경을 가할 수 있고 여러 가지 형태를 가질 수 있으므로 특정 실시예들은 도면에 예시하고 본 명세서 또는 출원에 상세하게 설명하고자 한다. 그러나 이는 본 발명의 개념에 따른 실시예들을 특정한 개시 형태에 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변경, 균등물 내지 대체물을 포함하는 것으로 이해되어야 한다. 제1 및 /또는 제2 등의 용어는 다양한 구성 요소들을 설명하는데 사용될 수 있지만, 상기 구성 요소들은 상기 용어들에 한정되지는 않는다. 상기 용어들은 하나의 구성 요소를 다른 구성 요소들로부터 구별하는 목적으로만, 예컨대 본 발명의 개념에 따른 권리 범위로부터 이탈되지 않은 채, 제1 구성 요소는 제2 구성 요소로 명명될 수 있고, 유사하게 제2 구성 요소는 제1 구성 요소로도 명명될 수 있다. 어떠한 구성 요소가 다른 구성 요소에 연결되어 있다거나 접속되어 있다고 언급된 때에는, 그 다른 구성 요소에 직접적으로 연결되어 있거나 또는 접속되어 있을 수도 있지만, 중간에 다른 구성 요소가 존재할 수도 있다고 이해되어야 할 것이다. 반면에, 어떠한 구성 요소가 다른 구성 요소에 직접 연결되어 있다거나 또는 직접 접속되어 있다고 언급된 때에는, 중간에 다른 구성 요소가 존재하지 않는 것으로 이해되어야 할 것이다. 구성요소들 간의 관계를 설명하기 위한 다른 표현들, 즉 ～사이에와 바로 ～사이에 또는 ～에 인접하는과 ～에 직접 인접하는 등의 표현도 마찬가지로 해석되어야 한다. 본 명세서에서 사용하는 용어는 단지 특정한 실시예를 설명하기 위해 사용된 것으로서, 본 발명을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함한다. 본 명세서에서 포함하다 또는 가지다 등의 용어는 설시된 특징, 숫자, 단계, 동작, 구성 요소, 부분품 또는 이들을 조합한 것이 존재함을 지정하려는 것이지, 하나 또는 그 이상의 다른 특징들이나 숫자, 단계, 동작, 구성 요소, 부분품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해되어야 한다. 다르게 정의되지 않는 한, 기술적이거나 과학적인 용어를 포함해서 여기서 사용되는 모든 용어들은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 일반적으로 이해되는 것과 동일한 의미를 가지고 있다. 일반적으로 사용되는 사전에 정의되어 있는 것과 같은 용어들은 관련 기술의 문맥상 가지는 의미와 일치하는 의미를 갖는 것으로 해석되어야 하며, 본 명세서에서 명백하게 정의하지 않는 한, 이상적이거나 과도하게 형식적인 의미로 해석되지 않는다. 이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명함으로써 본 발명을 상세히 설명하도록 한다. 각 도면에 제시된 동일한 참조부호는 동일한 부재를 나타낸다.The purpose, features and advantages of the present invention described above will become more apparent through the following examples with reference to the accompanying drawings. The specific structural and functional descriptions below are merely exemplified for the purpose of explaining other embodiments of the present invention, and the embodiments according to the present invention may be implemented in various forms and should not be construed as being limited to the embodiments described in this specification or application. Since the embodiments according to the present invention may have various modifications and may have various forms, specific embodiments will be illustrated in the drawings and described in detail in this specification or application. However, this is not intended to limit the embodiments according to the present invention to specific disclosed forms, and should be understood to include all modifications, equivalents or substitutes included in the spirit and technical scope of the present invention. The terms first and/or second, etc. may be used to describe various components, but the components are not limited to the terms. The above terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of rights according to the concept of the present invention, the first component may be called the second component, and similarly, the second component may also be called the first component. When a component is mentioned as being connected or connected to another component, it should be understood that it may be directly connected or connected to the other component, but there may be other components in between. On the other hand, when a component is mentioned as being directly connected or directly connected to another component, it should be understood that there are no other components in between. Other expressions used to describe the relationship between components, such as between and directly between or adjacent to and directly adjacent to, should also be interpreted in the same way. The terminology used herein is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this specification, the terms “include” or “have” are intended to indicate the presence of a described feature, number, step, operation, component, part, or combination thereof, but should be understood as not excluding in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which this invention belongs. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and shall not be interpreted in an ideal or overly formal sense unless explicitly defined herein. Hereinafter, the present invention will be described in detail by describing a preferred embodiment of the present invention with reference to the accompanying drawings. The same reference numerals presented in each drawing represent the same elements.
도 1은 본 발명의 실시예에 따라 N-MOS 트랜지스터(101, 102)로 구성되는 온도 센서의 회로도이다.FIG. 1 is a circuit diagram of a temperature sensor composed of N-MOS transistors (101, 102) according to an embodiment of the present invention.
본 발명의 일 실시예에 따른 온도 센서는 제1 MOS 트랜지스터(M1), 제2 MOS 트랜지스터(M2) 및 온도 검출부(110)를 포함할 수 있다. 본 발명의 실시예에 따라 제1 MOS 트랜지스터(M1) 및 제2 MOS 트랜지스터(M2)는 N-MOS 트랜지스터 및 P-MOS 트랜지스터 중 적어도 하나로 구성되되, 서로 동일한 타입으로 구성된다. 먼저 도 1을 참조하여, 제1 MOS 트랜지스터(M1) 및 제2 MOS 트랜지스터(M2)가 N-MOS 트랜지스터(101, 102)인 경우를 설명한다. A temperature sensor according to one embodiment of the present invention may include a first MOS transistor (M1), a second MOS transistor (M2), and a temperature detection unit (110). According to an embodiment of the present invention, the first MOS transistor (M1) and the second MOS transistor (M2) are configured as at least one of an N-MOS transistor and a P-MOS transistor, and are configured as the same type. First, referring to FIG. 1, a case where the first MOS transistor (M1) and the second MOS transistor (M2) are N-MOS transistors (101, 102) will be described.
제1 MOS 트랜지스터(M1)에 대응되는 N-MOS 트랜지스터(이하, 제1 N-MOS 트랜지스터)(101)는 일단이 전원(VDD)과 연결될 수 있다. 제1 N-MOS 트랜지스터(101)의 일단은 제1 N-MOS 트랜지스터(101)의 드레인(Drain)단 일 수 있다. An N-MOS transistor (hereinafter, the first N-MOS transistor) (101) corresponding to the first MOS transistor (M1) may have one end connected to a power supply (V DD ). One end of the first N-MOS transistor (101) may be a drain terminal of the first N-MOS transistor (101).
제2 MOS 트랜지스터(M2)에 대응되는 N-MOS 트랜지스터(이하, 제2 N-MOS 트랜지스터)(102)는 일단이 제1 N-MOS 트랜지스터(101)의 타단과 연결될 수 있다. 제2 N-MOS 트랜지스터(102)의 일단은 제2 N-MOS 트랜지스터(102)의 드레인(Drain)단 일 수 있고, 제1 N-MOS 트랜지스터(101)의 타단은 제1 N-MOS 트랜지스터(101)의 소스(Source)단 일 수 있다.An N-MOS transistor (hereinafter, referred to as a second N-MOS transistor) (102) corresponding to the second MOS transistor (M2) may have one end connected to the other end of the first N-MOS transistor (101). One end of the second N-MOS transistor (102) may be a drain end of the second N-MOS transistor (102), and the other end of the first N-MOS transistor (101) may be a source end of the first N-MOS transistor (101).
제2 N-MOS 트랜지스터(102)의 타단은 그라운드에 연결되며, 제2 N-MOS 트랜지스터(102)의 타단은 소스(Source)단 일 수 있다.The other terminal of the second N-MOS transistor (102) is connected to ground, and the other terminal of the second N-MOS transistor (102) may be a source terminal.
또한, 제1 N-MOS 트랜지스터(101) 및 제2 N-MOS 트랜지스터(102)의 게이트는 공통으로 그라운드에 연결될 수 있다. Additionally, the gates of the first N-MOS transistor (101) and the second N-MOS transistor (102) can be commonly connected to ground.
이러한 스택 구조를 갖는 제1 N-MOS 트랜지스터(101) 및 제2 N-MOS 트랜지스터(102)에 의하여 각 트랜지스터가 OFF 상태일 때, 제2 N-MOS 트랜지스터(102)에서 누설전류(Is)가 발생할 수 있다. 누설전류(Is)는 다음 [수학식 1]로 정의된다.When each transistor is in an OFF state due to the first N-MOS transistor (101) and the second N-MOS transistor (102) having such a stack structure, a leakage current (I s ) may occur in the second N-MOS transistor (102). The leakage current (I s ) is defined by the following [Mathematical Formula 1].
[수학식 1][Mathematical Formula 1]
Figure PCTKR2023003369-appb-img-000001
Figure PCTKR2023003369-appb-img-000001
A는 트랜지스터의 물적 특성에 따라 결정되는 파라미터, q는 전하량, n은 하위 임계값 기울기 계수(Subthreshold slope coefficient), k는 볼쯔만 상수(Boltzmann constant), T는 절대온도(Absolute Temperature), VTH0는 문턱전압,
Figure PCTKR2023003369-appb-img-000002
는 DIBL(Drain-Induced Barrier Lowering) 계수이다. A is a parameter determined by the physical characteristics of the transistor, q is the charge, n is the subthreshold slope coefficient, k is the Boltzmann constant, T is the absolute temperature, V TH0 is the threshold voltage,
Figure PCTKR2023003369-appb-img-000002
is the DIBL (Drain-Induced Barrier Lowering) coefficient.
여기서, 트랜지스터의 물적 특성에 따라 결정되는 파라미터(A)는
Figure PCTKR2023003369-appb-img-000003
로 정의된다. (
Figure PCTKR2023003369-appb-img-000004
는 전자의 이동도(zero-bias mobility), Cox는 게이트 산화 용량(gate oxide capacitance per unit area), Weff는 트랜지스터 채널 폭(transistor width), Leff는 트랜지스터 채널 깊이(transistor length), q는 전하량, k는 볼쯔만 상수, T는 절대온도)Here, the parameter (A) determined by the physical characteristics of the transistor is
Figure PCTKR2023003369-appb-img-000003
is defined as (
Figure PCTKR2023003369-appb-img-000004
where C ox is the zero-bias mobility, W eff is the transistor width, L eff is the transistor length, q is the charge, k is the Boltzmann constant, and T is the absolute temperature.
위와 같은 제2 N-MOS 트랜지스터(102)에서 발생된 누설전류(Is)에 의해 제1 N-MOS 트랜지스터(101)의 타단과 제2 N-MOS 트랜지스터(102)의 일단이 연결된 노드에서 출력 전압(VOUT1)이 발생할 수 있다. 상기 누설전류(Is)에 대한 [수학식 1]을 출력 전압(VOUT1)에 대한 식으로 정리하면 다음 [수학식 2]로 나타낼 수 있다.An output voltage (V OUT1 ) may be generated at a node where the other end of the first N-MOS transistor (101) and one end of the second N-MOS transistor (102) are connected due to a leakage current (I s ) generated in the second N-MOS transistor (102) as described above. If the [Mathematical Expression 1] for the leakage current (I s ) is rearranged into an expression for the output voltage ( V OUT1 ) , it can be expressed as the following [Mathematical Expression 2].
[수학식 2][Mathematical formula 2]
Figure PCTKR2023003369-appb-img-000005
Figure PCTKR2023003369-appb-img-000005
A1은 제1 N-MOS 트랜지스터(101)의 물적 특성에 의한 파라미터, A2는 제2 N-MOS 트랜지스터(102)의 물적 특성에 의한 파라미터, VDD는 입력전압이다. A1 is a parameter according to the physical characteristics of the first N-MOS transistor (101), A2 is a parameter according to the physical characteristics of the second N-MOS transistor (102), and V DD is an input voltage.
[수학식 2]에서
Figure PCTKR2023003369-appb-img-000006
는 양의 상수 값(C1)을 갖고,
Figure PCTKR2023003369-appb-img-000007
는 양의 상수 값(C2)을 갖기 때문에
Figure PCTKR2023003369-appb-img-000008
으로 정리할 수 있다. 즉, 제1 N-MOS 트랜지스터(101)의 타단과 제2 N-MOS 트랜지스터(102)의 일단이 연결된 노드에서 출력되는 전압(VOUT1)은 온도(T)에 선형적으로 비례하는 결과를 얻을 수 있다. 이후에, 도 4를 참조하여 출력전압(VOUT1)과 온도(T)의 관계를 실제 측정 결과와 함께 상세히 설명한다. In [Mathematical Formula 2]
Figure PCTKR2023003369-appb-img-000006
has a positive constant value (C1),
Figure PCTKR2023003369-appb-img-000007
Since has a positive constant value (C2)
Figure PCTKR2023003369-appb-img-000008
It can be summarized as follows. That is, the voltage (V OUT1 ) output from the node where the other end of the first N-MOS transistor (101) and one end of the second N-MOS transistor (102) are connected can obtain a result that is linearly proportional to the temperature (T). Hereinafter, with reference to FIG. 4, the relationship between the output voltage (V OUT1 ) and the temperature (T) will be described in detail along with actual measurement results.
또한, [수학식 2]에서 출력전압(VOUT1)과 온도(T)의 관계는 제1 N-MOS 트랜지스터(101)의 물적 특성(A1) 및 제2 N-MOS 트랜지스터(102)의 물적 특성(A2)과 관계가 있음을 알 수 있다. 온도(T)에 따른 출력 전압(VOUT1)의 변화량
Figure PCTKR2023003369-appb-img-000009
는 다음 [수학식 3]으로 정의된다.In addition, it can be seen that the relationship between the output voltage (V OUT1 ) and the temperature (T) in [Mathematical Formula 2] is related to the physical characteristics (A 1 ) of the first N-MOS transistor (101) and the physical characteristics (A 2 ) of the second N-MOS transistor (102). The amount of change in the output voltage (V OUT1 ) according to the temperature (T)
Figure PCTKR2023003369-appb-img-000009
is defined by the following [Mathematical Formula 3].
[수학식 3][Mathematical Formula 3]
Figure PCTKR2023003369-appb-img-000010
(
Figure PCTKR2023003369-appb-img-000011
는 선형화된 바디효과 계수(linearized body effect coefficient))
Figure PCTKR2023003369-appb-img-000010
(
Figure PCTKR2023003369-appb-img-000011
is the linearized body effect coefficient)
즉, 제1 N-MOS 트랜지스터(101)의 물적 특성(A1)이 제2 N-MOS 트랜지스터(102)의 물적 특성(A2)보다 클수록 온도(T)에 따른 출력 전압(VOUT1)의 변화량이 증가하고 이는 출력 전압(VOUT1)의 범위가 증가하며 보다 선형적으로 출력되는 효과가 있다. 여기서, 물적 특성(A)는
Figure PCTKR2023003369-appb-img-000012
로 정의됨에 따라 본 발명에 따른 온도 센서는 제1 N-MOS 트랜지스터(101)와 제2 N-MOS 트랜지스터(102)의 게이트 산화 용량(gate oxide capacitance per unit area, Cox) 내지 트랜지스터 채널 폭(transistor width, Weff) 중 적어도 하나를 상이하게 설정할 수 있다. 또한, 제1 N-MOS 트랜지스터(101)의 게이트 산화 용량(gate oxide capacitance per unit area, Cox) 내지 트랜지스터 채널 폭(transistor width, Weff) 중 적어도 하나는 제2 N-MOS 트랜지스터(102)보다 크게 설정될 수 있다.That is, as the material characteristic (A 1 ) of the first N-MOS transistor (101) is greater than the material characteristic (A 2 ) of the second N-MOS transistor (102), the amount of change in the output voltage (V OUT1 ) according to the temperature (T) increases, which has the effect of increasing the range of the output voltage (V OUT1 ) and making it output more linearly. Here, the material characteristic (A) is
Figure PCTKR2023003369-appb-img-000012
As defined, the temperature sensor according to the present invention can set at least one of the gate oxide capacitance per unit area (C ox ) and the transistor channel width (W eff ) of the first N-MOS transistor (101) and the second N-MOS transistor (102) differently. In addition, at least one of the gate oxide capacitance per unit area (C ox ) and the transistor channel width (W eff ) of the first N-MOS transistor (101) can be set to be larger than that of the second N-MOS transistor (102).
또한, 본 발명에 따른 온도 센서는 온도 검출부(110)를 포함할 수 있다. 온도 검출부(110)는 제1 N-MOS 트랜지스터(101)의 타단과 제2 N-MOS 트랜지스터(102)의 일단이 연결된 노드의 전압(VOUT1)에 기초하여 온도 정보를 제공할 수 있다. In addition, the temperature sensor according to the present invention may include a temperature detection unit (110). The temperature detection unit (110) may provide temperature information based on the voltage (V OUT1 ) of a node to which the other end of the first N-MOS transistor (101) and one end of the second N-MOS transistor (102) are connected.
또한, 온도 검출부(110)는 제1 N-MOS 트랜지스터(101)의 타단과 제2 N-MOS 트랜지스터(102)의 일단이 연결된 노드에서 출력된 전압(VOUT1)을 증폭하는 증폭기(111), 증폭기(111)에서 출력된 전압을 디지털 신호로 변환하여 출력하는 ADC(112) 및 디지털 신호를 선형화하여 출력하는 디지털 보정 회로(113)를 포함할 수 있다. 온도 검출부(110)는 디지털 보정 회로(113)에서 출력된 디지털 신호에 기초하여 온도 정보를 제공할 수 있다.In addition, the temperature detection unit (110) may include an amplifier (111) that amplifies a voltage (V OUT1 ) output from a node where the other end of the first N-MOS transistor (101) and one end of the second N-MOS transistor (102) are connected, an ADC (112) that converts the voltage output from the amplifier (111) into a digital signal and outputs it, and a digital compensation circuit (113) that linearizes the digital signal and outputs it. The temperature detection unit (110) may provide temperature information based on the digital signal output from the digital compensation circuit (113).
도 2는 본 발명의 실시예에 따라 P-MOS 트랜지스터(103, 104)로 구성되는 온도 센서의 회로도이다. FIG. 2 is a circuit diagram of a temperature sensor composed of P-MOS transistors (103, 104) according to an embodiment of the present invention.
본 발명의 실시예에 따라 제1 MOS 트랜지스터(M1) 및 제2 MOS 트랜지스터(M2)는 N-MOS 트랜지스터 및 P-MOS 트랜지스터 중 적어도 하나로 구성되되, 서로 동일한 타입으로 구성된다. 도 2에서는, 제1 MOS 트랜지스터(M1) 및 제2 MOS 트랜지스터(M2)가 P-MOS 트랜지스터(103, 104)인 경우를 설명한다. According to an embodiment of the present invention, the first MOS transistor (M1) and the second MOS transistor (M2) are configured as at least one of an N-MOS transistor and a P-MOS transistor, and are configured as the same type. In Fig. 2, a case is described where the first MOS transistor (M1) and the second MOS transistor (M2) are P-MOS transistors (103, 104).
제1 MOS 트랜지스터(M1)에 대응되는 P-MOS 트랜지스터(이하, 제1 P-MOS 트랜지스터)(103)는 일단이 전원(VDD)과 연결될 수 있다. 제1 P-MOS 트랜지스터(103)의 일단은 제1 P-MOS 트랜지스터(103)의 소스(Source)단 일 수 있다. A P-MOS transistor (hereinafter, the first P-MOS transistor) (103) corresponding to the first MOS transistor (M1) may have one end connected to a power supply (V DD ). One end of the first P-MOS transistor (103) may be a source terminal of the first P-MOS transistor (103).
제2 MOS 트랜지스터(M2)에 대응되는 P-MOS 트랜지스터(이하, 제2 P-MOS 트랜지스터)(104)는 일단이 제1 P-MOS 트랜지스터(103)의 타단과 연결될 수 있다. 제2 P-MOS 트랜지스터(104)의 일단은 제2 P-MOS 트랜지스터(104)의 소스(Source)단 일 수 있고, 제1 P-MOS 트랜지스터(103)의 타단은 제1 P-MOS 트랜지스터(103)의 드레인(Drain)단 일 수 있다.A P-MOS transistor (hereinafter, referred to as a second P-MOS transistor) (104) corresponding to the second MOS transistor (M2) may have one end connected to the other end of the first P-MOS transistor (103). One end of the second P-MOS transistor (104) may be a source end of the second P-MOS transistor (104), and the other end of the first P-MOS transistor (103) may be a drain end of the first P-MOS transistor (103).
제2 P-MOS 트랜지스터(104)의 타단은 그라운드에 연결되며, 제2 P-MOS 트랜지스터(104)의 타단은 드레인(Drain)단 일 수 있다.The other terminal of the second P-MOS transistor (104) is connected to ground, and the other terminal of the second P-MOS transistor (104) may be a drain terminal.
또한, 제1 P-MOS 트랜지스터(103) 및 제2 P-MOS 트랜지스터(104)의 게이트는 공통으로 전원(VDD)에 연결될 수 있다. Additionally, the gates of the first P-MOS transistor (103) and the second P-MOS transistor (104) can be commonly connected to a power supply (V DD ).
이러한 스택 구조를 갖는 제1 P-MOS 트랜지스터(103) 및 제2 P-MOS 트랜지스터(104)에 의하여 각 트랜지스터가 OFF 상태일 때, 제2 P-MOS 트랜지스터(104)에서 누설전류(Is)가 발생할 수 있다. 도 1을 참조하여 설명한 N-MOS 트랜지스터의 구성과 마찬가지로 누설전류(Is)는 상기 [수학식 1]로 정의된다.When each transistor is in the OFF state due to the first P-MOS transistor (103) and the second P-MOS transistor (104) having such a stack structure, a leakage current (I s ) may occur in the second P-MOS transistor (104). Similar to the configuration of the N-MOS transistor described with reference to Fig. 1, the leakage current (I s ) is defined by the above [Mathematical Formula 1].
제2 P-MOS 트랜지스터(104)에 의해 발생된 누설전류(Is)에 의해 제1 P-MOS 트랜지스터(103)의 타단과 제2 P-MOS 트랜지스터(104)의 일단이 연결된 노드에서 출력 전압(VOUT2)이 발생할 수 있다. 출력 전압(VOUT2)은 [수학식 2]로 정의된다. 다만, N-MOS 트랜지스터의 구조와 달리 P-MOS 트랜지스터 구조에서는 [수학식 2]의
Figure PCTKR2023003369-appb-img-000013
값이 음의 상수 값(-C3)을 갖는다.
Figure PCTKR2023003369-appb-img-000014
는 양의 상수 값(C4)로 정의하면 출력 전압(VOUT2)은
Figure PCTKR2023003369-appb-img-000015
로 정리할 수 있다. 즉, 제1 P-MOS 트랜지스터(103)의 타단과 제2 P-MOS 트랜지스터(104)의 일단이 연결된 노드에서 출력되는 전압(VOUT2)은 온도(T)에 선형적으로 반비례하는 결과를 얻을 수 있다. 이하, 도 5를 참조하여 출력전압(VOUT2)과 온도(T)의 관계를 실제 측정 결과와 함께 상세히 설명한다. An output voltage (V OUT2 ) may be generated at a node where the other end of the first P-MOS transistor (103) and one end of the second P-MOS transistor (104) are connected by a leakage current (I s ) generated by the second P-MOS transistor ( 104). The output voltage (V OUT2 ) is defined by [Mathematical Formula 2]. However, unlike the structure of the N-MOS transistor, in the P-MOS transistor structure, [Mathematical Formula 2]
Figure PCTKR2023003369-appb-img-000013
The value has a negative constant value (-C3).
Figure PCTKR2023003369-appb-img-000014
If is defined as a positive constant value (C4), the output voltage (V OUT2 ) is
Figure PCTKR2023003369-appb-img-000015
It can be summarized as follows. That is, the voltage (V OUT2 ) output from the node where the other end of the first P-MOS transistor (103) and one end of the second P-MOS transistor (104) are connected can obtain a result that is linearly inversely proportional to the temperature (T). Hereinafter, with reference to FIG. 5, the relationship between the output voltage (V OUT2 ) and the temperature (T) will be described in detail along with actual measurement results.
또한, [수학식 2]에 따라 출력전압(VOUT2)과 온도(T)의 관계는 제1 P-MOS 트랜지스터(103)의 물적 특성(A1) 및 제2 P-MOS 트랜지스터(104)의 물적 특성(A2)과 관계가 있음을 알 수 있다. 온도(T)에 따른 출력 전압(VOUT2)의 변화량
Figure PCTKR2023003369-appb-img-000016
는 다음 [수학식 4]로 정의된다.In addition, according to [Mathematical Formula 2], it can be seen that the relationship between the output voltage (V OUT2 ) and the temperature (T) is related to the physical characteristics (A 1 ) of the first P-MOS transistor (103) and the physical characteristics (A 2 ) of the second P-MOS transistor (104). The amount of change in the output voltage (V OUT2 ) according to the temperature (T)
Figure PCTKR2023003369-appb-img-000016
is defined by the following [Mathematical Formula 4].
[수학식 4][Mathematical formula 4]
Figure PCTKR2023003369-appb-img-000017
(
Figure PCTKR2023003369-appb-img-000018
는 선형화된 바디효과 계수(linearized body effect coefficient)
Figure PCTKR2023003369-appb-img-000017
(
Figure PCTKR2023003369-appb-img-000018
is the linearized body effect coefficient
즉, 제1 P-MOS 트랜지스터(103)의 물적 특성(A1)이 제2 P-MOS 트랜지스터(104)의 물적 특성(A2)보다 클수록 온도(T)에 따른 출력 전압(VOUT2)의 변화량이 증가하고 이는 출력 전압(VOUT2)의 범위가 증가하며 보다 선형적으로 출력되는 효과가 있다. 여기서, 물적 특성(A)는
Figure PCTKR2023003369-appb-img-000019
로 정의됨에 따라 본 발명에 따른 온도 센서는 제1 P-MOS 트랜지스터(103)와 제2 P-MOS 트랜지스터(104)의 게이트 산화 용량(gate oxide capacitance per unit area, Cox) 내지 트랜지스터 채널 폭(transistor width, Weff) 중 적어도 하나를 상이하게 설정할 수 있다. 또한, 제1 P-MOS 트랜지스터(103)의 게이트 산화 용량(gate oxide capacitance per unit area, Cox) 내지 트랜지스터 채널 폭(transistor width, Weff) 중 적어도 하나는 제2 P-MOS 트랜지스터(102)보다 크게 설정될 수 있다.That is, as the material characteristic (A 1 ) of the first P-MOS transistor (103) is greater than the material characteristic (A 2 ) of the second P-MOS transistor (104), the amount of change in the output voltage (V OUT2 ) according to the temperature (T) increases, which has the effect of increasing the range of the output voltage (V OUT2 ) and making it output more linearly. Here, the material characteristic (A) is
Figure PCTKR2023003369-appb-img-000019
As defined, the temperature sensor according to the present invention can set at least one of the gate oxide capacitance per unit area (C ox ) and the transistor channel width (W eff ) of the first P-MOS transistor (103) and the second P-MOS transistor (104) differently. In addition, at least one of the gate oxide capacitance per unit area (C ox ) and the transistor channel width (W eff ) of the first P-MOS transistor (103) can be set to be larger than that of the second P-MOS transistor (102).
또한, 본 발명에 따른 온도 센서는 온도 검출부(110)를 포함할 수 있다. 온도 검출부(110)는 제1 P-MOS 트랜지스터(103)의 타단과 제2 P-MOS 트랜지스터(104)의 일단이 연결된 노드의 전압(VOUT2)에 기초하여 온도 정보를 제공할 수 있다. In addition, the temperature sensor according to the present invention may include a temperature detection unit (110). The temperature detection unit (110) may provide temperature information based on the voltage (V OUT2 ) of a node to which the other end of the first P-MOS transistor (103) and one end of the second P-MOS transistor (104) are connected.
또한, 온도 검출부(110)는 제1 P-MOS 트랜지스터(103)의 타단과 제2 P-MOS 트랜지스터(104)의 일단이 연결된 노드에서 출력된 전압(VOUT2)을 증폭하는 증폭기(111), 증폭기(111)에서 출력된 전압을 디지털 신호로 변환하여 출력하는 ADC(112) 및 디지털 신호를 선형화하여 출력하는 디지털 보정 회로(113)를 포함할 수 있다. 온도 검출부(110)는 디지털 보정 회로(113)에서 출력된 디지털 신호에 기초하여 온도 정보를 제공할 수 있다.In addition, the temperature detection unit (110) may include an amplifier (111) that amplifies a voltage (V OUT2 ) output from a node where the other end of the first P-MOS transistor (103) and one end of the second P-MOS transistor (104) are connected, an ADC (112) that converts the voltage output from the amplifier (111) into a digital signal and outputs it, and a digital compensation circuit (113) that linearizes the digital signal and outputs it. The temperature detection unit (110) may provide temperature information based on the digital signal output from the digital compensation circuit (113).
도 3은 본 발명의 실시예에 따라 N-MOS 트랜지스터(201, 202) 및 P-MOS 트랜지스터(203, 204)를 병합하여 구성되는 온도 센서의 회로도이다.FIG. 3 is a circuit diagram of a temperature sensor configured by merging N-MOS transistors (201, 202) and P-MOS transistors (203, 204) according to an embodiment of the present invention.
도 3을 참조하면, 본 발명의 온도 센서는 N-MOS 트랜지스터인 제1 MOS 트랜지스터(MN1) 및 제2 MOS 트랜지스터(MN2), P-MOS 트랜지스터인 제3 MOS 트랜지스터(MP3) 및 제4 MOS 트랜지스터(MP4) 및 온도 검출부(210)를 포함할 수 있다.Referring to FIG. 3, the temperature sensor of the present invention may include a first MOS transistor (MN1) and a second MOS transistor (MN2) which are N-MOS transistors, a third MOS transistor (MP3) and a fourth MOS transistor (MP4) which are P-MOS transistors, and a temperature detection unit (210).
N-MOS 트랜지스터(201, 202)의 구조는 도 1을 참조하여 설명한 내용과 동일하고, P-MOS 트랜지스터(203, 204)의 구조는 도 2를 참조하여 설명한 내용과 동일하다. The structure of the N-MOS transistor (201, 202) is the same as that described with reference to Fig. 1, and the structure of the P-MOS transistor (203, 204) is the same as that described with reference to Fig. 2.
온도 검출부(210)는 제1 MOS 트랜지스터(MN1)의 타단과 제2 MOS 트랜지스터(MN2)의 일단이 연결된 노드의 전압(이하, 제1 출력 전압(VOUT1))과 제3 MOS 트랜지스터(MP3)의 타단과 제4 MOS 트랜지스터(MP4)의 일단이 연결된 노드의 전압(이하, 제2 출력 전압(VOUT2)) 간의 전압차에 기초하여 온도 정보를 제공할 수 있다. 도 1 및 도 2를 참조하여 설명한 바와 같이, 제1 출력 전압(VOUT1)은 온도(T)에 선형적으로 비례하고 제2 출력 전압(VOUT2)은 온도(T)에 선형적으로 반비례하기 때문에 서로 상보적이다. 따라서, 온도 검출부(210)는 제1 출력 전압(VOUT1)과 제2 출력 전압(VOUT2) 간의 차이를 이용해 온도(T)에 따른 출력 전압의 범위를 보다 넓힐 수 있다.The temperature detection unit (210) can provide temperature information based on the voltage difference between the voltage of the node connected between the other terminal of the first MOS transistor (MN1) and one terminal of the second MOS transistor (MN2) (hereinafter, the first output voltage (V OUT1 )) and the voltage of the node connected between the other terminal of the third MOS transistor (MP3) and one terminal of the fourth MOS transistor (MP4) (hereinafter, the second output voltage (V OUT2 )). As described with reference to FIGS. 1 and 2, the first output voltage (V OUT1 ) is linearly proportional to the temperature (T) and the second output voltage (V OUT2 ) is linearly inversely proportional to the temperature (T), so they are complementary to each other. Therefore, the temperature detection unit (210) can further expand the range of the output voltage according to the temperature (T) by utilizing the difference between the first output voltage (V OUT1 ) and the second output voltage (V OUT2 ).
또한, 온도 검출부(210)는 차동증폭기(211), ADC(212) 및 디지털 보정 회로(213)를 포함할 수 있다. 차동증폭기(211)는 제1 출력 전압(VOUT1)과 제2 출력 전압(VOUT2) 간의 차이를 연산하고 그 차이를 증폭하여 출력할 수 있다. ADC(212)는 차동증폭기(211)에서 출력된 전압을 디지털 신호로 변환하여 출력할 수 있다. 디지털 보정 회로(213)는 ADC(212)에서 출력된 디지털 신호를 선형화하여 출력할 수 있다. 온도 검출부(210)는 디지털 보정 회로(213)에서 출력된 디지털 신호에 기초하여 온도 정보를 제공할 수 있다. In addition, the temperature detection unit (210) may include a differential amplifier (211), an ADC (212), and a digital compensation circuit (213). The differential amplifier (211) may calculate the difference between the first output voltage (V OUT1 ) and the second output voltage (V OUT2 ) and may amplify and output the difference. The ADC (212) may convert the voltage output from the differential amplifier (211) into a digital signal and output it. The digital compensation circuit (213) may linearize and output the digital signal output from the ADC (212). The temperature detection unit (210) may provide temperature information based on the digital signal output from the digital compensation circuit (213).
도 4는 본 발명의 실시예에 따라 N-MOS 트랜지스터로 구성되는 온도 센서에 있어서 측정 전압을 나타내는 그래프이다. FIG. 4 is a graph showing a measurement voltage in a temperature sensor composed of an N-MOS transistor according to an embodiment of the present invention.
도 4를 참조하면, N-MOS 트랜지스터의 문턱전압(VTH)에 따른 출력 전압 값이 개시된다. 문턱전압(VTH)의 크기에 따라 각각 n-lvt(낮은 문턱전압, Low Voltage Transistor), n-rvt(기준 문턱전압, Regular Voltage Transistor), n-hvt(높은 문턱전압, High Voltage Transistor)로 구분될 수 있다. 먼저 n-lvt의 온도(T)에 따른 출력 전압(VOUT1)은 도 4에 도시된 바와 같이 GN1에 해당한다. 온도(T)가 -40℃에서 120℃까지 변화할 때, n-lvt의 출력 전압(VOUT1)은 약145mV에서 245mV까지 변화한다. Referring to FIG. 4, the output voltage value according to the threshold voltage (V TH ) of the N-MOS transistor is disclosed. Depending on the size of the threshold voltage (V TH ), they can be classified into n-lvt (low threshold voltage, Low Voltage Transistor), n-rvt (reference threshold voltage, Regular Voltage Transistor), and n-hvt (high threshold voltage, High Voltage Transistor). First, the output voltage (V OUT1 ) according to the temperature (T) of the n-lvt corresponds to GN1 as shown in FIG. 4. When the temperature (T) changes from -40℃ to 120℃, the output voltage (V OUT1 ) of the n-lvt changes from about 145 mV to 245 mV.
또한, n-rvt의 온도(T)에 따른 출력 전압(VOUT1)은 도 4에 도시된 바와 같이 GN2에 해당한다. 온도(T)가 -40℃에서 120℃까지 변화할 때, n-rvt의 출력 전압(VOUT1)은 약130mV에서 255mV까지 변화한다.In addition, the output voltage (V OUT1 ) according to the temperature (T) of n-rvt corresponds to GN2 as shown in Fig. 4. When the temperature (T) changes from -40℃ to 120℃, the output voltage (V OUT1 ) of n-rvt changes from about 130 mV to 255 mV.
또한, n-hvt의 온도(T)에 따른 출력 전압(VOUT1)은 도 4에 도시된 바와 같이 GN3에 해당한다. 온도(T)가 -40℃에서 120℃까지 변화할 때, n-hvt의 출력 전압(VOUT1)은 약90mV에서 240mV까지 변화한다. In addition, the output voltage (V OUT1 ) according to the temperature (T) of the n-hvt corresponds to GN3 as shown in Fig. 4. When the temperature (T) changes from -40℃ to 120℃, the output voltage (V OUT1 ) of the n-hvt changes from about 90mV to 240mV.
결과적으로 N-MOS 트랜지스터의 문턱전압(VTH)이 높을수록 온도(T)에 따른 출력 전압(VOUT1)의 범위가 넓고 보다 선형적인 것을 알 수 있다.As a result, it can be seen that the higher the threshold voltage (V TH ) of the N-MOS transistor, the wider and more linear the range of the output voltage (V OUT1 ) depending on the temperature (T).
도 5를 참조하면, P-MOS 트랜지스터의 문턱전압(VTH)에 따른 출력 전압 값이 개시된다. 문턱전압(VTH)의 크기에 따라 각각 p-lvt(낮은 문턱전압, Low Voltage Transistor), p-rvt(기준 문턱전압, Regular Voltage Transistor), p-hvt(높은 문턱전압, High Voltage Transistor)로 구분될 수 있다. 먼저 p-lvt의 온도(T)에 따른 출력 전압(VOUT2)은 도 5에 도시된 바와 같이 GP1에 해당한다. 온도(T)가 -40℃에서 120℃까지 변화할 때, p-lvt의 출력 전압(VOUT2)은 약1000mV에서 860mV까지 변화한다. Referring to FIG. 5, the output voltage value according to the threshold voltage (V TH ) of the P-MOS transistor is disclosed. Depending on the size of the threshold voltage (V TH ), they can be classified into p-lvt (low threshold voltage, Low Voltage Transistor), p-rvt (reference threshold voltage, Regular Voltage Transistor), and p-hvt (high threshold voltage, High Voltage Transistor). First, the output voltage (V OUT2 ) according to the temperature (T) of the p-lvt corresponds to GP1 as shown in FIG. 5. When the temperature (T) changes from -40℃ to 120℃, the output voltage (V OUT2 ) of the p-lvt changes from about 1000mV to 860mV.
또한, p-rvt의 온도(T)에 따른 출력 전압(VOUT2)은 도 5에 도시된 바와 같이 GP2에 해당한다. 온도(T)가 -40℃에서 120℃까지 변화할 때, p-rvt의 출력 전압(VOUT2)은 약1060mV에서 900mV까지 변화한다.In addition, the output voltage (V OUT2 ) according to the temperature (T) of the p-rvt corresponds to GP2 as shown in Fig. 5. When the temperature (T) changes from -40℃ to 120℃, the output voltage (V OUT2 ) of the p-rvt changes from about 1060mV to 900mV.
또한, p-hvt의 온도(T)에 따른 출력 전압(VOUT2)은 도 4에 도시된 바와 같이 GP3에 해당한다. 온도(T)가 -40℃에서 120℃까지 변화할 때, p-hvt의 출력 전압(VOUT2)은 약1120mV에서 950mV까지 변화한다. In addition, the output voltage (V OUT2 ) according to the temperature (T) of the p-hvt corresponds to GP3 as shown in Fig. 4. When the temperature (T) changes from -40℃ to 120℃, the output voltage (V OUT2 ) of the p-hvt changes from about 1120mV to 950mV.
결과적으로 P-MOS 트랜지스터의 문턱전압(VTH)이 높을수록 온도(T)에 따른 출력 전압(VOUT2)의 범위가 넓고 보다 선형적인 것을 알 수 있다.As a result, it can be seen that the higher the threshold voltage (V TH ) of the P-MOS transistor, the wider and more linear the range of the output voltage (V OUT2 ) depending on the temperature (T).
도 6은 본 발명의 일 실시예에 따라 제1 MOS 트랜지스터(N-MOS)의 물적 특성이 증가함에 따른 측정 전압(VOUT1)을 나타내는 그래프이다.FIG. 6 is a graph showing a measured voltage (V OUT1 ) as the physical characteristics of a first MOS transistor (N-MOS) increase according to one embodiment of the present invention.
도 1 및 도 6을 참조하면, 제1 N-MOS 트랜지스터(101)의 물적 특성(A1)만 변화 시켰을 때 각각의 출력 전압(VOUT1)이 도시된다. 물적 특성(A1)은 도 1을 참조하여 설명한 바와 같이 로 정의된다. 도 6은 물적 특성(A1) 중 트랜지스터의 채널 폭(transistor width, Weff)을 변화시켰을 때의 출력 전압(VOUT1)의 특성을 나타낸다. NW4는 제1 N-MOS 트랜지스터(101)의 채널 폭(W1)이 가장 큰 경우, NW1는 제1 N-MOS 트랜지스터(101)의 채널 폭(W1)이 가장 작은 경우에 해당한다. 제1 N-MOS 트랜지스터(101)의 채널 폭(W1)이 클수록 온도(T) 변화에 따른 출력 전압(VOUT1)의 범위가 넓고 보다 선형적으로 도시되는 것을 확인할 수 있다. Referring to FIGS. 1 and 6, when only the physical characteristic (A1) of the first N-MOS transistor (101) is changed, each output voltage (V OUT1 ) is illustrated. The physical characteristic (A1) is defined as described with reference to FIG. 1. FIG. 6 shows the characteristics of the output voltage (V OUT1 ) when the channel width (transistor width, W eff ) of the transistor is changed among the physical characteristics (A1). NW4 corresponds to the case where the channel width (W1) of the first N-MOS transistor (101) is the largest, and NW1 corresponds to the case where the channel width (W1) of the first N-MOS transistor (101) is the smallest. It can be confirmed that as the channel width (W1) of the first N-MOS transistor (101) increases, the range of the output voltage (V OUT1 ) according to the change in temperature (T) is wider and more linearly illustrated.
도 7은 본 발명의 일 실시예에 따라 제1 MOS 트랜지스터(P-MOS)의 물적 특성이 증가함에 따른 측정 전압(VOUT2)을 나타내는 그래프이다. FIG. 7 is a graph showing a measured voltage (V OUT2 ) as the physical characteristics of a first MOS transistor (P-MOS) increase according to one embodiment of the present invention.
도 1 및 도 7을 참조하면, 제1 P-MOS 트랜지스터(103)의 물적 특성(A1)만 변화 시켰을 때 각각의 출력 전압(VOUT2)이 도시된다. 물적 특성(A1)은 도 1을 참조하여 설명한 바와 같이
Figure PCTKR2023003369-appb-img-000020
로 정의된다. 도 7은 물적 특성(A1) 중 트랜지스터의 채널 폭(transistor width, Weff)을 변화시켰을 때의 출력 전압(VOUT2)의 특성을 나타낸다. PW4는 제1 P-MOS 트랜지스터(103)의 채널 폭(W1)이 가장 큰 경우, PW1는 제1 P-MOS 트랜지스터(103)의 채널 폭(W1)이 가장 작은 경우에 해당한다. 제1 P-MOS 트랜지스터(103)의 채널 폭(W1)이 클수록 온도(T) 변화에 따른 출력 전압(VOUT2)의 범위가 넓고 보다 선형적으로 도시되는 것을 확인할 수 있다. Referring to FIG. 1 and FIG. 7, each output voltage (V OUT2 ) is shown when only the physical characteristic (A1) of the first P-MOS transistor (103) is changed. The physical characteristic (A1) is as described with reference to FIG. 1.
Figure PCTKR2023003369-appb-img-000020
is defined as. Fig. 7 shows the characteristics of the output voltage (V OUT2 ) when the channel width (transistor width, W eff ) of the transistor among the physical characteristics (A1) is changed. PW4 corresponds to the case where the channel width (W1) of the first P-MOS transistor (103) is the largest, and PW1 corresponds to the case where the channel width (W1) of the first P-MOS transistor (103) is the smallest. It can be confirmed that as the channel width (W1) of the first P-MOS transistor (103) increases, the range of the output voltage (V OUT2 ) according to the change in temperature (T) becomes wider and more linearly depicted.
이상에서 본 발명의 바람직한 실시예에 대하여 설명하였으나, 본 발명에 개시된 실시예들은 본 발명의 기술 사상을 한정하기 위한 것이 아니라 설명하기 위한 것일 뿐이다. 따라서, 본 발명의 기술 사상은 개시된 각각의 실시예 뿐 아니라, 개시된 실시예들의 조합을 포함하고, 나아가, 이러한 실시예에 의하여 본 발명의 기술 사상의 범위가 한정되는 것은 아니다. 또한, 본 발명이 속하는 기술분야에서 통상의 지식을 가지는 자라면 첨부된 특허청구범위의 사상 및 범주를 일탈함이 없이 본 발명에 대한 다수의 변경 및 수정이 가능하며, 그러한 모든 적절한 변경 및 수정은 균등물로서 본 발명의 범위에 속하는 것으로 간주되어야 할 것이다.Although the preferred embodiments of the present invention have been described above, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but are merely intended to explain it. Therefore, the technical idea of the present invention includes not only each disclosed embodiment but also a combination of the disclosed embodiments, and further, the scope of the technical idea of the present invention is not limited by these embodiments. In addition, those skilled in the art to which the present invention pertains can make numerous changes and modifications to the present invention without departing from the spirit and scope of the appended claims, and all such appropriate changes and modifications should be considered as equivalents and falling within the scope of the present invention.
[부호의 설명][Explanation of symbols]
101, 102, 201, 202 : N-MOS 트랜지스터101, 102, 201, 202: N-MOS transistors
103, 104, 203, 204 : P-MOS 트랜지스터103, 104, 203, 204: P-MOS transistors
110, 210 : 온도 검출부110, 210: Temperature detection unit
111 : 증폭기111 : Amplifier
112, 212 : ADC112, 212 : ADC
113, 213 : 디지털 보정 회로113, 213: Digital compensation circuit
211 : 차동증폭기211 : Differential Amplifier
본 발명에 따른 온도 센서는 종래에 사용되던 트랜지스터를 이용한 온도 센서와 달리 온도 변화에 따른 전압의 출력 범위가 넓고 보다 선형적이기 때문에, 보다 정밀한 온도 측정을 요하는 환경에서 사용될 수 있다. Since the temperature sensor according to the present invention has a wider output range of voltage according to temperature change and is more linear, unlike a temperature sensor using a transistor used in the past, it can be used in an environment requiring more precise temperature measurement.

Claims (14)

  1. 일단이 전원에 연결된 제1 MOS 트랜지스터;First, the first MOS transistor is connected to the power supply;
    일단이 상기 제1 MOS 트랜지스터의 타단과 연결되고, 타단이 그라운드와 연결된 제2 MOS 트랜지스터; 및A second MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to ground; and
    상기 제1 MOS 트랜지스터의 타단과 제2 MOS 트랜지스터의 일단이 연결된 노드의 전압에 기초하여 온도 정보를 제공하는 온도 검출부;를 포함하되,A temperature detection unit that provides temperature information based on the voltage of a node connected to the other end of the first MOS transistor and one end of the second MOS transistor;
    상기 제1 및 제2 MOS 트랜지스터는 N-MOS 트랜지스터 또는 P-MOS 트랜지스터이되, 동일한 타입이고, 상기 제1 및 제2 MOS 트랜지스터의 게이트는 공통으로 연결된 것을 특징으로 하는 온도 센서.A temperature sensor characterized in that the first and second MOS transistors are N-MOS transistors or P-MOS transistors of the same type, and the gates of the first and second MOS transistors are commonly connected.
  2. 제1항에 있어서, In the first paragraph,
    상기 제1 MOS 트랜지스터는, 상기 제2 MOS 트랜지스터와 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area) 내지 채널 폭(Transistor width) 중 적어도 하나가 서로 상이한 것The first MOS transistor has at least one different gate oxide capacitance (Gate oxide capacitance per unit area) or channel width (Transistor width) from the second MOS transistor.
    을 특징으로 하는 온도 센서.A temperature sensor characterized by:
  3. 제2항에 있어서, In the second paragraph,
    상기 제1 MOS 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area)은 상기 제2 MOS 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area) 보다 큰 것The gate oxide capacitance per unit area of the first MOS transistor is greater than the gate oxide capacitance per unit area of the second MOS transistor.
    을 특징으로 하는 온도 센서.A temperature sensor characterized by:
  4. 제2항에 있어서, In the second paragraph,
    상기 제1 MOS 트랜지스터의 채널 폭(Transistor width)은 상기 제2 MOS 트랜지스터의 채널 폭(Transistor width) 보다 큰 것을 특징으로 하는 온도 센서.A temperature sensor, characterized in that the channel width of the first MOS transistor is greater than the channel width of the second MOS transistor.
  5. 제1항에 있어서, In the first paragraph,
    상기 제1 및 제2 MOS 트랜지스터는,The above first and second MOS transistors,
    N-MOS 트랜지스터이고, 상기 게이트가 공통으로 상기 그라운드에 연결된 것을 특징으로 하는 온도 센서.A temperature sensor characterized by being an N-MOS transistor and having the gates commonly connected to the ground.
  6. 제1항에 있어서, In the first paragraph,
    상기 제1 및 제2 MOS 트랜지스터는,The above first and second MOS transistors,
    P-MOS 트랜지스터이고, 상기 게이트가 공통으로 상기 전원에 연결된 것을 특징으로 하는 온도 센서.A temperature sensor characterized in that it is a P-MOS transistor and the gate is commonly connected to the power supply.
  7. 제1항에 있어서,In the first paragraph,
    상기 온도 검출부는,The above temperature detection unit,
    상기 제1 MOS 트랜지스터의 타단과 제2 MOS 트랜지스터의 일단이 연결된 노드에서 출력된 전압을 증폭하는 증폭기;An amplifier that amplifies a voltage output from a node connected between the other terminal of the first MOS transistor and one terminal of the second MOS transistor;
    상기 증폭기에서 출력된 전압을 디지털 신호로 변환하여 출력하는 ADC; 및An ADC that converts the voltage output from the above amplifier into a digital signal and outputs it; and
    상기 디지털 신호를 선형화하여 출력하는 디지털 보정 회로;를 포함하는 것을 특징으로 하는 온도 센서. A temperature sensor characterized by including a digital compensation circuit that linearizes and outputs the digital signal.
  8. 제7항에 있어서,In Article 7,
    상기 온도 검출부는,The above temperature detection unit,
    상기 디지털 신호에 기초하여 온도 정보를 제공하는 것을 특징으로 하는 온도 센서.A temperature sensor characterized by providing temperature information based on the above digital signal.
  9. 일단이 전원에 연결된 제1 MOS 트랜지스터;First, the first MOS transistor is connected to the power supply;
    일단이 상기 제1 MOS 트랜지스터의 타단과 연결되고, 타단이 그라운드와 연결된 제2 MOS 트랜지스터;A second MOS transistor having one terminal connected to the other terminal of the first MOS transistor and the other terminal connected to ground;
    일단이 상기 전원에 연결된 제3 MOS 트랜지스터;First, a third MOS transistor connected to the above power supply;
    일단이 상기 제3 MOS 트랜지스터의 타단과 연결되고, 타단이 상기 그라운드와 연결된 제4 MOS 트랜지스터; 및A fourth MOS transistor having one end connected to the other end of the third MOS transistor and the other end connected to the ground; and
    상기 제1 MOS 트랜지스터의 타단과 제2 MOS 트랜지스터의 일단이 연결된 노드의 전압과 상기 제3 MOS 트랜지스터의 타단과 제4 MOS 트랜지스터의 일단이 연결된 노드의 전압 간의 전압차에 기초하여 온도 정보를 제공하는 온도 검출부;를 포함하되,A temperature detection unit that provides temperature information based on a voltage difference between a voltage of a node connected to the other end of the first MOS transistor and one end of the second MOS transistor and a voltage of a node connected to the other end of the third MOS transistor and one end of the fourth MOS transistor; including:
    상기 제1 및 제2 MOS 트랜지스터는 N-MOS 트랜지스터이고,The above first and second MOS transistors are N-MOS transistors,
    상기 제3 및 제4 MOS 트랜지스터는 P-MOS 트랜지스터이며,The above third and fourth MOS transistors are P-MOS transistors,
    상기 제1 및 제2 MOS 트랜지스터의 게이트는 공통으로 상기 그라운드에 연결되고,The gates of the first and second MOS transistors are commonly connected to the ground,
    상기 제3 및 제4 MOS 트랜지스터의 게이트는 공통으로 상기 전원에 연결된 것을 특징으로 하는 온도 센서.A temperature sensor, characterized in that the gates of the third and fourth MOS transistors are commonly connected to the power supply.
  10. 제9항에 있어서, In Article 9,
    상기 제1 MOS 트랜지스터는, 상기 제2 MOS 트랜지스터와 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area) 내지 채널 폭(Transistor width) 중 적어도 하나가 서로 상이하고,The first MOS transistor has at least one different gate oxide capacitance (Gate oxide capacitance per unit area) and channel width (Transistor width) from the second MOS transistor,
    상기 제3 MOS 트랜지스터는, 상기 제4 MOS 트랜지스터와 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area) 내지 채널 폭(Transistor width) 중 적어도 하나가 서로 상이한 것을 특징으로 하는 온도 센서. A temperature sensor, wherein the third MOS transistor has at least one different gate oxide capacitance per unit area and/or channel width from the fourth MOS transistor.
  11. 제10항에 있어서,In Article 10,
    상기 제1 MOS 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area)은 상기 제2 MOS 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area) 보다 크고,The gate oxide capacitance per unit area of the first MOS transistor is greater than the gate oxide capacitance per unit area of the second MOS transistor,
    상기 제3 MOS 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area)은 상기 제4 MOS 트랜지스터의 게이트 산화 용량(Gate oxide capacitance per unit area) 보다 큰 것을 특징으로 하는 온도 센서.A temperature sensor, characterized in that the gate oxide capacitance per unit area of the third MOS transistor is greater than the gate oxide capacitance per unit area of the fourth MOS transistor.
  12. 제10항에 있어서,In Article 10,
    상기 제1 MOS 트랜지스터의 채널 폭(Transistor width)은 상기 제2 MOS 트랜지스터의 채널 폭(Transistor width) 보다 크고,The channel width of the first MOS transistor is larger than the channel width of the second MOS transistor,
    상기 제3 MOS 트랜지스터의 채널 폭(Transistor width)은 상기 제4 MOS 트랜지스터의 채널 폭(Transistor width) 보다 큰 것을 특징으로 하는 온도 센서.A temperature sensor, characterized in that the channel width of the third MOS transistor is greater than the channel width of the fourth MOS transistor.
  13. 제9항에 있어서,In Article 9,
    상기 온도 검출부는,The above temperature detection unit,
    상기 제1 MOS 트랜지스터의 타단과 제2 MOS 트랜지스터의 일단이 연결된 노드의 전압과 상기 제3 MOS 트랜지스터의 타단과 제4 MOS 트랜지스터의 일단이 연결된 노드의 전압 간의 차이를 증폭하여 출력하는 차동증폭기;A differential amplifier that amplifies and outputs the difference between the voltage of a node connected between the other terminal of the first MOS transistor and one terminal of the second MOS transistor and the voltage of a node connected between the other terminal of the third MOS transistor and one terminal of the fourth MOS transistor;
    상기 증폭기에서 출력된 전압을 디지털 신호로 변환하여 출력하는 ADC; 및An ADC that converts the voltage output from the above amplifier into a digital signal and outputs it; and
    상기 디지털 신호를 선형화하여 출력하는 디지털 보정 회로;를 포함하는 것을 특징으로 하는 온도 센서.A temperature sensor characterized by including a digital compensation circuit that linearizes and outputs the digital signal.
  14. 제13항에 있어서,In Article 13,
    상기 온도 검출부는,The above temperature detection unit,
    상기 디지털 신호에 기초하여 온도 정보를 제공하는 것을 특징으로 하는 온도 센서.A temperature sensor characterized by providing temperature information based on the above digital signal.
PCT/KR2023/003369 2023-02-20 2023-03-13 Temperature sensor WO2024177189A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08184505A (en) * 1994-11-02 1996-07-16 Seiko Instr Inc Temperature detector
KR19990025330A (en) * 1997-09-12 1999-04-06 이형도 CMOS temperature sensor circuit
JP2006242894A (en) * 2005-03-07 2006-09-14 Ricoh Co Ltd Temperature-sensing circuit
JP4843034B2 (en) * 2006-06-09 2011-12-21 富士通株式会社 Ring oscillator for temperature sensor, temperature sensor circuit, and semiconductor device including the same
CN114279595A (en) * 2021-12-28 2022-04-05 中国科学院半导体研究所 Temperature sensing circuit, CMOS temperature sensor based on temperature sensing circuit and calibration method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08184505A (en) * 1994-11-02 1996-07-16 Seiko Instr Inc Temperature detector
KR19990025330A (en) * 1997-09-12 1999-04-06 이형도 CMOS temperature sensor circuit
JP2006242894A (en) * 2005-03-07 2006-09-14 Ricoh Co Ltd Temperature-sensing circuit
JP4843034B2 (en) * 2006-06-09 2011-12-21 富士通株式会社 Ring oscillator for temperature sensor, temperature sensor circuit, and semiconductor device including the same
CN114279595A (en) * 2021-12-28 2022-04-05 中国科学院半导体研究所 Temperature sensing circuit, CMOS temperature sensor based on temperature sensing circuit and calibration method thereof

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