WO2024174969A1

WO2024174969A1 - Semiconductor device and manufacturing method therefor

Info

Publication number: WO2024174969A1
Application number: PCT/CN2024/077667
Authority: WO
Inventors: 黄艳; 梁昕; 陈政; 王聪
Original assignee: 芯联集成电路制造股份有限公司
Priority date: 2023-02-20
Filing date: 2024-02-20
Publication date: 2024-08-29
Also published as: CN115842029B; CN115842029A

Abstract

A semiconductor device and a manufacturing method therefor. The device comprises: a base, which comprises a first substrate, a second substrate, and an insulating layer arranged between the first substrate and the second substrate, and which further comprises at least two device regions, comprising at least one first device region in which the first substrate is isolated from the second substrate by means of the insulating layer and at least one second device region in which the insulating layer is discontinuous, wherein at least part of a surface of the first substrate and at least part of a surface of the second substrate are connected to each other; at least one isolation structure, which is arranged in the first substrate and is positioned between adjacent device regions so as to isolate the device regions; a first device, which is arranged in the first substrate and is positioned in the first device region; and a second device, which is arranged in the second device region and is a vertical-type device. The semiconductor device has a good heat dissipation property, such that the semiconductor device is more suitable for application in high-power fields.

Description

Semiconductor device and manufacturing method

Technical Field

The present application relates to the field of semiconductor technology, and more particularly to a semiconductor device and a manufacturing method thereof.

Background Art

In recent years, with the rapid development of microelectronics technology and the urgent needs of related fields such as automotive electronics, aerospace, industrial control and power transportation, the development of new high-power semiconductor devices has attracted more and more attention. Devices manufactured by the Bipolar-CMOS-DMOS (BCD) process based on the fully isolated structure of Silicon on Insulator (SOI) dielectric have the advantages of strong anti-interference ability, good reliability and elimination of parasitic latch effect. However, due to the fully isolated structure of SOI dielectric, BCD devices can only be turned on in the cells formed by the bottom of the isolation structure and the insulating layer of SOI, so the BCD devices based on the fully isolated structure of SOI dielectric have poor heat dissipation ability, which limits the application scope of devices manufactured by BCD process in high-power fields.

Summary of the invention

A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

The present application provides a semiconductor device, comprising: a substrate, comprising a first substrate, a second substrate and an insulating layer arranged between the first substrate and the second substrate, the substrate comprising at least two device regions, the at least two device regions comprising at least one first device region and at least one second device region, wherein in the first device region, the first substrate and the second substrate are isolated by the insulating layer; in the second device region, the insulating layer is discontinuous, and at least part of the surface of the first substrate and at least part of the surface of the second substrate are connected; at least one isolation structure is arranged in the first substrate and located between adjacent device regions to isolate each device region; a first device is arranged on the first substrate and located in the first device region; a second device is arranged in the second device region, and the second device is a vertical device.

Exemplarily, when the second device is a vertical double diffused MOS device, the vertical double diffused MOS device includes a drain, and the drain covers a bottom surface of the second substrate in the second device region.

Exemplarily, when the second device is a trench IGBT device, the trench IGBT device includes a collector, and the collector covers a bottom surface of the second substrate in the second device region.

Exemplarily, when the second device is a super junction MOS device, the super junction MOS device has a pillar region formed in the second device region, and the super junction MOS device includes a drain, and the drain covers the bottom surface of the second substrate in the second device region.

Exemplarily, an operating voltage of the first device is lower than an operating voltage of the second device.

Exemplarily, a liner is formed on the sidewall of the isolation structure, and a dielectric is filled in the isolation structure.

Illustratively, a first trench is formed in the second device region of the first substrate, the first trench penetrates the first substrate and the insulating layer, and the first trench is filled with an epitaxial layer, and the epitaxial layer is used to form the second device.

The present application also provides a method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate comprising a first substrate, a second substrate and an insulating layer arranged between the first substrate and the second substrate, the substrate comprising at least two device regions, the at least two device regions comprising at least one first device region and at least one second device region; forming at least one isolation structure in the first substrate, each of the isolation structures being located between adjacent device regions and isolating each device region; forming a first trench in the second device region, the first trench penetrating the first substrate and the insulating layer and the bottom of the first trench being located in the second substrate; growing an epitaxial layer in the first trench; forming a second device in the second device region, the second device being a vertical device; and forming a first device in the first device region.

Exemplarily, the second device includes a trench-type IGBT device, wherein the step of forming the second device in the second device region includes: forming a third trench in the epitaxial layer; forming an oxide layer on the inner wall of the third trench and the surface of the first substrate and filling a gate layer in the third trench to form a gate of the second device; and forming a collector covering the bottom surface of the second substrate in the second device region.

Exemplarily, the second device comprises a vertical double diffused MOS device, wherein the step of forming the second device in the second device region comprises: forming a drain covering a bottom surface of the second substrate in the second device region.

According to the semiconductor device and manufacturing method provided by the present application, the semiconductor device uses a semi-insulating SOI dielectric isolation structure, combining the insulation ability of the SOI structure for the first device in the first device area and the heat dissipation and conductivity of the second device in the second device area. In the first device area, the first device can be used as the low-voltage part of the semiconductor device, while in the second device area, the insulating layer is discontinuous in the second device area, and the first substrate and the second substrate in the second device area can be conductive, so the second device area can be used to make a vertical second device, which improves the space utilization of the substrate, and the second device can be used as the high-power part of the semiconductor device; in addition, since the current of the vertical device can be derived from the second substrate at the bottom, its heat dissipation ability is better, and the vertical device has more conduction channels, which saves the area occupied by the drift region; in summary, compared with the conventional BCD process using the SOI dielectric isolation structure, the semiconductor device of the present application has good heat dissipation, saves area, and can be suitable for application in high-power fields.

BRIEF DESCRIPTION OF THE DRAWINGS

The following drawings of the present application are used as a part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, which are used to explain the principle of the present application.

In the attached picture:

FIG1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present application;

FIG2 is a schematic diagram showing a top view of a semiconductor device according to an embodiment of the present application;

FIG3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present application;

FIG4 is a schematic flow chart showing a method for manufacturing a semiconductor device according to an embodiment of the present application;

5A to 5K are schematic cross-sectional views of a semiconductor device obtained by sequentially implementing steps of a method for manufacturing a semiconductor device according to an embodiment of the present application;

Reference numerals: semiconductor device 100, base 101, first substrate 1011, second substrate 1012, insulating layer
1013, isolation structure 130, liner 131, dielectric 132, first device region 110, first device 111, second device region 120, second device 122, pillar region 1221, first hard mask layer 1031, patterned photoresist layer 1032, first trench 121, third trench 123, epitaxial layer 1202, second hard mask layer 1203, patterned photoresist layer 104, oxide layer 105.

DETAILED DESCRIPTION

In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is easily understood by those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described.

It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and/or parts, these elements, components, regions, layers and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

The terminology used herein is intended only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "a", "an", and "/the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and/or "including" when used in this description are intended to include the plural forms. When used in the specification, the existence of a feature, integer, step, operation, element and/or component is determined, but the existence or addition of one or more other features, integers, steps, operations, elements, components and/or groups is not excluded. When used herein, the term "and/or" includes any and all combinations of the relevant listed items.

In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

In view of the problem that the device heat dissipation capability of the BCD process based on the full isolation structure of SOI medium is poor, the present application provides a semiconductor device, comprising: a substrate, comprising a first substrate, a second substrate located below the first substrate, and an insulating layer arranged between the first substrate and the second substrate, the substrate comprising at least two device regions, the at least two device regions comprising at least one first device region and at least one second device region, wherein in the first device region, the insulating layer between the first substrate and the second substrate is continuous, and the first substrate and the second substrate are isolated by the insulating layer, and in the second device region, the insulating layer between the first substrate and the second substrate is discontinuous, and at least part of the surface of the first substrate is connected to at least part of the surface of the second substrate; at least one isolation structure is arranged in the first substrate and located between adjacent device regions to isolate each device region; a first device is arranged on the first substrate and located in the first device region; a second device is arranged in the second device region, and the second device is a vertical device.

The semiconductor device of the present application combines the electrical and thermal conductivity of high-voltage power devices (including, for example, vertical devices) with the insulation capability of the SOI dielectric isolation structure to obtain a semiconductor device with a semi-insulating SOI dielectric isolation structure. The semiconductor device has good heat dissipation and is suitable for use in high-power fields.

Below, the semiconductor device of an embodiment of the present application is described in more detail with reference to Figures 1 to 3, wherein Figure 1 shows a schematic diagram of the cross-sectional structure of a semiconductor device according to an embodiment of the present application; Figure 2 shows a schematic diagram of the top view structure of a semiconductor device according to an embodiment of the present application; and Figure 3 shows a schematic diagram of the cross-sectional structure of a semiconductor device according to another embodiment of the present application.

In at least one embodiment, as shown in FIG. 1 , a semiconductor device 100 includes: a substrate 101, the substrate 101 is composed of a first substrate 1011, a second substrate 1012 and an insulating layer 1013, wherein the second substrate 1012 is located below the first substrate 1011, and the insulating layer 1013 is disposed between the first substrate 1011 and the second substrate 1012; a first device region 110 and a second device region 120, wherein in the first device region 110, the insulating layer 1013 between the first substrate 1011 and the second substrate 1012 is continuous, and in the second device region 120, the insulating layer 1013 between the first substrate 1011 and the second substrate 1012 is discontinuous, and in At the discontinuity of the insulating layer 1013, at least a portion of the surface of the first substrate 1011 is connected to at least a portion of the surface of the second substrate 1012; an isolation structure 130 is arranged in the first substrate 1011 and is located between adjacent device regions (for example, as shown in FIG. 1, between adjacent first device regions 110 and second device regions 120) to isolate each device region, and the isolation structure 130 is also provided with a liner 131 and filled with a dielectric 132; a first device 111 and a second device 122, wherein the first device 111 is arranged on the first substrate 1011 and is located in the first device region 110, and the second device 122 is located in the second device region 120, and optionally, a first trench is formed in the second device region 120, and the first trench is filled with an epitaxial layer, and the epitaxial layer is used to form The second device 122 is formed in the epitaxial layer. The operating voltage of the first device 111 is lower than that of the second device 122. Since the first device 111 is completely surrounded by the isolation structure 130 and the insulating layer 1013, the first device 111 has good insulation and is suitable for use as a low-voltage device, which is easy to integrate. The insulating layer 1013 is discontinuous in the second device area 120. At least part of the surface of the first substrate 1011 is connected to at least part of the surface of the second substrate 1012. Therefore, the first substrate 1011 and the second substrate 1012 in the second device area 120 can be conductive. The second device 122 can utilize the second substrate 1012 in the second device area 120, thereby improving the space utilization rate of the substrate. The second device 122 is suitable for use as a high-voltage power device.

Exemplarily, the first device includes a CMOS device, and the second device is a vertical device, which may include a vertical double-diffused MOS device (Vertically Double-diffused Metal Oxide Semiconductor, VDMOS) and an IGBT (Insulated Gate Bipolar Transistor, IGBT) device, wherein the VDMOS device includes a trench MOS device and a super junction MOS (Super Junction Metal Oxide Semiconductor, SJ-MOS) device, the IGBT device includes a trench IGBT device, or the second device may also be other types of vertical devices.

The terms "first substrate" and "second substrate" in this application refer to any semiconductor material constituting silicon on insulator (SOI), wherein illustrative examples of silicon-containing semiconductor materials that can be used as substrates include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), ceramic substrates of alumina, quartz or glass substrates, etc.

Although several examples of materials that can form the substrate are described herein, any material that can be used as the substrate falls within the spirit and scope of the present application. In addition, the substrate can be divided into active areas according to The substrate of the manufactured device can be undoped or doped. In at least one embodiment of the present application, as shown in FIG1 , various well structures and a channel layer on the surface of the substrate are also formed in the first substrate. Generally speaking, the ion doping conductivity type forming the well structure is the same as the ion doping conductivity type of the channel layer, but the concentration is lower than that of the gate channel layer, and the depth of the ion implantation is wider, and at the same time, it is necessary to reach a depth greater than that of the isolation structure. For simplicity and ease of explanation, only a blank first substrate 1011 and a second substrate 1012 are shown in FIG1 .

The buried insulating layer of silicon on insulator (SOI) can include any of several dielectric materials, non-limiting examples include oxides, nitrides and oxynitrides, in particular, oxides, nitrides and oxynitrides of silicon, but do not include oxides, nitrides and oxynitrides of other elements. The insulating layer can include crystalline or amorphous dielectric materials, and crystalline dielectric materials are generally selected. The insulating layer can be formed by any of several methods, non-limiting examples include ion implantation methods, thermal or plasma oxidation or nitridation methods, chemical vapor deposition (CVD) methods, and physical vapor deposition (PVD) methods. Typically, the insulating layer includes an oxide from a semiconductor material that constitutes the base semiconductor substrate (i.e., an oxide of the base semiconductor substrate). Typically, the insulating layer has a thickness from about to approximately In at least one embodiment of the present application, as shown in FIG1 , the insulating layer 1013 is made of silicon oxide.

In at least one embodiment of the present application, as shown in FIG1 , the insulating layer 1013 may also be formed using an insulating layer such as one containing polyvinyl phenol, polyimide or siloxane, etc. The insulating layer may be formed by any prior art known to those skilled in the art, and a chemical vapor deposition method (CVD) such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD) or plasma enhanced chemical vapor deposition (PECVD) may be selected.

Trench isolation technology is usually used to achieve isolation of active devices. In at least one embodiment of the present application, as shown in Figure 1, an isolation structure 130 is formed in the first substrate 1011. For those skilled in the art, the steps of forming the isolation structure 130 and defining the active area are well-known technical means and will not be described in detail here. Any suitable method can be used to form the isolation structure 130 and define the active area.

In at least one embodiment of the present application, as shown in FIG1 , in order to form the isolation structure 130, any prior art familiar to those skilled in the art may be used to etch the first substrate, including wet etching and dry etching. Exemplarily, the dry etching process includes, but is not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used, and the present application does not limit this.

In at least one embodiment of the present application, as shown in FIG1 , when forming the isolation structure 130, the trench can be filled with a dielectric 132 to form the isolation structure 130. As an example, the dielectric 132 can be polysilicon, and the method for forming polysilicon can be chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD) or plasma enhanced chemical vapor deposition (PECVD). Optionally, as shown in FIG1 , a liner 131 can be formed on the sidewall and bottom of the trench before the trench is filled. As an example, the liner 131 can be silicon dioxide. A densification step can be performed after the trench is filled, or a planarization process can be performed after the trench is filled. Compared with the field oxygen isolation region (LOCOS) formed by the PN junction isolation and the silicon local oxidation process, the isolation structure occupies less substrate surface area and can save more area.

In at least one embodiment of the present application, as shown in FIG1 , in the first device region 110 of the semiconductor device 100, the first device 111 and the devices around it are completely isolated and insulated by the isolation structure 130 and the insulating layer 1013, wherein the first device 111 can be a CMOS device, and the fields in which the CMOS device can be applied include but are not limited to, for example, logic circuits, analog circuits, mixed signal circuits and/or any suitable low-power integrated circuits. In other embodiments, the semiconductor device includes an interconnection metal structure (not shown) formed on the first substrate. The interconnection metal structure is configured to provide electrical interconnection between active devices and/or passive devices formed in the first substrate, the first device region and/or the second device region.

In at least one embodiment, as shown in FIG. 1 and FIG. 2 , in the second device region 120 of the semiconductor device 100 , the insulating layer 1013 disposed between the first substrate 1011 and the second substrate 1012 is discontinuous, so the second substrate 1012 in the second device region 120 can be turned on, the second device 122 can be turned on with the second substrate 1012, and the second device 122 can utilize the second substrate 1012 in the second device region 120, thereby improving the space utilization of the second device 122. The second device 122 is suitable for use as a high-voltage power device. Exemplarily, when the second device has a trench structure (such as a trench MOS device or a trench IGBT device), the structures of the second device distributed on the plane are all channels, which increases the channel area compared to the planar structure, so the second device of the semiconductor device of the present application can also save area, and compared with the conventional BCD process, the number of devices integrated per unit area of the wafer can be increased.

In some embodiments, the second device may also include a vertical double-diffused MOS (Vertically Double-diffused Metal Oxide Semiconductor, VDMOS) device, which has the advantages of low switching loss, high input impedance, low driving power, good frequency characteristics and highly linear transconductance, and is increasingly widely used in analog circuits and drive circuits, especially high-voltage power parts, such as DC-DC converters, DC-AC converters, fast switching conversion, relays or motor drives, etc. In the VDMOS device, a source is formed in the first substrate, and a gate structure is formed on the surface of the first substrate. The source is located in the first substrate on both sides of the gate structure, and the drain (e.g., the drain metal layer) covers the bottom surface of the second substrate in the second device region. When a positive voltage is applied to the gate structure to reach its turn-on voltage, a voltage is applied between the source and drain of the VDMOS device (generally, the source is positive and the drain is negative), the VDMOS device is turned on, and the current flows vertically downward through the first substrate and the second substrate to reach the drain at the bottom of the second substrate. A drain metal layer will be deposited at the bottom of the VDMOS device to form the drain of the VDMOS device. Since the deposited metal has good thermal conductivity, the heat dissipation of the second device 122 can be improved, thereby making the entire device have good thermal conductivity and can be applied to high-power fields.

In at least one embodiment, as shown in Figures 1 and 2, the second device 122 may be a trench IGBT device. Compared with a device with a planar gate structure, the trench IGBT device can significantly reduce the on-state voltage drop without increasing the turn-off loss. The main difference between the trench gate structure and the planar gate structure is that, compared with a device with a planar gate, the vertical structure of the trench IGBT device eliminates the area for making a conductive channel on the silicon surface, which is more conducive to designing compact cells, that is, more IGBT cells can be made on a unit area of the first substrate 1011, thereby increasing the width of the conductive channel and reducing the channel resistance; the trench IGBT device includes a collector, and the collector of the trench IGBT device covers the bottom surface of the second substrate in the second device area, and the current can be transferred from the bottom surface of the second substrate in the second device area. The collector of the trench IGBT device is derived, and since the collector of the deposited metal has good conductivity and heat dissipation, the conductivity and heat dissipation of the trench IGBT device are good; and since the insulating layer 1013 is discontinuous in the second device area 120, the first substrate 1011 and the second substrate 1012 in the second device area 120 can be conductive, the trench IGBT device can be conductive with the second substrate 1012, and the trench IGBT device can be conductive with the second substrate 1012 in the second device area 120, thereby improving the space utilization of the substrate. Therefore, when the second device 122 of the semiconductor device 100 of the present application is a trench IGBT device, the trench IGBT device has good heat dissipation and conductivity, and is used as the high-power part of the semiconductor device 100, and the semiconductor device 100 is suitable for high-power fields.

It is worth mentioning that, in the present application, the second device may be a vertical device, and the vertical device may include a trench device.

The semiconductor device of the above embodiment combines the insulation capability of the SOI dielectric isolation structure, the conductivity of the substrate, and the heat dissipation and conductivity of vertical devices (such as VDMOS devices and trench IGBT devices), and sets a low-voltage device (i.e., the first device) in the insulating part (i.e., the first device area) of the dielectric isolation, and sets a high-power device (i.e., the second device) in the conductive part (i.e., the second device area), thereby obtaining the semiconductor device of the above embodiment; in addition, since the semiconductor device of the present application includes a high-power device (such as a trench device), it also has the advantages of more conductive channels of the trench device and saves area. The first device has the advantages of being isolated from surrounding devices, and because the isolation between the first device and the surrounding devices utilizes the isolation structure of the SOI substrate, it can also play a role in saving area and increasing the utilization rate of the substrate.

In at least one embodiment, as shown in FIG. 3 , the second device 122 of the second device region 120 may also be a super junction MOS (Super Junction Metal Oxide Semiconductor, SJ-MOS) device, which includes a column region 1221 composed of a plurality of alternately arranged N-type conductive columns (not shown) and P-type conductive columns (not shown). By arranging the alternately arranged N-type conductive columns and P-type conductive columns, the doping concentration of the drift region of the second device 122 is increased to achieve low on-resistance. In some examples, the bottom end of the column region 1221 passes through the insulating layer 1013 and contacts and conducts with the second substrate 1012. Furthermore, the SJ-MOS device includes a drain (for example, a drain metal layer), and the drain of the SJ-MOS device covers the bottom surface of the second substrate in the second device region. Current can be derived from the drain on the bottom surface of the second substrate in the second device region. Since the drain metal layer has good conductivity and heat dissipation, the conductivity and heat dissipation of the SJ-MOS device are also better; and since the insulating layer 1013 is discontinuous in the second device region 120, the first substrate 1011 and the second substrate 1012 in the second device region 120 can be conductive, so the second device region 120 can be used to manufacture vertical devices, thereby improving the space utilization of the substrate; therefore, when the second device 122 of the semiconductor device 100 of the present application is a SJ-MOS device, the SJ-MOS device has good heat dissipation and conductivity, and the SJ-MOS device can be used as the high-power part of the semiconductor device 100, and the semiconductor device 100 is suitable for high-power fields.

According to the semiconductor device provided by the present application, it has the following advantages: the semiconductor device uses a semi-insulating SOI dielectric isolation structure, combining the insulation capability of the SOI structure for the first device in the first device region and the heat dissipation and conductivity capability of the second device in the second device region. In the first device region, the first device is a low-voltage device, that is, the first device can be used as the low-voltage part of the semiconductor device; and in the second device region, the second device is a high-voltage power device, that is, the second device can be used as the high-voltage power part of the semiconductor device. The insulating layer is discontinuous in the second device region, and the first substrate and the second substrate in the second device region can be conductive. Therefore, the second device region can be used to manufacture a vertical device (that is, the second device), thereby improving the space utilization rate of the substrate. And the second device of the semiconductor device is not completely isolated and insulated by the SOI dielectric isolation structure, the second device is a vertical device, which includes a VDMOS device or an IGBT device (such as a trench IGBT), wherein the VDMOS device includes at least one of a trench MOS device and an SJ-MOS device, and the second device has good conductivity and heat dissipation; wherein the SOI structure has the advantage of saving area, and at the same time the second device is a vertical device such as a trench device, and the trench device has more conduction channels, which saves the area occupied by the drift region; in summary, compared with the conventional BCD process using the SOI dielectric isolation structure, the semiconductor device of the present application combines The SOI structure has the insulation capability and the conduction and thermal conductivity of the vertical device, so it has good conductivity and heat dissipation. It also has the advantages of saving area of the SOI structure and vertical device, and is more suitable for application in high-power fields.

The present application also provides a method for manufacturing a semiconductor device. The manufacturing method of the semiconductor device 100 of the above embodiment of the present application is explained and illustrated in detail below with reference to Figure 4 and Figures 5A to 5K; wherein Figure 4 shows a schematic flow chart of the manufacturing method of a semiconductor device according to an embodiment of the present application; Figures 5A to 5K show schematic cross-sectional structures of a semiconductor device obtained by sequentially implementing each step of the manufacturing method of a semiconductor device according to an embodiment of the present application.

First, perform step S1, as shown in Figure 4, provide a substrate, the substrate includes a first substrate, a second substrate and an insulating layer arranged between the first substrate and the second substrate, the substrate includes at least two device areas, and the at least two device areas include at least one first device area and at least one second device area.

Specifically, as shown in FIG. 5C , the base 101 includes a first substrate 1011 , a second substrate 1012 located below the first substrate 1011 , an insulating layer 1013 disposed between the first substrate 1011 and the second substrate 1012 , a first device region 110 , and a second device region 120 .

The first substrate 1011 and the second substrate 1012 can be any semiconductor material constituting silicon on insulator (SOI), wherein illustrative examples of silicon-containing semiconductor materials that can be used as substrates include: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), ceramic substrates of alumina, quartz or glass substrates, etc.

The buried insulating layer may include any of several dielectric materials, non-limiting examples of which include oxides, nitrides and oxynitrides, in particular, oxides, nitrides and oxynitrides of silicon, but not oxides, nitrides and oxynitrides of other elements. The buried insulating layer may include crystalline or amorphous dielectric materials, with crystalline dielectric materials typically being selected. The buried insulating layer may be formed by any of several methods, non-limiting examples of which include ion implantation methods, thermal or plasma oxidation or nitridation methods, chemical vapor deposition (CVD) methods and physical vapor deposition (PVD) methods. Typically, the buried insulating layer includes an oxide of a semiconductor material from a semiconductor substrate constituting the base (i.e., an oxide of the semiconductor substrate of the base). Typically, the buried insulating layer has a thickness from about to approximately of In at least one embodiment of the present application, as shown in FIG. 1 , the insulating layer 1013 is made of silicon oxide.

In at least one embodiment of the present application, as shown in FIG1 , the insulating layer 1013 may also be formed using an insulating layer such as one containing polyvinyl phenol, polyimide or siloxane, etc. The insulating layer may be formed by any prior art known to those skilled in the art, preferably a chemical vapor deposition method (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD) or plasma enhanced chemical vapor deposition (PECVD).

In some embodiments of the present application, the base 101 may be formed by a bonding process, for example, as shown in FIG. 5A to FIG. 5C , a second substrate 1012 is provided, an insulating layer 1013 is formed on the surface of the second substrate 1012, and the first substrate 1011 and the second substrate 1012 are bonded to form a whole with the side of the insulating layer 1013 formed thereon, and then the first substrate 1011 is thinned to form the base 101 into a structure similar to an SOI substrate, wherein any suitable method may be used to thin the first substrate 1011, such as one or more of mechanical grinding, chemical mechanical grinding, plate cleaning or etching, etc. In other embodiments, the base 101 may also be formed by other suitable methods.

Next, step S2 is performed, as shown in FIG. 4 , to form at least one isolation structure in the first substrate, each of the isolation structures being located between adjacent device regions to isolate the device regions.

In one example, the step of forming at least one isolation structure in the first substrate includes:

First, as shown in FIG. 5D , the first substrate 1011 is etched to form at least one second trench. The bottom of the second trench may be located in the insulating layer 1013 , or the second trench may further pass through the insulating layer 1013 and be located in the second substrate.

The first substrate may be etched by any prior art known to those skilled in the art to form the second groove, such as wet etching or dry etching. Exemplarily, the dry etching process includes, but is not limited to, reactive ion etching (RIE), ion beam etching, plasma etching or laser ablation or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used, which is not limited in the present application.

Next, as shown in FIG. 5D , a liner 131 is formed on the bottom and sidewalls of the second trench, and a dielectric 132 is filled in the second trench.

The liner (which may be referred to as liner 131) may be formed on the bottom and sidewalls of the second trench by any existing technology familiar to those skilled in the art, such as chemical vapor deposition process or physical vapor deposition process, wherein the chemical vapor deposition process may be a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high-density plasma (HDP) manufacturing process. The liner 131 may be silicon dioxide or its He can choose the material, there is no limitation on this.

The dielectric can be filled in the liner 131 by any existing technology familiar to those skilled in the art, such as chemical vapor deposition (CVD) or physical vapor deposition, etc., wherein the physical vapor deposition process can be selected from low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD) or plasma enhanced chemical vapor deposition (PECVD), etc. As an example, the dielectric 132 can be polysilicon, and a densification step can be performed after the trench is filled.

Next, as shown in FIG. 5D , the dielectric 132 is planarized to form at least one isolation structure 130 .

The electrolyte may be planarized by any prior art known to those skilled in the art, such as a mechanical planarization method or a chemical mechanical polishing planarization method, etc. For example, a chemical mechanical polishing planarization method may be used to planarize the dielectric.

Compared with PN junction isolation and field oxygen isolation region (LOCOS) formed by local oxidation of silicon process, the isolation structure prepared in the present application occupies less substrate surface area and can save more area.

Next, step S3 is performed, as shown in FIG. 4 , a first trench is formed in the second device region, the first trench penetrates the first substrate and the insulating layer, and the bottom of the first trench is located in the second substrate.

In one example, the step of forming a first trench in the second device region includes:

First, as shown in FIG. 5D , a first hard mask layer 1031 is formed on the surface of the first substrate 1011 .

The hard mask material may be any material known to those skilled in the art, including but not limited to SiO ₂ , SiCN or SiN, etc. Preferably, the hard mask material is silicon nitride, and the hard mask material may also be a stack of a silicon nitride material layer and other suitable film layers.

Next, as shown in FIG. 5E , a patterned photoresist layer 1032 is formed on the first hard mask layer 1031 , and an opening of the patterned photoresist layer 1032 corresponds to the second device region 120 .

A patterned photoresist layer 1032 may be formed on the surface of the first hard mask layer 1031 by a photolithography process.

5F, the first hard mask layer 1031, the first substrate 1011 and the insulating layer 1013 are etched at the opening to form the first trench 121. During the etching process, only the insulating layer may be etched without etching the second substrate 1012, or a portion of the second substrate 1012 may be etched. The etching may be dry etching or wet etching, preferably dry etching.

Next, step S4 is performed, as shown in FIG. 4 , to grow an epitaxial layer in the first trench.

The epitaxial layer 1202 may be grown in the first trench 121 by any suitable technique known to those skilled in the art, such as chemical vapor deposition or plasma enhanced chemical vapor deposition (PECVD). The epitaxial layer may be Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP, AsGa or other III-V binary or ternary compounds. Exemplarily, the material of the epitaxial layer 1202 is Si. The epitaxial layer 1202 fills the first trench 121, as shown in FIG5F and FIG5G.

Optionally, the epitaxial layer 1202 may be doped according to a predetermined second device type, for example, by doping with phosphorus or boron.

Next, step S5 is performed, as shown in FIG. 4 , to form a second device in the second device region, wherein the second device is a vertical device.

The second device includes a VDMOS device and/or an IGBT device (eg, a trench IGBT device), wherein the VDMOS device includes a trench MOS device and a SJ-MOS device, or the second device may also be another type of vertical device.

In some embodiments, the second device may also include a vertical double diffused MOS (Vertically Double-diffused Metal Oxide Semiconductor, VDMOS) device, which has the advantages of low switching loss, high input impedance, low driving power, good frequency characteristics and highly linear transconductance, and is increasingly widely used in analog circuits and drive circuits, especially high-voltage power parts, such as DC-DC converters, DC-AC converters, fast switching conversion, relays or motor drives, etc. In the VDMOS device, a source is formed in the first substrate, a gate structure is formed on the surface of the first substrate, the source is located on both sides of the gate structure, and the drain (such as a drain metal layer) covers the bottom surface of the second substrate in the second device area. When the gate structure is applied with a positive voltage to reach its turn-on voltage, a voltage is applied between the source and drain of the VDMOS device (generally the source is positive and the drain is negative), the VDMOS device is turned on, and the current flows vertically downward through the first substrate and the second substrate to reach the drain at the bottom of the second substrate. A drain metal layer is deposited at the bottom of the VDMOS device to form the drain of the VDMOS device. Since the deposited metal has good thermal conductivity, the second device 122 can have good heat dissipation, thereby making the entire device have good thermal conductivity and suitable for high power fields.

Exemplarily, as shown in FIG. 1 and FIG. 2 , the second device 122 may be a trench IGBT device. Compared with a device with a planar gate structure, the trench IGBT device can significantly reduce the on-state voltage drop without increasing the turn-off loss. The main difference between the trench gate structure and the planar gate structure is that, compared with a device with a planar gate, the vertical structure of the trench IGBT device saves the area for making a conductive channel on the silicon surface, which is more conducive to the design of compact cells, that is, more IGBT cells can be made on a unit area of the first substrate 1011, thereby increasing the width of the conductive channel and reducing the channel resistance; the trench gate structure is different from the planar gate structure in that the vertical structure of the trench IGBT device saves the area for making a conductive channel on the silicon surface, which is more conducive to the design of compact cells, that is, more IGBT cells can be made on a unit area of the first substrate 1011, thereby increasing the width of the conductive channel and reducing the channel resistance; The IGBT device includes a collector, and the collector of the trench IGBT device covers the bottom surface of the second substrate in the second device area. Current can be derived from the collector of the trench IGBT device located on the bottom surface of the second substrate in the second device area. Since the collector of the deposited metal has good conductivity and heat dissipation, the trench IGBT device has good conductivity and heat dissipation. Since the insulating layer 1013 is discontinuous in the second device area 120, the first substrate 1011 and the second substrate 1012 in the second device area 120 can be conductive, the trench IGBT device can be conductive with the second substrate 1012, and the trench IGBT device can be conductive with the second substrate 1012 in the second device area 120, thereby improving the space utilization rate of the substrate. Therefore, when the second device 122 of the semiconductor device 100 of the present application is a trench IGBT device, the trench IGBT device has good heat dissipation and conductivity, and is used as the high-power part of the semiconductor device 100. The semiconductor device 100 is suitable for high-power fields.

Exemplarily, as shown in FIG3 , the second device 122 of the second device region 120 can also be a super junction MOS (Super Junction Metal Oxide Semiconductor, SJ-MOS) device, which includes a column region 1221 composed of a plurality of alternatingly arranged N-type conductive columns (not shown) and P-type conductive columns (not shown). By arranging the alternatingly arranged N-type conductive columns and P-type conductive columns, the doping concentration of the drift region of the second device 122 is increased to achieve low on-resistance. In some examples, the bottom end of the column region 1221 passes through the insulating layer 1013 and contacts and conducts with the second substrate 1012. Furthermore, the SJ-MOS device includes a drain (for example, a drain metal layer), and the drain of the SJ-MOS device covers the bottom surface of the second substrate in the second device region. Current can be derived from the drain on the bottom surface of the second substrate in the second device region. Since the drain metal layer has good conductivity and heat dissipation, the conductivity and heat dissipation of the SJ-MOS device are also better; and since the insulating layer 1013 is discontinuous in the second device region 120, the first substrate 1011 and the second substrate 1012 in the second device region 120 can be conductive, so the second device region 120 can be used to manufacture vertical devices, thereby improving the space utilization of the substrate; therefore, when the second device 122 of the semiconductor device 100 of the present application is a SJ-MOS device, the SJ-MOS device has good heat dissipation and conductivity, and the SJ-MOS device can be used as the high-power part of the semiconductor device 100, and the semiconductor device 100 is suitable for high-power fields.

In one example, taking the second device as a vertical device (e.g., a trench IGBT device or a VDMOS device, wherein the VDMOS device includes an SJ-MOS device) as an example, the step of forming the second device in the second device region, as shown in FIGS. 5H to 5K , includes:

First, as shown in FIG. 5I and FIG. 5J , a third trench 123 is formed in the epitaxial layer 1202 .

The epitaxial layer may be etched by any prior art known to those skilled in the art to form the third trench 123, such as wet etching or dry etching. Exemplarily, the dry etching process includes but is not limited to: The method is limited to: reactive ion etching (RIE), ion beam etching, plasma etching or laser ablation or any combination of these methods. A single etching method or more than one etching method may also be used, and the present application does not impose any limitation on this.

Next, as shown in FIG5K , taking the second device as a trench IGBT as an example, an oxide layer 105 is formed on the inner wall of the third trench 123 and the surface of the first substrate 1011, and a gate layer (not shown) is filled in the third trench 123 to form a gate of the second device. The oxide layer on the inner wall of the third trench 123 serves as a gate dielectric layer.

The gate layer can be filled in the third trench by any existing technology familiar to those skilled in the art, such as chemical vapor deposition (CVD), physical vapor deposition, etc., wherein the physical vapor deposition process can be selected from low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD) or plasma enhanced chemical vapor deposition (PECVD), etc. As an example, the gate layer can be polysilicon.

It is worth mentioning that for different types of second devices, the structures formed on one side of the first substrate will be different. For example, if the second device is a trench IGBT, a gate structure is formed in the third trench 123, and an emitter region is formed in the first substrate on both sides of the gate structure, and an emitter metal is formed to cover the emitter region and the gate structure. When the second device is an SJ-MOS device, a column region is formed in the third trench. For the description of the column region, refer to the previous text. A gate structure is formed on the column region, and a source region is formed in the first substrate on both sides of the gate structure, wherein at least part of the source region may also be located in the column region.

Next, a back metal layer is formed to cover the bottom surface of the second substrate in the second device region.

In some embodiments, the second device includes a trench IGBT device, and the back metal layer serves as a collector (ie, a collector metal layer), wherein a collector region may be formed on the bottom surface of the second substrate on the collector metal layer, and current may flow downward from the first substrate to the second substrate and be derived from the collector metal layer.

In some embodiments, the second device includes a VDMOS device, and the back metal layer serves as a drain, wherein a drain region is also formed in the bottom surface of the second substrate, and current can flow downward from the first substrate to the second substrate and be derived from the collector metal layer.

The source region and the drain region may be formed in the semiconductor substrate by an ion implantation process. Specifically, suitable doping ions may be selected according to the type of device to be formed, and no specific limitation is made here.

In one example, the step of forming a third trench in the epitaxial layer includes:

First, as shown in FIG. 5H , a second hard mask layer 1203 is formed on the surface of the epitaxial layer 1202 .

Next, as shown in FIG. 5I , a patterned photoresist layer 104 is formed on the second hard mask layer 1203 and the first hard mask layer 1031 , and an opening of the patterned photoresist layer 104 corresponds to the second hard mask layer 1203 .

A patterned photoresist layer 104 may be formed on the surfaces of the second hard mask layer 1203 and the first hard mask layer 1031 by a photolithography process.

Next, as shown in FIG. 5I , FIG. 5J and FIG. 5K , the second hard mask layer 1203 and a portion of the epitaxial layer 1202 are etched at the opening to form the third trench 123 .

In one example, after forming the third groove, the method further includes: removing the patterned photoresist layer, the first hard mask layer and the second hard mask layer on other parts outside the isolation structure, that is, a portion of the first hard mask layer 1031 is retained on the top surface of the isolation structure, so that the isolation structure can play a better insulating isolation role.

Next, step S6 is performed, as shown in FIG4 , to form a first device in the first device region. In the first device region 110 of the semiconductor device 100, the first device 111 and the devices adjacent thereto are completely isolated and insulated by the isolation structure 130 and the insulating layer 1013, so the first device 111 has good insulation capability, wherein the first device 111 may be a CMOS device, and the fields in which the CMOS device may be applied include, but are not limited to, for example, logic circuits, analog circuits, mixed signal circuits and/or any suitable low-power integrated circuits. In other embodiments, the semiconductor device includes an interconnection metal structure (not shown) formed on the first substrate. The interconnection metal structure is configured to provide electrical interconnection between active devices and/or passive devices formed in the first substrate, the first device region and/or the second device region.

As shown in Figure 1, the floating body effect is an effect of transistors made of silicon on an insulator. Its body potential and bias are related to the carrier recombination process; the transistor forms a capacitor relative to the substrate. Charges accumulate on the capacitor, causing adverse effects. The floating body effect is highly correlated with the capacitor, so when the SOI thickness is large, the floating body effect can be ignored. In addition, the carriers of the first device, such as planar MOS, are increased by surface injection, and the substrate concentration itself is low, and the carrier concentration is low, so the carrier recombination process is relatively weak on both sides of the SOI.

It is worth mentioning that the above steps can be exchanged or performed alternately without conflict. For example, the first device can be formed first and then the second device, or some steps of manufacturing two devices can be performed simultaneously.

So far, some descriptions of the manufacturing method of the semiconductor device of the present application have been completed, but it can be understood that in order to achieve a complete device structure, other process steps may be performed.

The semiconductor device obtained by the manufacturing method of the present application has good heat dissipation and is suitable for application in high-power fields.

The present application has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of example and illustration, and are not intended to limit the present application to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present application is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present application, and these variations and modifications all fall within the scope of protection claimed by the present application. The scope of protection of the present application is defined by the attached claims and their equivalents.

Claims

A semiconductor device, comprising:

A substrate, comprising a first substrate, a second substrate and an insulating layer disposed between the first substrate and the second substrate, wherein the substrate comprises at least two device regions, the at least two device regions comprising at least one first device region and at least one second device region, wherein in the first device region, the first substrate and the second substrate are isolated by the insulating layer; in the second device region, the insulating layer is discontinuous, and at least a portion of the surface of the first substrate is connected to at least a portion of the surface of the second substrate;

At least one isolation structure, disposed in the first substrate and located between adjacent device regions to isolate the device regions;

A first device, disposed on the first substrate and located in the first device region;

The second device is arranged in the second device area, and the second device is a vertical device.
The semiconductor device according to claim 1, characterized in that when the second device is a vertical double diffused MOS device, the vertical double diffused MOS device comprises a drain, and the drain covers the bottom surface of the second substrate in the second device region.
The semiconductor device according to claim 1, characterized in that when the second device is a trench IGBT device, the trench IGBT device comprises a collector, and the collector covers a bottom surface of the second substrate in the second device region.
The semiconductor device according to claim 1 is characterized in that, when the second device is a super junction MOS device, the super junction MOS device forms a column region in the second device region, and the super junction MOS device includes a drain, and the drain covers the bottom surface of the second substrate in the second device region.
The semiconductor device according to claim 1, wherein an operating voltage of the first device is lower than an operating voltage of the second device.
The semiconductor device according to claim 1 is characterized in that a liner is formed on the sidewall of the isolation structure, and a dielectric is filled in the isolation structure.
The semiconductor device according to claim 1, characterized in that a first trench is formed in the second device region of the first substrate, the first trench penetrating the first substrate and the insulating layer. The first trench is filled with an epitaxial layer, and the epitaxial layer is used to form the second device.
A method for manufacturing a semiconductor device, comprising:

Providing a substrate, the substrate comprising a first substrate, a second substrate and an insulating layer disposed between the first substrate and the second substrate, the substrate comprising at least two device regions, the at least two device regions comprising at least one first device region and at least one second device region;

forming at least one isolation structure in the first substrate, each of the isolation structures being located between adjacent device regions to isolate the device regions;

forming a first trench in the second device region, wherein the first trench penetrates the first substrate and the insulating layer;

growing an epitaxial layer in the first trench;

forming a second device in the second device region, wherein the second device is a vertical device; and

A first device is formed in the first device region.
The manufacturing method according to claim 8, characterized in that the second device comprises a trench IGBT device, wherein the step of forming the second device in the second device region comprises:

forming a third trench in the epitaxial layer;

forming an oxide layer on the inner wall of the third trench and the surface of the first substrate and filling a gate layer in the third trench to form a gate of the second device;

A collector electrode is formed to cover the bottom surface of the second substrate in the second device region.
The manufacturing method according to claim 8, characterized in that the second device comprises a vertical double diffused MOS device, wherein the step of forming the second device in the second device region comprises:

A drain is formed to cover the bottom surface of the second substrate in the second device region.