WO2024174710A1

WO2024174710A1 - Stacked electronic device, integrated filter, filtering circuit and electronic apparatus

Info

Publication number: WO2024174710A1
Application number: PCT/CN2023/140982
Authority: WO
Inventors: 周雨进; 韦皓宇; 周骏; 沈亚
Original assignee: 南京国博电子股份有限公司
Priority date: 2023-02-23
Filing date: 2023-12-22
Publication date: 2024-08-29

Abstract

The present application relates to a stacked electronic device, an integrated filter, a filtering circuit and an electronic apparatus. The stacked electronic device comprises a multi-layer medium layer (101), a first pattern conductor (201), at least two channel conductors (401) and a capacitive structure (301), wherein the first pattern conductor (201), the capacitive structure (301), the channel conductors (401), and coupling paths therebetween form a three-dimensional integrated closed loop in a three-dimensional space; and the projection of the first pattern conductor (201) on a face perpendicular to a stacking direction at least partially overlaps with the projections of a plurality of metallized electrodes of the capacitive structure (301) on the face perpendicular to the stacking direction. The filtering circuit comprises a first input/output electrode, a second input/output electrode, a first band-stop function unit, a second band-stop function unit, a third band-stop function unit, a first matching function unit, a second matching function unit, a third matching function unit, a fourth matching function unit, a fifth matching function unit, a sixth matching function unit, a seventh matching function unit, an eighth matching function unit, a first potential end and a second potential end.

Description

Stacked electronic device, integrated filter, filter circuit and electronic device

Related Applications

This application claims the priority of Chinese patent application No. 202310154880.7, filed on February 23, 2023, entitled “Stacked electronic device, integrated filter and electronic device”, and the priority of Chinese patent application No. 202310156865.6, filed on February 23, 2023, entitled “A filter circuit”, the entire text of which is hereby incorporated by reference.

Technical Field

The present application relates to the technical field of stacked electronic devices, integrated filters and filter circuits.

Background Art

At present, the complexity of wireless RF communication system systems and modes is constantly increasing, especially the terminal equipment of today's mobile communication system, which often needs to support different communication modes such as 2G, 3G, 4G, 5G, WiFi, etc. in the limited space of the same terminal equipment, which makes the number of RF working bands supported by related equipment continue to increase. Therefore, as a key component in wireless terminals to filter out clutter and ensure the normal operation of multi-band fusion of the system, the number of filters required has also increased significantly, which has brought great challenges to the integration of terminal RF systems, especially the miniaturization integration capability of related filters.

As the basic component of the filter, the resonator plays a decisive role in the miniaturization capability and selection performance of the filter. Therefore, for filters in the context of high-density integrated communication terminal applications, how to improve the resonator Q value performance in an extremely limited space while further reducing the resonator size is the focus of high-density integrated filter design and a difficult problem that the industry needs to continuously solve.

In addition, the bandpass filter is a device used for frequency selection, which is used to select the required signal in the radio frequency link and suppress the unwanted signal to ensure that the overall noise (spurious) of the system is in a controllable state. It is widely used in wireless radio frequency systems such as communication, radar, and detection. In the development process of the bandpass filter, the design of the circuit topology architecture is particularly critical, which is directly related to the miniaturization capability, integration capability, low loss capability and frequency selection capability of the developed filter. Generally speaking, in order to obtain better frequency selection performance, it is often achieved by increasing the filter order, but this method will greatly increase the number of filter elements (unit structure) and the overall structural complexity, especially in the filter design based on lumped parameters. The increase in the filter order will directly lead to a surge in the number of inductor elements, which brings huge challenges to the miniaturization, integration, and low loss design of filters in high-density radio frequency integrated circuit systems. Therefore, how to use filters with fewer orders to achieve superior filter response has always been a pain point and hot issue in filter design research.

On the other hand, in order to further reduce the size of wireless communication and perception terminals, mounting interfaces such as conductive bumps, BGA solder balls, Bumps, Cu-Pillars, etc. are usually used to connect the filter (or resonator) to its metallized mounting surface. However, due to the limitations of mounting alignment accuracy and the existence of process errors during the manufacturing process, the height consistency of the mounting interfaces (such as conductive bumps, BGA solder balls, BumP, Cu-Pillar, etc.) used to connect the filter and its mounting surface will inevitably fluctuate, and this fluctuation will have an adverse effect on the performance consistency and yield rate during the large-scale application of the filter. This effect is particularly prominent in the use of high-frequency, high-density integrated filters. Therefore, it is of great significance to improve the tolerance capability of high-density integrated filter structures (or resonator structures) in batch applications at the design level, and minimize the impact of height changes of mounting interfaces such as conductive bumps, BGA solder balls, Bumps, Cu-Pillar, etc. on device performance during the installation process, which is of great significance to the development of high-density integrated wireless communication and perception products.

Summary of the invention

The purpose of the present application is to provide a stacked electronic device, whose structure has the advantages of miniaturization and high quality factor; at the same time, in the use scenario where the device needs to be flipped or labeled on the mounting surface through a mounting interface in the form of a conductive bump, BGA solder ball, Bump, Cu-Pillar, etc., the performance characteristics of the proposed stacked electronic device have a strong tolerance for the process fluctuation (error) of the mounting interface height, can significantly improve the device processing process error and the adverse effects of the installation process error in its application on its performance batch consistency, which is conducive to the large-scale manufacturing of devices and the improvement of the yield rate in applications.

In order to achieve the above objectives, the solution of this application is:

The present application provides a stacked electronic device in the first aspect, comprising: a multi-layer medium layer, formed by stacking a plurality of dielectric layers along a stacking direction; a first pattern conductor, formed such that when viewed from the stacking direction, its projection on a plane perpendicular to the stacking direction is centered around a point and arranged in a circle around the point; the first pattern conductor is formed on the surface of the dielectric layer or between the dielectric layers; at least two via conductors penetrate the dielectric layer along the stacking direction; the first pattern conductor is coupled with the via conductor; a capacitive structure is formed by coupling a plurality of metallized electrodes that face each other; the first pattern conductor is coupled with the capacitive structure through the via conductor; the first pattern conductor, the capacitive structure, the via conductor and the coupling path therebetween form a three-dimensional integrated closed loop in a three-dimensional space. The projection of the first pattern conductor on a plane perpendicular to the stacking direction at least partially overlaps with the projection of the plurality of metallized electrodes of the capacitive structure on a plane perpendicular to the stacking direction.

In one of the embodiments, the capacitive structure of the stacked electronic device is arranged between the first pattern conductor and the mounting surface along the stacking direction, and the mounting surface is the surface of the mounting carrier, and the mounting carrier is a carrier for mounting or fixing the stacked electronic device, or a carrier for mounting or fixing any electronic device composed of the stacked electronic device; the projection of the first pattern conductor on the mounting surface and the projection of multiple metallized electrodes of the capacitive structure that are facing each other on the mounting surface at least partially overlap.

In one embodiment, the capacitive structure of the stacked electronic device has a plurality of metallized electrodes in a mutually facing relationship formed on the surface of a dielectric layer or between dielectric layers;

In one embodiment, the capacitive structure of the stacked electronic device is formed by three or more metallized electrodes facing each other.

In one embodiment, the projection of the first pattern conductor of the stacked electronic device on a plane perpendicular to the stacking direction is formed by extending a fold line around a point with a point as the center.

In one embodiment, the projection of the first pattern conductor of the stacked electronic device on a plane perpendicular to the stacking direction is formed by extending an arc around a point with a point as the center.

In one embodiment, the projection of the first pattern conductor of the stacked electronic device on a plane perpendicular to the stacking direction is formed by spirally extending around a point with the point as the center.

In one of the embodiments, a projection of a first pattern conductor of a stacked electronic device on a plane perpendicular to a stacking direction is formed by a combination of a spiral line and a zigzag line.

In one embodiment, the stacked electronic device further includes a first external terminal and a second external terminal, the first external terminal and the second external terminal are formed of metallized materials, and the first external terminal and the second external terminal are formed in a three-dimensional integrated closed loop.

In one embodiment, the stacked electronic device further includes at least one second pattern conductor formed on the surface of the dielectric layer or between the dielectric layers, and the second pattern conductor is formed so that when viewed from the stacking direction, its projection on the plane perpendicular to the stacking direction is centered on a point and is arranged around the point; the second pattern conductor is coupled to the first pattern conductor through a via conductor, and the second pattern conductor is coupled to the capacitive structure; the second pattern conductor, the first pattern conductor, the capacitive structure, the via conductor and the coupling path therebetween form a three-dimensional integrated closed loop in three-dimensional space. In this case, the second pattern conductor of the stacked electronic device can be arranged between the first pattern conductor and the mounting surface along the stacking direction, and the mounting surface is the surface of the mounting carrier, and the mounting carrier is a carrier for mounting or fixing the stacked electronic device, or a carrier for mounting or fixing any electronic device composed of the stacked electronic device; the projection of the first pattern conductor on the mounting surface at least partially overlaps with the projection of multiple metallized electrodes of the capacitive structure on the mounting surface. In addition, the projection of the second pattern conductor on the plane perpendicular to the stacking direction is centered on a point and is formed by at least one of a straight line, a broken line, an arc line, and a spiral line extending from the point.

Compared with the current situation that the conventional resonator flat integration method occupies a large amount of device plane load space, the stacked electronic device disclosed in the present application uses a first pattern conductor, a capacitive structure and more than two through-hole conductors to form a three-dimensional space. The three-dimensional integrated closed loop reduces the planar size occupied by the device, thereby realizing the miniaturization of the resonance unit. In the present application, the first pattern conductor is formed as a structure centered on a point and spirally arranged around the point. This structure improves space utilization and can further reduce the planar size of the stacked electronic device to realize the miniaturization of the resonance unit. On the other hand, the introduction of two path conductors reduces the occupied area of the physical structure corresponding to the equivalent inductance value required by the resonance unit, thereby further realizing the miniaturization of the resonance unit. Therefore, the stacked electronic device disclosed in the present application has outstanding miniaturization capabilities.

The stacked electronic device disclosed in the present application is formed into a three-dimensional structure in space, which is conducive to achieving a higher quality factor than the conventional flat-type integrated resonator structure, thereby facilitating lower insertion loss and higher frequency selectivity when using the stacked electronic device to form a filter.

The stacked electronic device disclosed in the present application utilizes a capacitive structure as a barrier between the first pattern conductor and the mounting surface, which can confine most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device within the dielectric layer between the first pattern conductor and the capacitive structure, thereby increasing the stability of the electromagnetic field between the first pattern conductor and the mounting surface, and reducing the adverse effects of height fluctuations of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the performance of the stacked electronic device. On the other hand, in the present application, the three-dimensional integrated structure formed by the stacked electronic device increases the distance between the first pattern conductor and the mounting surface, and reduces the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the performance of the stacked electronic device. Therefore, the performance of the stacked electronic device disclosed in the present application has a strong tolerance capability for the height error of the mounting interface.

Another object of the present application is to provide an integrated filter, the resonator structure of which is based on the stacked electronic device proposed above, and the overall structure has a compact topology and outstanding miniaturization capability, and has out-of-band multi-transmission zero characteristics and excellent frequency selection characteristics, which are conducive to applications in high-density integration scenarios. In addition, the filter effectively improves the tolerance of the filter to process fluctuations (errors) of installation interfaces such as conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. in actual batch installation applications through clever structural design innovations, which is conducive to improving the yield of large-scale production and delivery of filters.

In order to achieve the above objectives, the solution of this application is:

In a second aspect, the present application provides an integrated filter, comprising a first input-output terminal, a second input-output terminal, a first module, a second module, a third module, a first common terminal, and a second common terminal; the first input-output terminal, the second input-output terminal, the first common terminal, and the second common terminal are formed of a metallized material;

The first module includes a first connection terminal, a first potential terminal, a first stacked electronic device, and at least one first additional capacitive structure; the first connection terminal is formed of a metallized material; the first stacked electronic device is any of the above-mentioned stacked electronic devices; the first additional capacitive structure is formed by coupling a plurality of metallized electrodes that are in a mutually facing relationship; the first additional capacitive structure is configured on a coupling path between the first stacked electronic device and the first connection terminal, or the first additional capacitive structure is configured on a coupling path between the first stacked electronic device and the first potential terminal;

The second module includes a second connection terminal, a second potential terminal, a second stacked electronic device, and at least one second additional capacitive structure; the second connection terminal is formed of a metallized material; the second stacked electronic device is any of the above-mentioned stacked electronic devices; the second additional capacitive structure is formed by coupling a plurality of metallized electrodes that face each other; the second additional capacitive structure is arranged on a coupling path between the second stacked electronic device and the second connection terminal, or the second additional capacitive structure is arranged on a coupling path between the second stacked electronic device and the second potential terminal;

The third module includes a third connection terminal, a fourth connection terminal, a third stacked electronic device, and at least one third additional capacitive structure; the third connection terminal and the fourth connection terminal are formed of metallized materials; the third stacked electronic device is any of the above-mentioned stacked electronic devices; the third additional capacitive structure is formed by coupling a plurality of metallized electrodes that are in a mutually facing relationship; the third additional capacitive structure is configured on a coupling path between the third stacked electronic device and the third connection terminal, and/or the third additional capacitive structure is configured on a coupling path between the third stacked electronic device and the fourth connection terminal;

The first connection end of the first module and the third connection end of the third module are coupled to the first common end, and the first common end is coupled to the first input-output end; the second connection end of the second module and the fourth connection end of the third module are coupled to the second common end, and the second common end is coupled to the second input-output end;

In one embodiment, the first module further comprises at least one first additional inductive structure, the first additional inductive structure being arranged on a coupling path between a first connection end of the first module and a first stacked electronic device of the first module; and /or, the first additional inductive structure is arranged on the coupling path between the first connection end of the first module and the first additional capacitive structure of the first module; and/or, the first additional inductive structure is arranged on the coupling path between the first stacked electronic device of the first module and the first additional capacitive structure of the first module; and/or, the first additional inductive structure is arranged on the coupling path between the first potential end of the first module and the first additional capacitive structure of the first module; and/or, the first additional inductive structure is arranged on the coupling path between the first potential end of the first module and the first stacked electronic device of the first module; the second module also includes at least one second additional inductive structure, the second additional inductive structure is arranged between the second stacked electronic device of the second module and The first additional inductive structure and the second additional inductive structure are arranged on a coupling path between the second connection end of the second module and the second additional capacitive structure of the second module; and/or, the second additional inductive structure is arranged on a coupling path between the second stacked electronic device of the second module and the second additional capacitive structure of the second module; and/or, the second additional inductive structure is arranged on a coupling path between the second potential end of the second module and the second additional capacitive structure of the second module; and/or, the second additional inductive structure is arranged on a coupling path between the second potential end of the second module and the second stacked electronic device of the second module; the first additional inductive structure and the second additional inductive structure are formed of metallized materials. In this case, the projection of the first additional inductive structure on a plane perpendicular to the stacking direction of the first stacked electronic device is formed by at least one of a straight line, a folded line, an arc, and a spiral extending from a point; the first additional inductive structure is arranged between the first pattern conductor and the mounting surface of the first stacked electronic device along the stacking direction of the first stacked electronic device, and the mounting surface is the surface of the mounting carrier, and the mounting carrier is a carrier for mounting or fixing an integrated filter, or a carrier for mounting or fixing any electronic device composed of an integrated filter. In addition, the projection of the second additional inductive structure on a plane perpendicular to the stacking direction of the second stacked electronic device is formed by at least one of a straight line, a folded line, an arc, and a spiral extending from a point; the second additional inductive structure is arranged between the first pattern conductor and the mounting surface of the second stacked electronic device along the stacking direction of the second stacked electronic device. Alternatively, the first additional inductive structure and the second additional inductive structure may be formed on the surface of the mounting carrier or inside the mounting carrier; in addition, the first connection terminal may be formed on the first stacked electronic device of the first module; or, the first connection terminal is coupled to the first stacked electronic device of the first module; or, the first connection terminal is formed on the first additional capacitive structure of the first module; or, the first connection terminal is coupled to the first additional capacitive structure of the first module; or, the first connection terminal is formed on the first additional inductive structure of the first module; or, the first connection terminal is coupled to the first additional inductive structure of the first module; the first potential terminal is formed on the first stacked electronic device of the first module; or, the first potential terminal is coupled to the first stacked electronic device of the first module; or, the first potential terminal is formed on the first stacked electronic device of the first module. The first potential terminal is formed on the first additional capacitive structure of the first module; or, the first potential terminal is coupled with the first additional capacitive structure of the first module; or, the first potential terminal is formed on the first additional inductive structure of the first module; or, the first potential terminal is coupled with the first additional inductive structure of the first module; the second connection terminal is formed on the second stacked electronic device of the second module; or, the second connection terminal is coupled with the second stacked electronic device of the second module; or, the second connection terminal is formed on the second additional capacitive structure of the second module; or, the second connection terminal is coupled with the second additional capacitive structure of the second module; or, the second connection terminal is formed on the second additional inductive structure of the second module; or, the second connection terminal is coupled with the second additional inductive structure of the second module; the second potential terminal is formed on the second module or the second potential terminal is coupled to the second stacked electronic device of the second module; or the second potential terminal is formed on the second additional capacitive structure of the second module; or the second potential terminal is coupled to the second additional capacitive structure of the second module; or the second potential terminal is formed on the second additional inductive structure of the second module; or the second potential terminal is coupled to the second additional inductive structure of the second module; the third connection terminal is formed on the third stacked electronic device of the third module; or the third connection terminal is coupled to the third stacked electronic device of the third module; or the third connection terminal is formed on the third additional capacitive structure of the third module; or the third connection terminal is coupled to the third additional capacitive structure of the third module; the fourth connection terminal is formed on the third layer of the third module; The fourth connection terminal is connected to the third stacked electronic device of the third module; or, the fourth connection terminal is formed on the third additional capacitive structure of the third module; or, the fourth connection terminal is coupled to the third additional capacitive structure of the third module; in addition, the first connection terminal shares the same metallized electrode with the first stacked electronic device of the first module; or, the first connection terminal shares the same metallized electrode with the first additional capacitive structure of the first module; or, the first connection terminal shares the same metallized electrode with the first additional inductive structure of the first module; the first potential terminal shares the same metallized electrode with the first stacked electronic device of the first module; or, the first potential terminal shares the same metallized electrode with the first additional capacitive structure of the first module; or, the first potential terminal and The first additional inductive structure of the first module shares the same metallized electrode; the second connection terminal shares the same metallized electrode with the second stacked electronic device of the second module; or, the second connection terminal shares the same metallized electrode with the second additional capacitive structure of the second module; or, the second connection terminal shares the same metallized electrode with the second additional inductive structure of the second module; the second potential terminal shares the same metallized electrode with the second stacked electronic device of the second module; or, the second potential terminal shares the same metallized electrode with the second additional capacitive structure of the second module; or, the second potential terminal shares the same metallized electrode with the second additional inductive structure of the second module; the third connection terminal shares the same metallized electrode with the third stacked electronic device of the third module; or, the third connection terminal shares the same metallized electrode with the third additional The capacitive structures share the same metallized electrode; the fourth connection terminal and the third stacked electronic device of the third module share the same metallized electrode; or, the fourth connection terminal and the third additional capacitive structure of the third module share the same metallized electrode; alternatively, the integrated filter may include at least one fifth additional capacitive structure; the fifth additional capacitive structure is configured on the coupling path between the first input-output terminal and the first common terminal; and/or, the fifth additional capacitive structure is configured on the coupling path between the second input-output terminal and the second common terminal; the fifth additional capacitive structure is formed by coupling a plurality of metallized electrodes that are facing each other; the first additional capacitive structure of the first module is configured on the coupling path between the first stacked electronic device and the first connection terminal, and the first additional inductive structure of the first module is configured on the coupling path between the first stacked electronic device and the first connection terminal. The first module is configured on a coupling path between a first potential terminal of a module and a first stacked electronic device of the first module; the second additional capacitive structure of the second module is configured on a coupling path between the second stacked electronic device and the second connection terminal, and the second additional inductive structure of the second module is configured on a coupling path between the second potential terminal of the second module and the second stacked electronic device of the second module; alternatively, the integrated filter may include at least one sixth additional capacitive structure; the sixth additional capacitive structure is configured on a coupling path between the first input-output terminal and the first common terminal; and/or the sixth additional capacitive structure is configured on a coupling path between the second input-output terminal and the second common terminal; the sixth additional capacitive structure is formed by coupling a plurality of metallized electrodes that are facing each other; the first additional capacitive structure of the first module The first additional inductive structure of the first module is configured on a coupling path between the first additional capacitive structure of the first module and the first stacked electronic device of the first module, or the first additional inductive structure of the first module is configured on a coupling path between the first additional capacitive structure of the first module and the first potential end; the second additional capacitive structure of the second module is configured on a coupling path between the second stacked electronic device and the second potential end, the second additional inductive structure of the second module is configured on a coupling path between the second additional capacitive structure of the second module and the second stacked electronic device of the second module, or the second additional inductive structure of the second module is configured on a coupling path between the second additional capacitive structure of the second module and the second potential end.

In one embodiment, the first to third additional capacitive structures include fourth to sixth metallized electrodes, the fourth metallized electrode and the fifth metallized electrode are formed in different dielectric layers and face each other, and the fifth metallized electrode and the sixth metallized electrode are formed in different dielectric layers and face each other. In this case, the overlapping portion of the projections of the fourth metallized planar electrode and the fifth metallized planar electrode on the mounting surface does not overlap with the overlapping portion of the projections of the fifth metallized planar electrode and the sixth metallized planar electrode on the mounting surface;

In one embodiment, the positional relationship among the first stacked electronic device, the second stacked electronic device, and the third stacked electronic device is configured as follows: a projection of the first pattern conductor of the third stacked electronic device on the mounting surface is sandwiched between a projection of the first pattern conductor of the first stacked electronic device on the mounting surface and a projection of the first pattern conductor of the second stacked electronic device on the mounting surface; or, a projection of the first pattern conductor of the third stacked electronic device on a surface perpendicular to the stacking direction is sandwiched between a projection of the first pattern conductor of the first stacked electronic device on a surface perpendicular to the stacking direction and a projection of the first pattern conductor of the second stacked electronic device on a surface perpendicular to the stacking direction.

In one embodiment, the projection of the first module on the mounting surface, the projection of the second module on the mounting surface, and the projection of the third module on the mounting surface partially overlap, and the mounting surface is the surface of the mounting carrier, and the mounting carrier is a carrier for mounting or fixing the integrated filter, or a carrier for mounting or fixing any electronic device composed of the integrated filter.

In one embodiment, a plurality of metallized electrodes in a mutually facing relationship of the first additional capacitive structure can be formed on the surface of a dielectric layer or between dielectric layers in the first stacked electronic device; a plurality of metallized electrodes in a mutually facing relationship of the second additional capacitive structure can be formed on the surface of a dielectric layer in the second stacked electronic device. or between dielectric layers; a third additional capacitive structure having a plurality of metallized electrodes in a facing relationship with each other may be formed on the surface of the dielectric layer or between dielectric layers in the third stacked electronic device;

In one embodiment, the projection of the first additional capacitive structure on a plane perpendicular to the stacking direction of the first stacked electronic device at least partially overlaps with the projection of the first pattern conductor of the first stacked electronic device on a plane perpendicular to the stacking direction of the first stacked electronic device; the projection of the second additional capacitive structure on a plane perpendicular to the stacking direction of the second stacked electronic device at least partially overlaps with the projection of the first pattern conductor of the second stacked electronic device on a plane perpendicular to the stacking direction of the second stacked electronic device; the projection of the third additional capacitive structure on a plane perpendicular to the stacking direction of the third stacked electronic device at least partially overlaps with the projection of the first pattern conductor of the third stacked electronic device on a plane perpendicular to the stacking direction of the third stacked electronic device;

In one of the embodiments, at least one fourth additional capacitive structure is included, and the fourth additional capacitive structure is configured on the coupling path between the first input-output terminal and the first common terminal; and/or, the fourth additional capacitive structure is configured on the coupling path between the second input-output terminal and the second common terminal; the fourth additional capacitive structure is formed by coupling a plurality of metallized electrodes that are facing each other. In this case, the fourth additional capacitive structure includes the seventh to ninth metallized electrodes, the seventh metallized electrode and the eighth metallized electrode are formed in different dielectric layers and face each other, and the eighth metallized electrode and the ninth metallized electrode are formed in different dielectric layers and face each other. In addition, the first common terminal can share the same metallized electrode with the first connection terminal of the first module, the third connection terminal of the third module, and the fourth additional capacitive structure; the second common terminal can share the same metallized electrode with the second connection terminal of the second module, the fourth connection terminal of the third module, and the fourth additional capacitive structure;

In one embodiment, the first common terminal of the integrated filter is formed on the first module, or the first common terminal is formed on the third module; the second common terminal is formed on the second module, or the second common terminal is formed on the third module;

In one embodiment, the first common terminal of the integrated filter and the first connection terminal of the first module share the same metallized electrode; or, the first common terminal and the third connection terminal of the third module share the same metallized electrode; the second common terminal and the second connection terminal of the second module share the same metallized electrode; or, the second common terminal and the fourth connection terminal of the third module share the same metallized electrode;

In one embodiment, the first common terminal of the integrated filter shares the same metallized electrode with the first connection terminal of the first module and the third connection terminal of the third module; the second common terminal shares the same metallized electrode with the second connection terminal of the second module and the fourth connection terminal of the third module;

In one embodiment, the projection of a three-dimensional integrated closed loop formed by the first pattern conductor, capacitive structure, via conductor and coupling paths therebetween in three-dimensional space on a plane perpendicular to the long side of the multilayer medium layer of the integrated filter, the projection of a three-dimensional integrated closed loop formed by the first pattern conductor, capacitive structure, via conductor and coupling paths therebetween in three-dimensional space on a plane perpendicular to the long side of the multilayer medium layer of the integrated filter of the second stacked electronic device, and the projection of a three-dimensional integrated closed loop formed by the first pattern conductor, capacitive structure, via conductor and coupling paths therebetween in three-dimensional space on a plane perpendicular to the long side of the multilayer medium layer of the integrated filter of the third stacked electronic device at least partially overlap.

According to the above invention, the integrated filter is composed of three modules including the above-mentioned stacked electronic devices. The stacked electronic devices as the resonance unit are formed into a three-dimensional integrated closed loop in three-dimensional space, which has the advantages of miniaturization and high quality factor, so as to facilitate the integrated filter to achieve miniaturization and high frequency selection characteristics. The layout mode of the integrated filter in which the projection of the third module on the mounting surface is sandwiched between the projection of the second module on the mounting surface and the projection of the first module on the mounting surface is conducive to further miniaturization of the filter. In addition, the integrated filter arranges the additional capacitive structure and the additional inductive structure between the first pattern conductor and the mounting surface of the integrated filter, and the projection of the additional capacitive structure or the additional inductive structure on the mounting surface can partially overlap with the projection of the first pattern conductor on the mounting surface, making full use of the space between the first pattern conductor and the mounting surface, realizing the compact layout of the additional capacitive structure and the additional inductive structure, and facilitating further miniaturization of the filter. Therefore, the integrated filter disclosed in the present application has outstanding miniaturization performance.

The integrated filter disclosed in the present application can achieve filtering without the need for an additional resonator structure by flexibly and variously configuring the position, properties and parameters of the capacitive structure or the inductive structure loaded around the stacked electronic device. The filter has multiple transmission zeros in response and enhanced out-of-band suppression, which makes the filter have excellent frequency selection characteristics.

In addition, the capacitive structure and the additional capacitive structure in the stacked electronic device included in the integrated filter disclosed in the present application are arranged between the first pattern conductor and the mounting surface along the stacking direction. The capacitive structure and the additional capacitive structure in the stacked electronic device are used as a barrier between the first pattern conductor and the mounting surface. Most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the filter can be bound in the dielectric layer between the first pattern conductor and the capacitive structure and the additional capacitive structure in the stacked electronic device, thereby increasing the stability of the electromagnetic field between the first pattern conductor and the mounting surface. The adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the filter performance can be effectively reduced, so that the filter performance has a strong tolerance capability for the height error of the mounting interface, which is conducive to improving the yield of large-scale production and delivery of filters.

In a third aspect, the present application provides an electronic device, which includes any one of the above-mentioned stacked electronic devices or any one of the above-mentioned integrated filters.

Another object of the present application is to provide a filtering circuit, which adopts a main functional unit configuration with a number equivalent to that of a low-order bandpass filter, and uses three band-stop functional units as the main body of the filtering circuit. By coordinating with corresponding matching functional units, the number and position of transmission zero points can be flexibly set outside the passband, thereby supporting customized configuration of the circuit's out-of-band suppression performance and selection characteristic response, and providing an effective new solution for improving the performance of miniaturized filtering circuits under high-density integration applications.

The present invention adopts the following technical solutions to achieve the above-mentioned invention object:

In a fourth aspect, the present application provides a filtering circuit, including: a first input-output electrode, a second input-output electrode, a first band-stop characteristic functional unit, a second band-stop functional unit, a third band-stop functional unit, a first matching functional unit, a second matching functional unit, a third matching functional unit, a fourth matching functional unit, a fifth matching functional unit, a sixth matching functional unit, a seventh matching functional unit, an eighth matching functional unit, a first potential end, and a second potential end. The first input-output electrode is connected to one end of the first matching functional unit, the other end of the first matching functional unit is simultaneously connected to one end of the second matching functional unit and one end of the fifth matching functional unit, the other end of the second matching functional unit is connected to one end of the first band-stop functional unit, the other end of the first band-stop functional unit is connected to one end of the third matching functional unit, the other end of the third matching functional unit is simultaneously connected to one end of the fourth matching functional unit and one end of the seventh matching functional unit, the other end of the fourth matching functional unit is connected to the second input-output electrode, the other end of the fifth matching functional unit is connected to one end of the second band-stop functional unit, the other end of the second band-stop functional unit is connected to one end of the sixth matching functional unit, the other end of the sixth matching functional unit is connected to the first potential end, the other end of the seventh matching functional unit is connected to one end of the third band-stop functional unit, the other end of the third band-stop functional unit is connected to one end of the eighth matching functional unit, and the other end of the eighth matching functional unit is connected to the second potential end. The first band-stop functional unit to the third band-stop functional unit are two-port networks with attenuation poles in their transmission characteristics. The first matching functional unit to the eighth matching functional unit are two-port networks;

In one embodiment, the first potential terminal and the second potential terminal are at the same potential as the reference ground.

In one embodiment, the first matching functional unit, the second matching functional unit, the third matching functional unit and the fourth matching functional unit of the filter circuit are composed of elements whose imaginary part of admittance is greater than zero, or elements whose imaginary part of admittance is equal to zero.

In one of the embodiments, the sixth matching functional unit of the filtering circuit is composed of elements whose imaginary part of admittance is greater than zero, and the fifth matching functional unit is composed of elements whose imaginary part of admittance is less than zero; or, the sixth matching functional unit is composed of elements whose imaginary part of admittance is less than zero, and the fifth matching functional unit is composed of a structure whose imaginary part of admittance is greater than zero; or, the sixth matching functional unit is composed of a two-port network whose imaginary part of admittance is greater than zero and a two-port network whose imaginary part of admittance is less than zero connected in series, and the fifth matching functional unit is composed of elements whose imaginary part of admittance is equal to zero.

In one of the embodiments, the eighth matching functional unit of the filtering circuit is composed of elements whose imaginary part of admittance is greater than zero, and the seventh matching functional unit is composed of elements whose imaginary part of admittance is less than zero; or, the eighth matching functional unit is composed of elements whose imaginary part of admittance is less than zero, and the seventh matching functional unit is composed of elements whose imaginary part of admittance is greater than zero; or, the eighth matching functional unit is composed of a two-port network whose imaginary part of admittance is greater than zero and a two-port network whose imaginary part of admittance is less than zero connected in series, and the seventh matching functional unit is composed of elements whose imaginary part of admittance is equal to zero.

In one embodiment, the first band-stop functional unit includes an element whose imaginary part of admittance is greater than zero and an element whose imaginary part of admittance is less than zero, and the element whose imaginary part of admittance is greater than zero and the element whose imaginary part of admittance is less than zero are connected in parallel; or, the first band-stop functional unit includes an element whose imaginary part of admittance is greater than zero, an element whose imaginary part of admittance is less than zero and a third potential terminal, and the element whose imaginary part of admittance is greater than zero, the element whose imaginary part of admittance is less than zero and the third potential terminal are connected in series.

The second band-stop functional unit includes an element whose imaginary part of admittance is greater than zero and an element whose imaginary part of admittance is less than zero, and the element whose imaginary part of admittance is greater than zero and the element whose imaginary part of admittance is less than zero are connected in parallel; or, the second band-stop functional unit includes an element whose imaginary part of admittance is greater than zero, an element whose imaginary part of admittance is less than zero and a fourth potential terminal, and the element whose imaginary part of admittance is greater than zero, the element whose imaginary part of admittance is less than zero and the fourth potential terminal are connected in series.

The third band-stop functional unit includes an element whose imaginary part of admittance is greater than zero and an element whose imaginary part of admittance is less than zero, and the element whose imaginary part of admittance is greater than zero and the element whose imaginary part of admittance is less than zero are connected in parallel; or, the third band-stop functional unit includes an element whose imaginary part of admittance is greater than zero, an element whose imaginary part of admittance is less than zero and a fifth potential terminal, and the element whose imaginary part of admittance is greater than zero, the element whose imaginary part of admittance is less than zero and the fifth potential terminal are connected in series.

In one of the embodiments, the third potential terminal, the fourth potential terminal and the fifth potential terminal of the filter circuit are at the same potential as the reference ground.

In a fifth aspect, the present application provides a circuit, which includes any one of the above-mentioned filter circuits.

The technical solution of the above-mentioned filter circuit adopted in this application has the following beneficial effects:

(1) The filter circuit disclosed in the present invention includes the first to third band-stop function units as the main structure of the circuit, and through the coordinated configuration of the matching function units around the band-stop function units, the filter circuit frequency response multi-transmission zero point characteristics are realized when the number of main function units is equivalent to the number of main function units in the low-order bandpass filter and no additional resonator structure is required, thereby improving the out-of-band suppression performance of the filter circuit. Therefore, the filter circuit disclosed in the present invention has the advantages of miniaturization and high frequency selection characteristics.

(2) The filter circuit disclosed in the present invention can configure the structure, properties and parameters of the first to third band-stop functional units and the first to eighth matching functional units in a diversified manner, so as to realize the flexible deployment of the number and position of the transmission zero points of the filter circuit, so that the filter circuit disclosed in the present invention has the advantage of being able to customize the circuit's out-of-band suppression performance and selection characteristic response according to requirements.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of a stacked electronic device D1 according to Embodiment 1. FIG.

FIG. 2 is a perspective view of a conventional tile-type integrated resonator.

FIG. 3 is a side view of the stacked electronic device D1 according to the first embodiment when it is fixed to a mounting surface.

FIG. 4 is a schematic diagram showing the performance fluctuation of the stacked electronic device D1 according to Embodiment 1 as the height of the mounting interface fluctuates.

FIG. 5 is a side view of a conventional flat-lay integrated resonator being fixed to a mounting surface.

FIG6 is a schematic diagram showing the fluctuation of the resonator performance in a conventional tiled integration method with the height of the mounting interface.

FIG. 7 is a perspective view of a stacked electronic device D2 according to Embodiment II.

FIG8 is a circuit diagram showing a circuit configuration of an integrated filter 3 according to Embodiment III.

FIG. 9 is a perspective view of a first module 701 of the integrated filter 3 according to Embodiment III.

FIG. 10 is a transmissive top view of the first module 701 of the integrated filter 3 according to Embodiment III.

FIG. 11 is a schematic diagram of a two-port network of the first to sixth additional capacitive structures.

FIG12 is a diagram showing the admittance characteristics of the first additional capacitive structure 801 of the integrated filter 3 according to Implementation III.

FIG. 13 is a perspective view of a second module 702 of the integrated filter 3 according to Embodiment III.

FIG. 14 is a transmissive top view of the second module 702 of the integrated filter 3 according to Embodiment III.

FIG. 15 is a perspective view of a third module 703 of the integrated filter 3 according to Embodiment III.

FIG. 16 is a transmissive top view of the third module 703 of the integrated filter 3 according to Embodiment III.

FIG. 17 is a perspective view of the integrated filter 3 according to Embodiment III.

FIG. 18 is a transmissive stereoscopic view of the integrated filter 3 according to Embodiment III from another viewing angle.

FIG. 19 is a plan view of the integrated filter 3 according to Embodiment III when it is fixed to the mounting surface.

FIG. 20 is a perspective view showing the structure of the integrated filter 3 according to Embodiment III when it is fixed to a mounting surface.

FIG. 21 is a side view of the integrated filter 3 according to Embodiment III when it is fixed to the mounting surface.

FIG. 22 is a graph showing reflection and transmission characteristics of the integrated filter 3 according to Embodiment III.

FIG. 23 is a circuit diagram showing a circuit configuration of an integrated filter 4 according to Embodiment IV.

FIG. 24 is a perspective view of a first module 704 of the integrated filter 4 according to Embodiment IV.

FIG. 25 is a perspective view of the first module 704 of the integrated filter 4 according to Embodiment IV from another perspective.

FIG. 26 is a transmissive top view of the first module 704 of the integrated filter 4 according to Embodiment IV.

FIG. 27 is a schematic diagram of a two-port network of the first to second additional inductive structures.

FIG. 28 is a diagram showing the admittance characteristics of the first additional inductive structure 901 of the integrated filter 4 according to Embodiment IV.

FIG. 29 is a perspective view of a second module 705 of the integrated filter 4 according to Embodiment IV.

FIG. 30 is a transmissive top view of the second module 705 of the integrated filter 4 according to Embodiment IV.

FIG. 31 is a perspective view of a third module 703 of the integrated filter 4 according to Embodiment IV.

FIG. 32 is a transmissive top view of the third module 703 of the integrated filter 4 according to Embodiment IV.

FIG. 33 is a perspective view of the integrated filter 4 according to Embodiment IV.

FIG. 34 is a transparent stereoscopic view of the integrated filter 4 of Embodiment IV from another viewing angle.

FIG. 35 is a side view of the integrated filter 4 according to Embodiment IV when it is fixed to the mounting surface.

FIG. 36 is a plan view of the integrated filter 4 according to Embodiment IV when it is fixed to the mounting surface.

FIG. 37 is a perspective view showing the structure of the integrated filter 4 according to Embodiment IV when it is fixed to the mounting surface.

FIG38 is a graph showing reflection and transmission characteristics of the integrated filter 4 according to Embodiment IV.

FIG39 is a circuit diagram showing a circuit configuration of an integrated filter 5 according to Embodiment V. FIG.

FIG. 40 is a perspective view of a first module 704 of the integrated filter 5 according to Embodiment V. FIG.

FIG. 41 is a perspective view of the first module 704 of the integrated filter 5 of Embodiment V from another perspective.

FIG. 42 is a transmissive top view of the first module 704 of the integrated filter 5 according to Embodiment V. FIG.

FIG. 43 is a perspective view of a second module 705 of the integrated filter 5 according to Embodiment V. FIG.

FIG. 44 is a transmissive top view of the second module 705 of the integrated filter 5 according to Embodiment V. FIG.

FIG. 45 is a perspective view of a third module 703 of the integrated filter 5 according to Embodiment V. FIG.

FIG. 46 is a transmissive top view of the third module 703 of the integrated filter 5 according to Embodiment V. FIG.

FIG. 47 is a perspective view of the integrated filter 5 according to Embodiment V. FIG.

FIG. 48 is a transparent stereoscopic view of the integrated filter 5 of Embodiment V from another viewing angle.

FIG. 49 is a side view of the integrated filter 5 according to Embodiment V when it is fixed to the mounting surface.

FIG. 50 is a plan view of the integrated filter 5 according to Embodiment V when it is fixed to the mounting surface.

FIG. 51 is a perspective view showing the structure of the integrated filter 5 according to Embodiment V when it is fixed to a mounting surface.

Figure 52 is a reflection and transmission characteristic diagram of the integrated filter 5 of implementation mode V.

FIG53 is a circuit diagram showing a circuit structure of an integrated filter 6 according to Embodiment VI.

FIG54 is a perspective view of the first module 706 of the integrated filter 6 according to Embodiment VI;

FIG. 55 is a perspective view of the first module 706 of the integrated filter 6 of Embodiment VI from another perspective.

FIG. 56 is a transmissive top view of the first module 706 of the integrated filter 6 according to Embodiment VI.

FIG. 57 is a perspective view of a second module 707 of the integrated filter 6 according to Embodiment VI.

FIG. 58 is a transmissive top view of the second module 707 of the integrated filter 6 according to Embodiment VI.

FIG. 59 is a perspective view of a third module 708 of the integrated filter 6 according to Embodiment VI.

FIG. 60 is a transmissive top view of the third module 708 of the integrated filter 6 according to Embodiment VI.

FIG. 61 is a perspective view of the integrated filter 6 according to Embodiment VI.

FIG62 is a perspective view of the integrated filter 6 of Embodiment VI from another angle.

FIG. 63 is a side view of the integrated filter 6 according to Embodiment VI when it is fixed to the mounting surface.

FIG. 64 is a plan view of the integrated filter 6 according to Embodiment VI when it is fixed to the mounting surface.

FIG. 65 is a perspective view showing the structure of the integrated filter 6 according to Embodiment VI when it is fixed to the mounting surface.

FIG. 66 is a graph showing reflection and transmission characteristics of the integrated filter 6 according to embodiment VI.

FIG67 is a circuit diagram showing a circuit structure of an integrated filter 7 according to Embodiment VII.

FIG68 is a perspective view showing a first module 709 of the integrated filter 7 according to Embodiment VII.

FIG69 is a transparent stereoscopic view of the first module 709 of the integrated filter 7 according to Embodiment VII from another viewing angle.

FIG. 70 is a transmissive top view of the first module 709 of the integrated filter 7 according to Embodiment VII.

FIG. 71 is a perspective view showing a second module 710 of the integrated filter 7 according to Embodiment VII.

FIG. 72 is a transmissive top view of the second module 710 of the integrated filter 7 according to Embodiment VII.

FIG. 73 is a perspective view of a third module 711 of the integrated filter 7 according to Embodiment VII.

FIG. 74 is a transmissive top view of the third module 711 of the integrated filter 7 according to Embodiment VII.

FIG. 75 is a perspective view of the integrated filter 7 according to Embodiment VII.

FIG. 76 is a transparent stereoscopic view of the integrated filter 7 of Embodiment VII from another viewing angle.

FIG. 77 is a side view of the integrated filter 7 according to Embodiment VII when it is fixed to the mounting surface.

FIG. 78 is a plan view of the integrated filter 7 according to Embodiment VII when it is fixed to the mounting surface.

FIG. 79 is a perspective view showing the structure of the integrated filter 7 according to Embodiment VII when it is fixed to the mounting surface.

FIG80 is a graph showing reflection and transmission characteristics of the integrated filter 7 according to embodiment VII.

FIG81 is a circuit diagram of the filter circuit 1 according to implementation VIII of the present application.

Figure 82 is a two-port network schematic diagram of the first to eighth matching functional units in implementation mode VIII of the present application.

FIG83 is a schematic diagram of the structure of the first band-stop functional unit of the filter circuit 1 proposed in implementation VIII of the present application.

FIG84 is a schematic diagram of the structure of the third band-stop functional unit of the filter circuit 1 proposed in implementation VIII of the present application.

Figure 85 is a two-port network schematic diagram of the components in implementation mode VIII of the present application.

FIG86 is a transmission characteristic diagram of the first band-stop functional unit of the filter circuit 1 proposed in implementation mode VIII of the present application.

FIG87 is a top view of the structure of the filter circuit 1 proposed in implementation VIII of the present application.

FIG88 is a structural stereogram of the filter circuit 1 according to implementation example VIII of the present application.

FIG89 is a graph showing the insertion loss and return loss characteristics of the filter circuit 1 according to implementation VIII of the present application.

Figure 90 is a circuit diagram of the filter circuit 2 proposed in implementation mode IX of the present application.

Figure 91 is a top view of the structure of the filter circuit 2 proposed in implementation mode IX of the present application.

Figure 92 is a structural stereogram of the filter circuit 2 proposed in implementation mode IX of the present application.

Figure 93 is an insertion loss and return loss characteristic diagram of the filter circuit 2 proposed in implementation mode IX of the present application.

Figure 94 is a topological diagram of the filter circuit 3 proposed in implementation mode X of the present application.

Figure 95 is a top view of the structure of the filter circuit 3 proposed in implementation mode X of the present application.

FIG96 is a three-dimensional structural diagram of the filter circuit 3 proposed in implementation mode X of the present application.

Figure 97 is an insertion loss and return loss characteristic diagram of the filter circuit 3 proposed in implementation mode X of the present application.

DETAILED DESCRIPTION

The following describes various aspects of the present disclosure. It should be clear that the teachings herein can be embodied in a variety of forms and any specific structure, function, or both disclosed herein are merely representative. Based on the teachings herein, those skilled in the art should recognize that an aspect disclosed herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, using any number of aspects of the aspects set forth herein, a device can be implemented or a method can be practiced. In addition, additional to one or more aspects of the aspects set forth herein or in addition to one or more aspects of the aspects set forth herein, using other structures, functionality, or structure and functionality, such a device can be implemented or such a method can be practiced. In addition, an aspect can include at least one element of a claim.

The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present application. Description, obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "up", "down", "left", and "right", generally refer to the up, down, left, and right of the device in actual use or working state, specifically the drawing direction in the accompanying drawings.

First, the structure of the stacked electronic device D1 of the first embodiment of the present application is described with reference to FIG. 1. FIG. 1 is a perspective view of the stacked electronic device D1 of the first embodiment. The stacked electronic device D1 of the present embodiment comprises a multilayer medium layer 101, a first pattern conductor 201, a capacitive structure 301, and two via conductors 401. The multilayer medium layer 101 is formed by stacking a plurality of dielectric layers along the stacking direction. The dielectric layer can be composed of one or more dielectric materials such as gallium arsenide, silicon carbide, silicon nitride, aluminum nitride, aluminum oxide, glass, and silicon oxide. The first pattern conductor 201 is formed on the surface of the dielectric layer of the multilayer medium layer 101. When the first pattern conductor 201 is viewed from the stacking direction, its projection on the plane perpendicular to the stacking direction is centered at one point and is arranged around the point with a spiral and a fold line; in the present embodiment, the first pattern conductor 201 can be composed of one or more metallized materials such as Ag, Au, and Cu, and is formed into a spiral shape, and the spiral shape includes a bent fold line. The capacitive structure 301 is located below the first pattern conductor along the stacking direction, and is formed by coupling two metallized electrodes that face each other. The two metallized electrodes that face each other are formed between the dielectric layers of the multilayer medium layer 101, and the metallized electrodes can be composed of one or more metallized materials such as Ag, Au, and Cu. Two via conductors 401 penetrate the dielectric layer along the stacking direction. The via conductors can be composed of through holes composed of one or more metallized materials such as Ag, Au, and Cu, or can be composed of solid cylinders composed of one or more metallized materials such as Ag, Au, and Cu. The two via conductors 401 are connected to the first pattern conductor 201 and to the capacitive structure 301. The first pattern conductor 201, the capacitive structure 301, the two via conductors 401, and the coupling paths therebetween form a three-dimensional integrated closed loop in three-dimensional space. The projection of the first pattern conductor 201 on a plane perpendicular to the stacking direction partially overlaps with the projection of the two metallized electrodes of the capacitive structure 301 on a plane perpendicular to the stacking direction.

When the stacked electronic device of the present application is used as a resonant unit of a filter, compared with the current situation where the conventional resonator flat-laying integration method as shown in FIG. 2 occupies a large amount of device plane load space, the stacked electronic device D1 of this embodiment is composed of a first pattern conductor structure 201, a capacitive structure 301, and two via conductors 401 and the coupling path therebetween to form a three-dimensional integrated closed loop in three-dimensional space. The layout of the structure along the stacking direction utilizes the space in the vertical direction, reducing the plane size occupied by the device, thereby realizing the miniaturization of the resonant unit. In this embodiment, the first pattern conductor 201 is formed as a structure that is centered on a point and spirally arranged around the point. The structure improves the space utilization rate, can further reduce the size of the stacked electronic device, and realizes the miniaturization of the resonant unit. The introduction of two via conductors reduces the occupied area of the physical structure corresponding to the equivalent inductance value required by the resonant unit, thereby further realizing the miniaturization of the resonant unit.

The stacked electronic device of the present application is formed into a three-dimensional structure in space, which is conducive to achieving a higher quality factor than the conventional flat-type integrated resonator structure, and the frequency selection performance of the filter is positively correlated with the quality factor of the resonant unit constituting the filter. Therefore, using the above-mentioned stacked electronic device D1 as a resonant unit to constitute a filter is conducive to achieving lower insertion loss and higher frequency selectivity.

FIG3 is a side view of the stacked electronic device D1 of Embodiment 1 when it is fixed to the mounting surface. Referring to FIG3, when the stacked electronic device D1 is fixed to the mounting surface 501 through a mounting interface in the form of a conductive bump, a BGA solder ball, a Bump, a Cu-Pillar, etc., the mounting surface 501 is the surface of a mounting carrier for fixing the stacked electronic device D1 or for fixing any electronic device composed of the stacked electronic device D1, and the mounting carrier is a substrate including at least one layer of metallized material or at least one layer of dielectric layer, such as a PCB substrate, an ABF substrate, a FCBGA substrate, a silicon-based adapter board, a glass-based adapter board, etc. composed of at least one layer of metallized material and at least one layer of dielectric layer. In this embodiment, the filter is fixed on the FCBGA substrate through metallized micro-bumps (BGA, Bump, Cu-pillar, etc.), and is interconnected with other components such as a power amplifier and a low-noise amplifier to realize the function of the RF front-end module. The conductive bumps may be solder bumps, solder balls, etc. deposited on the pads of the mounting carrier. The capacitive structure 301 is located between the first pattern conductor 201 and the mounting surface 501 along the stacking direction. The projection of the first pattern conductor 201 on the mounting surface 501 partially overlaps with the projection of the two metallized electrodes constituting the capacitive structure 301 on the mounting surface 501. The barrier between the conductor 201 and the mounting surface 501 can confine most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D1 to the dielectric layer between the first pattern conductor 201 and the capacitive structure 301, thereby increasing the stability of the electromagnetic field between the first pattern conductor 201 and the mounting surface 501 and reducing the adverse effects of the height error of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-pillars, etc. on the performance of the stacked electronic device D1. FIG. 4 is a schematic diagram of the performance of the stacked electronic device D1 of Implementation Method I fluctuating with the height of the mounting interface. FIG. 5 is a side view of a conventional flat-lay integrated resonator fixed to the mounting surface. FIG. 6 is a schematic diagram of the performance of a conventional flat-lay integrated resonator fluctuating with the height of the mounting interface. Referring to FIG. 4 to FIG. 6, when the stacked electronic device D1 in this embodiment fluctuates with the height h1 of the mounting interface, its performance change is much smaller than the performance change of the resonator structure formed by the conventional flat-lay integrated method when the height h1 of the mounting interface fluctuates. On the other hand, the three-dimensional integrated structure formed by the stacked electronic device D1 increases the distance between the first pattern conductor 201 and the mounting surface 501, and reduces the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-pillars, etc. on the performance of the stacked electronic device. In summary, the performance of the stacked electronic device proposed in this application has a strong tolerance capability for the height fluctuation of the mounting interface.

The above describes the embodiment I of the present application, but the present application is not necessarily limited to the above-mentioned embodiment I, and various changes can be made without departing from the scope of the main purpose. For example, the first pattern conductor 201 of the present embodiment can also be formed as a projection on a plane perpendicular to the stacking direction, with a point as the center, and is formed by extending around the point with a broken line, or extending around the point with an arc line, or extending around the point with a spiral line. The first pattern conductor 201 can also be formed between the dielectric layers of the multilayer medium layer 101. In addition, the metallized electrodes of the capacitive structure 301 that face each other can also be formed on the surface of the dielectric layer of the multilayer medium layer 101; in addition, the stacked electronic device D1 can also further include a first external terminal and a second external terminal, the first external terminal and the second external terminal are composed of a metallized material, and are both formed on a three-dimensional integrated closed loop formed by the first pattern conductor 201, the capacitive structure 301, the two via conductors 401 and the coupling path therebetween in a three-dimensional space, and the first external terminal and the second external terminal are used to connect the stacked electronic device D1 with other devices or structures;

The following describes a stacked electronic device D2 according to Embodiment II of the present application. Embodiment II differs from Embodiment I in that it further comprises a second pattern conductor, and the capacitive structure is composed of three metallized electrodes that face each other;

FIG7 is a perspective view of a stacked electronic device D2 according to Embodiment II. Referring to FIG7, the stacked electronic device D2 according to Embodiment II comprises a multilayer medium layer 102, a first pattern conductor 202, a capacitive structure 302, two via conductors 402, and a second pattern conductor 203. The multilayer medium layer 102 is formed by stacking a plurality of dielectric layers along a stacking direction. The dielectric layer can be made of one or more dielectric materials such as gallium arsenide, silicon carbide, silicon nitride, aluminum nitride, aluminum oxide, glass, and silicon oxide. The first pattern conductor 202 is formed on the surface of the dielectric layer of the multilayer medium layer 102. When the first pattern conductor 202 is viewed along the stacking direction, its projection on a plane perpendicular to the stacking direction is centered on a point and is arranged around the point with a spiral and a fold line, forming a spiral shape in a plane, and the spiral includes a fold line; the first pattern conductor 202 can be made of one or more metallized materials such as Ag, Au, and Cu. The capacitive structure 302 is located below the first pattern conductor along the stacking direction, and is formed by coupling three metallized electrodes that face each other. The three metallized electrodes that face each other are formed between the dielectric layers of the multilayer medium layer 102, and the metallized electrodes can be formed of one or more metallized materials such as Ag, Au, and Cu. Two via conductors 402 penetrate the dielectric layer along the stacking direction. The via conductors 402 can be formed by through holes formed by one or more metallized materials such as Ag, Au, and Cu, or can be formed by solid cylinders formed by one or more metallized materials such as Ag, Au, and Cu. One end of one via conductor 402 is connected to the first pattern conductor 202, and the other end is connected to the capacitive structure 302. One end of another via conductor 402 is connected to the first pattern conductor 202, and the other end is connected to the second pattern conductor 203. The second pattern conductor 203 is located below the first pattern conductor 202 along the stacking direction, and is formed such that when viewed from the stacking direction, its projection on the plane perpendicular to the stacking direction is centered around a point, and is arranged around the point, and is formed by a broken line extending outward from the point; the second pattern conductor 203 can be formed of one or more metallized materials such as Ag, Au, Cu, etc., and is formed into a spiral shape. One end of the second pattern conductor 203 is connected to the via conductor 402, and the other end is connected to the capacitive structure 302. The first pattern conductor 202, the capacitive structure 302, the two via conductors 402, the second pattern conductor 203 and the coupling paths therebetween form a three-dimensional integrated closed loop in three-dimensional space. The projection of the first pattern conductor 202 on the plane perpendicular to the stacking direction partially overlaps with the projection of the three metallized electrodes of the capacitive structure 302 on the plane perpendicular to the stacking direction.

The capacitive structure 302 in this embodiment is formed by coupling three metallized electrodes that face each other. Compared with the method of forming the capacitive structure using two metallized electrodes that face each other, the area of the metallized electrodes in the plane direction is enlarged, which is conducive to enhancing the barrier effect of the capacitive structure on the first pattern conductor and the mounting surface, and further confines most of the electromagnetic field that affects the fluctuation of the equivalent inductance of the stacked electronic device to the dielectric layer between the first pattern conductor 202 and the capacitive structure 302, thereby increasing the stability of the electromagnetic field between the first pattern conductor 202 and the mounting surface, and reducing the adverse effects of the height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillar, etc. on the performance of the stacked electronic device. On the other hand, the three-dimensional integrated structure formed by the stacked electronic device D2 increases the distance between the first pattern conductor 202 and the mounting surface, and reduces the adverse effects of the height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillar, etc. on the performance of the stacked electronic device. In summary, the performance of the stacked electronic device proposed in this application has a strong tolerance capability for the height fluctuation of the mounting interface.

In this embodiment, the second pattern conductor 203 is formed into a structure with one point as the center and spirally arranged around the point, which improves space utilization and can reduce the size of the stacked electronic device.

In addition, the capacitive structure 302 can also be formed by more than three metallized electrodes that are facing each other; the metallized electrodes that are facing each other can also be formed on the surface of the dielectric layer of the multilayer medium layer 102; in addition, the second pattern conductor 203 can also be formed as a projection on a plane perpendicular to the stacking direction, with a point as the center, and a structure formed by one or more combinations of straight lines, broken lines, arcs, and spirals extending from the point.

The integrated filter 3 of implementation mode III of the present application is described below.

This embodiment provides an integrated filter composed of the aforementioned stacked electronic device. The proposed integrated filter is based on the aforementioned stacked electronic device and loaded by an additional capacitive structure, and has the advantages of simple structure, miniaturization, and good out-of-band attenuation characteristics.

Fig. 8 is a circuit diagram of the circuit structure of the integrated filter 3 of implementation mode III. The integrated filter 3 comprises a first input-output terminal 601, a second input-output terminal 602, a first module 701, a second module 702, a third module 703, a first common terminal 603 and a second common terminal 604, a path 11, a path 12, a path 13, a path 14, a path 15 and a path 16; the first input-output terminal 601, the second input-output terminal 602, the first common terminal 603 and the second common terminal 604 are made of one or more metallized materials such as Ag, Au, and Cu;

The first module 701 includes a first connection terminal 605, a first stacked electronic device D3, a first additional capacitive structure 801, a first potential terminal 606, a path 17, and a path 18. The first connection terminal 605 is made of a metallized material, the first stacked electronic device D3 is the structure of the stacked electronic device in the aforementioned embodiment or a modified example thereof, the first additional capacitive structure 801 is formed by coupling a plurality of metallized electrodes facing each other, and the first potential terminal 606 is made of a metallized material for connecting to a reference ground. The path 17 connects the first connection terminal 605 to the first stacked electronic device D3, the path 18 connects the first stacked electronic device D3 to the first potential terminal 606, and the first additional capacitive structure 801 is arranged on the path 18.

The second module 702 includes a second connection terminal 607, a second potential terminal 608, a second stacked electronic device D4, a second additional capacitive structure 802, a path 19, and a path 20. The second connection terminal 607 is made of a metalized material, the second stacked electronic device D4 is the structure of the stacked electronic device in the aforementioned embodiment or a modified example thereof, the second additional capacitive structure 802 is formed by coupling a plurality of metalized electrodes facing each other, the second potential terminal 608 is made of a metalized material, and is used to connect to a reference ground. Path 19 connects the second connection terminal 607 to the second stacked electronic device D4, path 20 connects the second stacked electronic device D4 to the second potential terminal 608, and the second additional capacitive structure 802 is arranged on path 19.

The third module 703 includes a third connection terminal 609, a fourth connection terminal 610, a third stacked electronic device D5, a third additional capacitive structure 803, a path 21, and a path 22. The third connection terminal 609 and the fourth connection terminal 610 are made of metallized materials, the third stacked electronic device D5 is the structure of the stacked electronic device in the aforementioned embodiment or a modified example thereof, and the third additional capacitive structure 803 is formed by coupling a plurality of metallized electrodes that face each other. The path 21 connects the third connection terminal 609 to the third stacked electronic device D5, the path 22 connects the third stacked electronic device D5 to the fourth connection terminal 610, and the third additional capacitive structure 803 is arranged on the path 21.

The first connection terminal 605 of the first module 701 is connected to the first common terminal 603 through the path 12, the third connection terminal 609 of the third module 703 is connected to the first common terminal 603 through the path 13, and the first common terminal 603 is connected to the first input-output terminal 601 through the path 11. The second connection terminal 607 of the second module 702 is connected to the second common terminal 604 through the path 14. The second common terminal 604 is connected to the fourth connection terminal 610 of the third module through the path 15 , and the second common terminal 604 is connected to the second input-output terminal 602 through the path 16 .

Next, the integrated filter 3 will be described with reference to FIG. 8 to FIG. 22 .

FIG9 is a perspective view of the first module 701 of the integrated filter 3 of Embodiment III. Referring to FIG9 , the first module 701 of the integrated filter 3 is formed in a multilayer medium layer 103. The multilayer medium layer 103 is formed by stacking a plurality of dielectric layers along a stacking direction, and the dielectric layers can be composed of one or more dielectric materials such as gallium arsenide, silicon carbide, silicon nitride, aluminum nitride, aluminum oxide, glass, silicon oxide, etc. The first connection terminal 605 in the first module 701 and the capacitive structure of the first stacked electronic device D3 share the same metallized electrode E01, and the capacitive structure of the first stacked electronic device D3 also includes a metallized electrode E02, which is formed on a different dielectric layer and faces each other with the electrode E01, and is coupled to form the capacitive structure of the first stacked electronic device 3. The electrode E02 is located below the electrode E01 along the stacking direction. The first additional capacitive structure 801 is formed by coupling the electrode E03 and the metallized electrode E04, and the metallized electrodes E03 and E04 are formed on different dielectric layers and face each other. Electrode E04 is located below electrode E03 along the stacking direction. Electrode E01, electrode E02, electrode E03, and electrode E04 can be composed of one or more metallized materials such as Ag, Au, and Cu. Two via conductors 403 penetrate the dielectric layer along the stacking direction. The via conductors 403 can be composed of through holes composed of one or more metallized materials such as Ag, Au, and Cu, or can be composed of solid cylinders composed of one or more metallized materials such as Ag, Au, and Cu. One end of one via conductor 403 is connected to electrode E01, and the other end is connected to the first pattern conductor 204. One end of the other via conductor 402 is connected to the first pattern conductor 204, and the other end is connected to the metallized electrode E02 and electrode E03. The first pattern conductor 204 is located above the electrode E01, the electrode E02, the electrode E03, and the electrode E04 along the stacking direction, and can be composed of one or more metalized materials such as Ag, Au, and Cu, extending from a point in the form of a zigzag line to form a spiral shape, and the spiral contains a bent zigzag line. The two ends of the first pattern conductor 204 are respectively connected to the two via conductors 403. The first potential end 606 and the first additional capacitive structure 801 share the same metalized electrode E04. The first potential end 606 can be connected to the reference ground on the filter mounting surface through a mounting interface in the form of a conductive bump, a BGA solder ball, a bump, a Cu-Pillar, etc.

Fig. 10 is a transparent top view of the first module 701 of the integrated filter 3 of Embodiment III. Referring to Fig. 10, the electrodes E01 and E02 constituting the capacitive structure of the first stacked electronic device D3 are located below the first pattern conductor 204 along the stacking direction, and the electrodes E03 and E04 constituting the first additional capacitive structure 801 are located below the first pattern conductor 204 along the stacking direction. The projection of the first pattern conductor 204 on the plane perpendicular to the stacking direction of the first stacked electronic device D3 partially overlaps with the projection of the electrodes E01, E02, E03, and E04 on the plane perpendicular to the stacking direction. The first module 701 utilizes the capacitive structure of the first stacked electronic device D3 and the first additional capacitive structure 801 as a barrier between the first pattern conductor 204 and the mounting surface, and can confine most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D3 within the dielectric layer between the first pattern conductor 204 and the capacitive structure of the stacked electronic device D3 and the first additional capacitive structure 801, thereby increasing the stability of the electromagnetic field between the first pattern conductor 204 and the mounting surface, and reducing the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the performance of the integrated filter, thereby making the filter performance have a strong tolerance capability for mass manufacturing and application installation conditions.

FIG11 is a schematic diagram of a two-port network of the first to sixth additional capacitive structures. Referring to FIG11 , the first additional capacitive structure, the second additional capacitive structure, the third additional capacitive structure, the fourth additional capacitive structure, the fifth additional capacitive structure, and the sixth additional capacitive structure are all two-port elements, including two ports Port1 and Port2, _V1 is the total voltage between Port1 and reference point 1, _I1 is the total current of Port1, _V2 is the total voltage between Port2 and reference point 2, and _I2 is the total current of Port2. The relationship between the voltage and current between Port1 and Port2 of the first to sixth additional capacitive structures is represented by the admittance matrix [Y], respectively, and the admittance matrix [Y] of the first to sixth additional capacitive structures is:

Within the operating frequency band of the filter, the imaginary part of _Y11 in the admittance matrix [Y] of the first additional capacitive structure, the second additional capacitive structure, the third additional capacitive structure, the fourth additional capacitive structure, the fifth additional capacitive structure, and the sixth additional capacitive structure is greater than zero.

FIG12 is a diagram showing the admittance characteristics of the first additional capacitive structure 801 of the integrated filter 3. Referring to FIG12 , curve FC1 The imaginary part of _Y11 in the admittance matrix [Y] of the first additional capacitive structure 801 varies with frequency, wherein _fLE represents a frequency lower than the filter operating band, _fHE represents a frequency higher than the filter operating band, and Bwpass represents the filter operating band. The frequency band in which the imaginary part of _Y11 in the admittance matrix [Y] of the first additional capacitive structure 801 is greater than zero can be set within the filter operating band Bwpass.

FIG13 is a perspective view of the second module 702 of the integrated filter 3 of Embodiment III. Referring to FIG13 , the second module 702 of the integrated filter 3 is formed in the multilayer medium layer 103. The second connection terminal 607 in the second module 702 shares the same metallized electrode E05 with the second additional capacitive structure 802. The second additional capacitive structure 802 also includes a metallized electrode E06, which is formed on a different dielectric layer from the electrode E05 and faces each other, and is coupled to form the second additional capacitive structure 802; the metallized electrode E07 and the electrode E08 are formed on different dielectric layers and face each other, and are coupled to form the capacitive structure of the first stacked electronic device D4. The electrode E07 is located below the electrode E08 along the stacking direction, and the electrode E07 is connected to the electrode E06; the electrode E05, the electrode E06, the electrode E07, and the electrode E08 can be composed of one or more metallized materials such as Ag, Au, and Cu. Two via conductors 404 penetrate the dielectric layer along the stacking direction. The via conductors 404 can be formed by through holes made of one or more metallized materials such as Ag, Au, Cu, etc., or can be formed by solid cylinders made of one or more metallized materials such as Ag, Au, Cu, etc. One end of one via conductor 404 is connected to electrode E07 through a metal conductor, and the other end is connected to one end of the first pattern conductor 206. One end of another via conductor 404 is connected to the first pattern conductor 206, and the other end is connected to electrode E08. The first pattern conductor 206 is located above the electrodes E05, E06, E07, and E08, and is made of one or more metallized materials such as Ag, Au, Cu, etc. It extends from a point in the form of a zigzag line to form a spiral shape, and the spiral contains a bent zigzag line. The two ends of the first pattern conductor 206 are respectively connected to the two via conductors 404. The second potential end 608 is made of a metallized material and is connected to the electrode E08. The second potential terminal 608 can be connected to the reference ground on the filter mounting surface through a mounting interface in the form of a conductive bump, a BGA solder ball, a bump, a Cu-Pillar, etc.

Fig. 14 is a transparent top view of the second module 702 of the integrated filter 3 of Embodiment III. Referring to Fig. 14, the electrodes E07 and E08 constituting the capacitive structure of the second stacked electronic device D4 are located below the first pattern conductor 206 along the stacking direction, the electrodes E05 and E06 constituting the second additional capacitive structure 802 are located below the first pattern conductor 206 along the stacking direction, and the projection of the first pattern conductor 206 on the plane perpendicular to the stacking direction of the second stacked electronic device D4 at least partially overlaps with the projection of the electrodes E05, E06, E07, and E08 on the plane perpendicular to the stacking direction of the second stacked electronic device D4. The second module 702 utilizes the capacitive structure of the second stacked electronic device D4 and the second additional capacitive structure 802 as a barrier between the first pattern conductor 206 and the mounting surface, and can confine most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D4 within the dielectric layer between the first pattern conductor 206 and the capacitive structure of the stacked electronic device D4 and the second additional capacitive structure 802, thereby increasing the stability of the electromagnetic field between the first pattern conductor 206 and the mounting surface, and reducing the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the performance of the integrated filter, so that the filter performance has a strong tolerance capability for mass manufacturing and application installation conditions.

FIG15 is a perspective view of the third module 703 of the integrated filter 3 of embodiment III. Referring to FIG15 , the third module 703 of the integrated filter 3 is formed in the multilayer medium layer 103. The third connection terminal 609 in the third module 703 and the third additional capacitive structure 803 share the same metallized electrode E09. The third additional capacitive structure 803 also includes a metallized electrode E10, which is formed on a different dielectric layer and faces the electrode E09, and is coupled to form the third additional capacitive structure 803; the electrode E11 is formed in a bent shape; the electrode E11 and the electrode E10 are formed on different dielectric layers and face each other, and the electrode E12 and the electrode E11 are formed on different dielectric layers and face each other. The metallized electrode E10 and the metallized electrodes E11 and E12 are coupled together to form the capacitive structure in the third stacked electronic device D5. The metallized electrode E11 is located below the electrodes E10 and E12 along the stacking direction. Electrode E09, electrode E10, electrode E11, and electrode E12 can be composed of one or more metallized materials such as Ag, Au, and Cu. Two via conductors 405 penetrate the dielectric layer along the stacking direction. One end of one via conductor 405 is connected to the metallized electrode E12, and the other end is connected to the first pattern conductor 208; one end of the other via conductor 405 is connected to the first pattern conductor 208, and the other end is connected to the metallized electrode E10. The via conductor 405 can be composed of a through hole composed of one or more metallized materials such as Ag, Au, and Cu, or a solid column composed of one or more metallized materials such as Ag, Au, and Cu. The first pattern conductor 208 is located at Located above the electrodes E09, E10, E11, and E12 along the stacking direction, it is made of one or more metalized materials such as Ag, Au, and Cu, and extends from a point in the form of a zigzag line to form a planar spiral shape, and the spiral contains a bent zigzag line. Two via conductors 405 are connected to the two ends of the first pattern conductor 208. The capacitive structure in the third stacked electronic device D5 and the third additional capacitive structure 803 share the electrode E10. The fourth connection terminal 610 and the capacitive structure in the third stacked electronic device D5 share the metalized electrode E12.

FIG. 16 is a transmissive top view of the third module 703 of the integrated filter 3 according to Embodiment III. 16 , electrodes E10, E11, and E12 constituting the capacitive structure of the third stacked electronic device D5 are located below the first pattern conductor 208 along the stacking direction, and electrodes E09 and E10 constituting the third additional capacitive structure 803 are located below the first pattern conductor 208 along the stacking direction; the projections of the structures of electrodes E10 and E11 on the plane perpendicular to the stacking direction partially overlap, the projections of the structures of electrodes E11 and E12 on the plane perpendicular to the stacking direction partially overlap, and the overlapping portions of the projections of electrodes E10 and E11 on the plane perpendicular to the stacking direction do not intersect or overlap with the overlapping portions of the projections of electrodes E11 and E12 on the plane perpendicular to the stacking direction; the projection of the first pattern conductor 208 on the plane perpendicular to the stacking direction at least partially overlaps with the projections of electrodes E09, E10, E11, and E12 on the plane perpendicular to the stacking direction. The third module 703 utilizes the capacitive structure of the third stacked electronic device D5 and the third additional capacitive structure 803 as a barrier between the first pattern conductor 208 and the mounting surface, and can confine most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D5 within the dielectric layer between the capacitive structure of the first pattern conductor 208 and the stacked electronic device D5 and the third additional capacitive structure 803, thereby increasing the stability of the electromagnetic field between the first pattern conductor 208 and the mounting surface, and reducing the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the performance of the integrated filter, so that the filter performance has a strong tolerance capability for mass manufacturing and application installation conditions.

FIG. 17 and FIG. 18 are perspective views of the integrated filter 3 of Embodiment III. Referring to FIG. 17 and FIG. 18, the first module 701, the second module 702 and the third module 703 are all formed in the multilayer medium layer 103. The first input/output terminal 601 of the integrated filter 3 is formed on the metallized electrode E13. The electrode E13 is connected to the electrode E01 of the first module 701 through a metal conductor, the first common terminal 603 and the first connection terminal 605 of the first module share the electrode E01, and the electrode E01 is connected to the electrode E09 of the third module 703 through a metal conductor. The second input/output terminal 602 of the integrated filter 3 is formed on the metallized electrode E14. The electrode E14 is connected to the electrode E05 of the second module 702 through a metal conductor, the second common terminal 604 and the second connection terminal 607 of the second module share the electrode E05, and the electrode E05 is also connected to the electrode E12 of the third module 703. At this time, the first connection terminal 605 of the first module 701 is connected to the first common terminal 603, the third connection terminal 609 of the third module 703 is connected to the first common terminal 603, and the first common terminal 603 is connected to the first input-output terminal 601; the second connection terminal 607 of the second module 702 is connected to the second common terminal 604, the second common terminal 604 is connected to the fourth connection terminal 610 of the third module, and the second common terminal 604 is connected to the second input-output terminal 602. Electrodes E13 and E14 are formed on the surface of the dielectric layer of the multilayer medium layer 103, and can be connected to the mounting surface of the integrated filter through mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-pillars, etc. Electrodes E14 and E13 can be composed of one or more metallized materials such as Ag, Au, Cu, etc. The internal structures and connection relationships of the first module 704, the second module 705 and the third module 703 are the same as described above. The arrangement direction of the first module 704 , the second module 705 and the third module 703 is perpendicular to the stacking direction of the dielectric layers of the multi-layer medium layer 103 .

Since the first stacked electronic device D3, the second stacked electronic device D4, and the third stacked electronic device D5 are all structures of the stacked electronic devices in the aforementioned embodiments or their variations, based on the characteristics of the stacked electronic devices, the integrated filter 3 has the advantages of high frequency selectivity and miniaturization and can effectively reduce the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, Bumps, Cu-Pillars, etc. on the filter performance, so that the filter has a stronger tolerance capability in batch manufacturing and application installation, which is conducive to improving the yield of large-scale production and delivery of filters.

The grounded first module 701 and the grounded second module 702 can realize the introduction of the integrated filter transmission zero point, and the integrated filter selection characteristics are improved by using the first module 701 and the second module 702. The third module 703 can realize the introduction of the integrated filter transmission zero point, and the integrated filter selection characteristics are improved by using the third module 703. The first additional capacitive structure 801 and the second additional capacitive structure 802 are loaded to help adjust the impedance of the first module 701 and the second module 702. The loading of the third additional capacitive structure 803 can adjust the impedance matching between the third stacked electronic device D5 and the first module 701 and the second module 702. The frequency selectivity of the filter is effectively improved by the grounded first module 701, the grounded second module 702, and the third module 703, so that the filter has the advantages of simple structure, small size, and high out-of-band noise suppression performance.

Referring to Figures 19 to 21, the layout of the first to third stacked electronic devices in the integrated filter 3 is that the projection of the first pattern conductor 208 of the third stacked electronic device D5 on the integrated filter mounting surface 502 is sandwiched between the projection of the first pattern conductor 204 of the first stacked electronic device D3 on the integrated filter mounting surface 502 and the projection of the first pattern conductor 206 of the second stacked electronic device D4 on the integrated filter mounting surface 502. The integrated filter mounting surface 502 is a surface of a mounting carrier for fixing the integrated filter or for fixing any electronic device composed of the integrated filter, and the mounting carrier is a substrate including at least one layer of metallized material or at least one layer of dielectric layer, such as a PCB substrate, ABF substrate, FCBGA substrate, silicon-based adapter board, glass-based adapter board, etc. composed of at least one layer of metallized material and at least one layer of dielectric layer. In this embodiment, the filter is fixed on the FCBGA substrate through metallized micro-bumps (BGA, Bump, Cu-pillar, etc.), and is interconnected with other components such as power amplifiers and low-noise amplifiers to realize the function of the RF front-end module. The projection of the first module 701 on the integrated filter mounting surface 502, the projection of the second module 702 on the integrated filter mounting surface 502, and the projection of the third module 703 on the integrated filter mounting surface 502 partially overlap. This compact structural layout can further reduce the size of the filter and achieve miniaturization of the filter.

The first stacked electronic device D3, the second stacked electronic device D4 and the third stacked electronic device D5 all include a first pattern conductor, a capacitive structure and two via conductors. The first pattern conductor, the capacitive structure, the two via conductors and the coupling paths therebetween form a three-dimensional integrated closed loop in three-dimensional space. The projection of the three-dimensional integrated closed loop formed by the first pattern conductor 204, the capacitive structure, the via conductor 403 and the coupling path therebetween in the three-dimensional space of the first stacked electronic device D3 on the plane perpendicular to the long side of the integrated filter multilayer medium layer 103 at least partially overlaps with the projection of the three-dimensional integrated closed loop formed by the first pattern conductor 206, the capacitive structure, the via conductor 404 and the coupling path therebetween in the three-dimensional space of the second stacked electronic device D4 on the plane perpendicular to the long side of the integrated filter multilayer medium layer 103 and the projection of the three-dimensional integrated closed loop formed by the first pattern conductor 208, the capacitive structure, the via conductor 405 and the coupling path therebetween in the three-dimensional space on the plane perpendicular to the long side of the integrated filter multilayer medium layer 103. This compact layout can reduce the plane size of the filter and improve the miniaturization level of the filter.

Fig. 22 is a reflection and transmission characteristic diagram of the integrated filter 3 of the third embodiment. Referring to Fig. 22, the integrated filter 3 has good echo reflection characteristics in the band, the first module 701 generates a transmission zero TZ1 on the left side of the filter passband, and the second module 702 generates a transmission zero TZ2 on the left side of the filter passband, and the above transmission zero TZ1 and transmission zero TZ2 improve the frequency selectivity on the left side of the passband of the integrated filter 3. At the same time, the third module 703 generates a transmission zero TZ3 located on the right side of the passband, thereby improving the frequency selectivity on the right side of the passband of the integrated filter 3.

In addition, the first additional capacitive structure 801 may also be disposed on the path 17 ; the second additional capacitive structure 802 may also be disposed on the path 20 ; and the third additional capacitive structure 803 may also be disposed on the path 22 .

In addition, the first module 701 may also include more than one first additional capacitive structure; the second module 702 may also include more than one second additional capacitive structure; and the third module 703 may also include more than one third additional capacitive structure.

Alternatively, the electrodes E13 and E14 may be formed between dielectric layers within the multilayer medium layer 103 .

In addition, the first additional capacitive structure 801, the second additional capacitive structure 802, and the third additional capacitive structure 803 may also be composed of two or more metallized electrodes formed on different dielectric layers and facing each other.

In addition, the metallized electrodes constituting the first additional capacitive structure 801 , the second additional capacitive structure 802 , and the third additional capacitive structure 803 may also be formed on the surface of the dielectric layer of the multi-layer medium layer 103 .

The integrated filter 4 of Embodiment IV of the present application is described below. The integrated filter 4 involved in Embodiment IV is different from Embodiment III in that the integrated filter 4 further includes a first additional inductive structure and a second additional inductive structure, which can further improve the out-of-band suppression capability and frequency selectivity of the filter. FIG23 is a circuit diagram of the circuit structure of the integrated filter 4 of Embodiment IV. Referring to FIG23, the integrated filter 4 is configured to further include the first additional inductive structure and the second additional inductive structure. The additional inductive structure 901 and the second additional inductive structure 902 are respectively configured in the first module and the second module of the integrated filter.

The integrated filter 4 comprises a first input-output terminal 601, a second input-output terminal 602, a first module 704, a second module 705, a third module 703, a first common terminal 603 and a second common terminal 604, a path 11, a path 12, a path 13, a path 14, a path 15 and a path 16; the first input-output terminal 601, the second input-output terminal 602, the first common terminal 603 and the second common terminal 604 are made of one or more metallized materials such as Ag, Au, and Cu;

The first module 704 includes a first connection terminal 605, a first stacked electronic device D3, a first additional capacitive structure 801, a first potential terminal 606, a first additional inductive structure 901, a path 17, and a path 18. The first connection terminal 605 is made of a metalized material, the first stacked electronic device D3 is the structure of the stacked electronic device in the aforementioned embodiment or a modified example thereof, the first additional capacitive structure 801 is formed by coupling a plurality of metalized electrodes facing each other, the first additional inductive structure 901 is made of a metalized material, and the first potential terminal 606 is made of a metalized material for connecting to a reference ground. Path 17 connects the first connection terminal 605 to the first stacked electronic device D3, and path 18 connects the first stacked electronic device D3 to the first potential terminal 606. The first additional capacitive structure 801 and the first additional inductive structure 901 are arranged in the path 18 between the first stacked electronic device D3 and the first potential terminal 606, and are connected in sequence in the order of the first additional capacitive structure 801 and the first additional inductive structure 901 starting from the first stacked electronic device D3.

The second module 705 includes a second connection terminal 607, a second potential terminal 608, a second stacked electronic device D4, a second additional capacitive structure 802, a second additional inductive structure 902, a path 19, and a path 20. The second connection terminal 607 is made of a metalized material, the second stacked electronic device D4 is the structure of the stacked electronic device in the aforementioned embodiment or a modified example thereof, the second additional capacitive structure 802 is formed by coupling a plurality of metalized electrodes facing each other, the second additional inductive structure 902 is made of a metalized material, and the second potential terminal is made of a metalized material for connecting to a reference ground. Path 19 connects the second connection terminal 607 to the second stacked electronic device D4, and path 20 connects the second stacked electronic device D4 to the second potential terminal 608. The second additional capacitive structure 802 and the second additional inductive structure 902 are arranged on path 19 between the second stacked electronic device D4 and the second connection terminal 607, and are connected in sequence from the second connection terminal 607 side in the order of the second additional capacitive structure 802 and the second additional inductive structure 902.

The first connection terminal 605 of the first module 704 is connected to the first common terminal 603 through a path 12, the third connection terminal 609 of the third module 703 is connected to the first common terminal 603 through a path 13, and the first common terminal 603 is connected to the first input-output terminal 601 through a path 11. The second connection terminal 607 of the second module 705 is connected to the second common terminal 604 through a path 14, the second common terminal 604 is connected to the fourth connection terminal 610 of the third module through a path 15, and the second common terminal 604 is connected to the second input-output terminal 602 through a path 16.

Next, the structure of the integrated filter 4 will be described with reference to FIG. 23 to FIG. 38 .

FIG. 24 and FIG. 25 are perspective views of the first module 704 of the integrated filter 4 of Embodiment IV. Referring to FIG. 24 and FIG. 25, the first module 704 of the integrated filter 4 is formed in a multilayer medium layer 104. The multilayer medium layer 104 is formed by stacking a plurality of dielectric layers along a stacking direction, and the dielectric layers can be composed of one or more dielectric materials such as gallium arsenide, silicon carbide, silicon nitride, aluminum nitride, aluminum oxide, glass, silicon oxide, etc. The first connection terminal 605 in the first module 704 and the capacitive structure of the first stacked electronic device D3 share the same metallized electrode E15, and the capacitive structure of the first stacked electronic device D3 also includes a metallized electrode E16, which is formed on a different dielectric layer from the electrode E15 and faces each other, and is coupled to form the capacitive structure of the first stacked electronic device D3. The electrode E16 is located below the electrode E15 along the stacking direction. Two via conductors 406 penetrate the dielectric layer along the stacking direction. The via conductors 406 can be formed by through holes made of metallized materials such as Ag, Au, Cu, etc., or can be formed by solid columns made of one or more metallized materials such as Ag, Au, Cu, etc. One end of one via conductor 406 is connected to the electrode E15, and the other end is connected to the first pattern conductor 209. One end of a via conductor 406 is connected to the first pattern conductor 209, and the other end is connected to the metallized electrode E17. The first pattern conductor 209 is located above the electrode E15, the electrode E16, the electrode E17, and the electrode E18, and can be composed of one or more metallized materials such as Ag, Au, and Cu. It extends from a point in the form of a zigzag line to form a spiral shape, and the spiral contains a bent zigzag line. The two ends of the first pattern conductor 209 are respectively connected to two via conductors 406. The first additional capacitive structure 801 is formed by coupling the electrode E17 and the metallized electrode E18. The electrode E18 and the electrode E17 are formed on different dielectric layers and face each other. The electrode E18 is located below the electrode E17 along the stacking direction. The electrode E18 can be coupled to the first additional inductive structure 901 through a copper column. The electrode E15, the electrode E16, the electrode E17, and the electrode E18 can be composed of one or more metallized materials such as Ag, Au, and Cu. The first additional inductive structure 901 can be made of one or more metallized materials such as Ag, Au, Cu, etc., and is formed on the filter installation surface, extending from one point in the form of a folded line, forming a spiral shape, and the spiral shape includes a bent folded line. The first potential terminal 606 is formed on the first additional inductive structure 901. The first potential terminal 606 is connected to the reference ground on the filter installation surface.

Fig. 26 is a transparent top view of the first module 704 of the integrated filter 4 of Embodiment IV. Referring to Fig. 26, the electrodes E15 and E16 constituting the capacitive structure of the first stacked electronic device D3 and the electrodes E17 and E18 constituting the first additional capacitive structure 801 are located below the first pattern conductor 209 along the stacking direction, and the projection of the first pattern conductor 209 on the plane perpendicular to the stacking direction of the first stacked electronic device D3 at least partially overlaps with the projection of the electrodes E15, E16, E17, and E18 on the plane perpendicular to the stacking direction of the first stacked electronic device D3. The first module 704 utilizes the capacitive structure of the first stacked electronic device D3 and an additional capacitive structure 801 as a barrier between the first pattern conductor 209 and the mounting surface, and can confine most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D3 within the dielectric layer between the first pattern conductor 209 and the capacitive structure of the stacked electronic device D3 and the first additional capacitive structure 801, thereby increasing the stability of the electromagnetic field between the first pattern conductor 209 and the mounting surface, and reducing the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the performance of the integrated filter, so that the filter performance has a strong tolerance capability for mass manufacturing and application installation conditions.

FIG27 is a schematic diagram of a two-port network of the first to second additional inductive structures. Referring to FIG27 , the first additional inductive structure and the second additional inductive structure are two-port elements, including two ports Port3 and Port4, _V1 is the total voltage between Port3 and reference point 3, _I1 is the total current of Port3, _V2 is the total voltage between Port4 and reference point 4, and _I2 is the total current of Port4. The admittance matrix [Y] is used to represent the relationship between the voltage and current between Port3 and Port4 of the first to second additional inductive structures, respectively. Then, the admittance matrix [Y] of the first to second additional inductive structures is:

In the operating frequency band of the filter, the imaginary part of _Y11 in the admittance matrix [Y] of the first additional inductive structure and the second additional inductive structure is less than zero.

FIG28 is an admittance characteristic diagram of the first additional inductive structure 901 of the integrated filter 4. Referring to FIG28, curve FL1 shows the variation of the imaginary part of _Y11 in the admittance matrix [Y] of the first additional inductive structure 901 with frequency. Wherein _fLE represents a frequency lower than the filter operating frequency band, _fHE represents a frequency higher than the filter operating frequency band, and Bwpass represents the filter operating frequency band. The frequency band in which the imaginary part of _Y11 in the admittance matrix [Y] of the first additional inductive structure 901 is less than zero can be set within the filter operating frequency band Bwpass.

FIG29 is a perspective view of the second module 705 of the integrated filter 4 of Embodiment IV. Referring to FIG29 , the second module 705 of the integrated filter 4 is formed in the multilayer medium layer 104. The second connection terminal 607 in the second module 705 and the second additional capacitive structure 802 share the same metallized electrode E19. The second additional capacitive structure 802 also includes a metallized electrode E20, which is formed on different dielectric layers and faces the electrode E19, and is coupled to form a second additional capacitive structure; the electrode E20 is located below the electrode E19 along the stacking direction. The metallized electrode E21 and the metallized electrode E22 are formed on different dielectric layers and face each other, and are coupled to form the capacitive structure of the second stacked electronic device D4. The electrode E21 is located below the electrode E22 along the stacking direction. The electrode E20 is connected to one end of the second additional inductive structure 902. The second additional inductive structure 902 can be made of one or more metalized materials such as Ag, Au, Cu, etc., and is extended from a point in the form of a folded line to form a spiral shape. The spiral shape includes a bent folded line. The other end of the second additional inductive structure 902 is connected to the metalized electrode E21. The electrodes E19, E20, E21 and E22 can be made of one or more metalized materials such as Ag, Au, Cu, etc. The two via conductors 407 penetrate the dielectric layer in the stacking direction. The via conductors 407 can be composed of a through hole composed of one or more metallized materials such as Ag, Au, Cu, etc., or a solid cylinder composed of one or more metallized materials such as Ag, Au, Cu, etc. One end of one via conductor 407 is connected to the electrode E21 through a metal conductor, and the other end is connected to the first pattern conductor 210. One end of the other via conductor 407 is connected to the first pattern conductor 210, and the other end is connected to the electrode E22. The first pattern conductor 210 is located above the electrode E19, the electrode E20, the electrode E21, the electrode E22 and the second additional inductive structure 902 in the stacking direction, and is composed of one or more metallized materials such as Ag, Au, Cu, etc. It extends from a point in the form of a zigzag line, forming a planar spiral shape, and the spiral contains a bent zigzag line. The two ends of the first pattern conductor 210 are respectively connected to the two via conductors 407. The second potential terminal 608 is made of metalized material and connected to the electrode E22 through a metal conductor. The second potential terminal 608 can be connected to the reference ground on the filter mounting surface through a mounting interface in the form of a conductive bump, BGA solder ball, Bump, Cu-Pillar, etc.

Fig. 30 is a transparent top view of the second module 705 of the integrated filter 4 of Embodiment IV. Referring to Fig. 30, the electrodes E21 and E22 constituting the capacitive structure of the second stacked electronic device D4 are located below the first pattern conductor 210 along the stacking direction, the electrodes E20 and E19 constituting the second additional capacitive structure 802 are located below the first pattern conductor 210 along the stacking direction, and the projection of the first pattern conductor 210 on a plane perpendicular to the stacking direction of the second stacked electronic device D4 at least partially overlaps with the projection of the electrodes E19, E20, E21, and E22 on a plane perpendicular to the stacking direction of the second stacked electronic device D4. The second module 705 utilizes the capacitive structure of the second stacked electronic device D4 and the second additional capacitive structure 802 as a barrier between the first pattern conductor 210 and the mounting surface, and can confine most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D4 within the dielectric layer between the first pattern conductor 210 and the capacitive structure of the stacked electronic device D4 and the second additional capacitive structure 802, thereby increasing the stability of the electromagnetic field between the first pattern conductor 210 and the mounting surface, and reducing the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the performance of the integrated filter, so that the filter performance has a strong tolerance capability for mass manufacturing and application installation conditions.

FIG31 is a perspective view of the third module 703 of the integrated filter 4 of Embodiment IV. Referring to FIG31 , the third module 703 of the integrated filter 4 is formed in the multilayer medium layer 104. The third connection terminal 609 in the third module 703 and the third additional capacitive structure 803 share the same metallized electrode E23. The third additional capacitive structure 803 also includes a metallized electrode E24, which is formed on a different dielectric layer and faces the electrode E23, and is coupled to form the third additional capacitive structure 803. The metallized electrode E23 is located below the electrode E24 along the stacking direction. The metallized electrode E25 is formed in a bent shape, and is formed on a different dielectric layer and faces the electrode E24. The metallized electrode E26 and the electrode E25 are formed on different dielectric layers and face each other. The metallized electrode E24, the metallized electrode E25, and the electrode E26 are coupled together to form the capacitive structure in the third stacked electronic device D5. The metallized electrode E25 is located below the electrode E24 and the electrode E26 along the stacking direction. The electrodes E23, E24, E25, and E26 can be made of one or more metallized materials such as Ag, Au, and Cu. Two via conductors 408 penetrate the dielectric layer along the stacking direction. One end of one via conductor 408 is connected to the metallized electrode E24, and the other end is connected to the first pattern conductor 211; one end of the other via conductor 408 is connected to the first pattern conductor 211, and the other end is connected to the metallized electrode E26. The via conductor 408 can be made of a through hole made of one or more metallized materials such as Ag, Au, and Cu, or a solid cylinder made of one or more metallized materials such as Ag, Au, and Cu. The first pattern conductor 211 is located above the electrodes E23, E24, E25, and E26 along the stacking direction, and can be made of one or more metallized materials such as Ag, Au, and Cu. It extends from a point in the form of a zigzag line to form a spiral shape, and the spiral shape contains a bent zigzag line. Two via conductors 408 are connected to the two ends of the first pattern conductor 211, respectively. The capacitive structure in the third stacked electronic device D5 and the third additional capacitive structure 803 share the electrode E24; the fourth connection terminal 610 and the capacitive structure in the third stacked electronic device D5 share the metallized electrode E26;

FIG32 is a transparent top view of the third module 703 of the integrated filter 4 of Embodiment IV. Referring to FIG32, the electrodes E24, E25, and E26 constituting the capacitive structure of the third stacked electronic device D5 are located below the first pattern conductor 211 in the stacking direction, and the electrodes E23 and E24 constituting the third additional capacitive structure 803 are located below the first pattern conductor 211 in the stacking direction; viewed from the stacking direction, the projections of the structures of the electrodes E24 and E25 on the plane perpendicular to the stacking direction partially overlap, and the projections of the structures of the electrodes E25 and E26 on the plane perpendicular to the stacking direction partially overlap. There is a partial overlap, and the overlapping portion of the projection of the structure of electrodes E24 and E25 on the plane perpendicular to the stacking direction does not intersect or overlap with the overlapping portion of the projection of the structure of electrodes E25 and E26 on the plane perpendicular to the stacking direction; the projection of the first pattern conductor 211 on the plane perpendicular to the stacking direction of the third stacked electronic device D5 at least partially overlaps with the projection of electrodes E23, electrode E24, electrode E25, and electrode E26 on the plane perpendicular to the stacking direction of the third stacked electronic device D5. The third module 703 utilizes the capacitive structure of the third stacked electronic device D5 and the third additional capacitive structure 803 as a barrier between the first pattern conductor 211 and the mounting surface, and can confine most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D5 within the dielectric layer between the first pattern conductor 211 and the capacitive structure of the stacked electronic device D5 and the third additional capacitive structure 803, thereby increasing the stability of the electromagnetic field between the first pattern conductor 211 and the mounting surface, and reducing the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the performance of the integrated filter, so that the filter performance has a strong tolerance capability for mass manufacturing and application installation conditions.

FIG. 33 and FIG. 34 are perspective views of the integrated filter 4 of Embodiment IV. Referring to FIG. 33 and FIG. 34, the first module 704, the second module 705 and the third module 703 are all formed in the multilayer medium layer 104. The first input/output terminal 601 of the integrated filter 4 is formed on the metallized electrode E27. The electrode E27 is connected to the electrode E15 of the first module 704 through a metal conductor, and the electrode E27 is connected to the electrode E23. The first common terminal 603 and the third connection terminal 609 of the third module 703 share the electrode E23, and the electrode E15 is connected to the electrode E23 of the third module 703. The second input/output terminal 602 of the integrated filter 4 is formed on the metallized electrode E28. The electrode E28 is connected to the electrode E19 of the second module 705 through a metal conductor, the second common terminal 604 and the second connection terminal 607 of the second module share the electrode E19, and the electrode E19 is also connected to the electrode E26 of the third module 703. At this time, the first connection terminal 605 of the first module 704 is connected to the first common terminal 603, the third connection terminal 609 of the third module 703 is connected to the first common terminal 603, and the first common terminal 603 is connected to the first input-output terminal 601; the second connection terminal 607 of the second module 705 is connected to the second common terminal 604, the second common terminal 604 is connected to the fourth connection terminal 610 of the third module, and the second common terminal 604 is connected to the second input-output terminal 602. Electrodes E27 and E28 are formed on the surface of the dielectric layer of the multilayer medium layer 104, and can be connected to the mounting surface of the integrated filter through mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-pillars, etc. Electrodes E27 and E28 can be composed of one or more metallized materials such as Ag, Au, Cu, etc. The internal structures and connection relationships of the first module 704, the second module 705 and the third module 703 are the same as described above. The arrangement direction of the first module 704 , the second module 705 and the third module 703 is perpendicular to the stacking direction of the dielectric layers of the multi-layer medium layer 104 .

The grounded first module 704 of the integrated filter 4 is loaded by the first additional capacitive structure 801 and the first additional inductive structure 901, which is conducive to the introduction of multiple controllable transmission zeros; at the same time, the grounded second module 705 is loaded by the second additional capacitive structure 802 and the second additional inductive structure 902, which is also conducive to the introduction of multiple transmission zeros. The third module 703 is conducive to the introduction of the transmission zero of the integrated filter, so that the integrated filter selection characteristics are improved by using the third module 703, and the loading of the third additional capacitive structure 803 can adjust the impedance matching between the third stacked electronic device D5 and the first module 701 and the second module 702. Compared with the integrated filter 3, the first additional inductive structure 901 and the second additional inductive structure 902 newly added to the integrated filter 4 respectively introduce two additional controllable transmission zeros into the first module 704 and the second module 705, thereby realizing the multi-transmission zero filtering of the filter without the need for an additional resonator structure, thereby effectively improving the frequency selectivity of the filter, so that the filter has the advantages of simple structure, small size, and high out-of-band noise suppression performance.

Since the first stacked electronic device D3, the second stacked electronic device D4, and the third stacked electronic device D5 are all structures of the stacked electronic devices in the aforementioned embodiments or their variations, based on the characteristics of stacked electronic devices, the integrated filter 4 has the advantages of high frequency selectivity and miniaturization and can effectively reduce the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, Bumps, Cu-Pillars, etc. on the filter performance, so that the filter has a strong tolerance capability in mass manufacturing and application installation, which is conducive to improving the yield of large-scale production and delivery of filters.

FIG35 is a side view of the integrated filter 4 of Embodiment IV fixed to the mounting surface. Referring to FIG35, the first additional inductive structure 901 is arranged on the surface of the filter mounting surface and is located below the multilayer medium layer 104 along the stacking direction. The second additional inductive structure 902 is arranged on the dielectric layer surface of the multilayer medium layer 104 and is located between the first pattern conductor 210 and the integrated filter mounting surface along the stacking direction. The electrodes E15-E28 are located between the first pattern conductor 209 and the first Between the pattern conductor 210, the first pattern conductor 211 and the integrated filter mounting surface.

FIG36 is a top view of the integrated filter 4 of Embodiment IV when it is fixed to the mounting surface. FIG37 is a structural stereogram of the integrated filter 4 of Embodiment IV when it is fixed to the mounting surface. Referring to FIG36 and FIG37, the layout of the first to third stacked electronic devices in the integrated filter 4 is that the projection of the first pattern conductor 211 of the third stacked electronic device D5 on the integrated filter mounting surface 503 is sandwiched between the projection of the first pattern conductor 209 of the first stacked electronic device D3 on the integrated filter mounting surface 503 and the projection of the first pattern conductor 210 of the second stacked electronic device D4 on the integrated filter mounting surface 503. The mounting surface 503 is a surface of a mounting carrier for fixing the integrated filter 4 or for fixing any electronic device composed of the integrated filter 4, and the mounting carrier is a substrate including at least one layer of metallized material or at least one layer of dielectric layer, such as a PCB substrate, ABF substrate, FCBGA substrate, silicon-based adapter board, glass-based adapter board, etc., which are composed of at least one layer of metallized material and at least one layer of dielectric layer. In this embodiment, the filter is fixed on the FCBGA substrate by metallized micro-bumps (BGA, Bump, Cu-pillar, etc.), and is interconnected with other components such as power amplifiers and low-noise amplifiers to realize the function of the RF front-end module. The projection of the first module 704 on the integrated filter mounting surface 503, the projection of the second module 705 on the integrated filter mounting surface 503, and the projection of the third module 703 on the integrated filter mounting surface 503 partially overlap. This compact structural layout can further reduce the size of the filter and realize the miniaturization design of the filter.

FIG38 is a reflection and transmission characteristic diagram of the integrated filter 4 of the fourth embodiment. Referring to FIG38, the first module 704 of the integrated filter 4 generates transmission zeros TZ1 and TZ5, and the second module 705 generates transmission zeros TZ2 and TZ4. The transmission zeros TZ1 and TZ2 are on the left side of the passband, which improves the frequency selectivity of the left side of the passband. The transmission zeros TZ4 and TZ5 are on the right side of the passband, thereby improving the frequency selectivity of the right side of the passband. At the same time, the third module 703 generates a transmission zero TZ3 located on the right side of the passband, thereby improving the frequency selectivity of the right side of the passband.

Embodiment IV of the present application has been described above, but the present application is not necessarily limited to the above-mentioned embodiment IV, and various changes can be made without departing from the scope of the main purpose. For example, the first additional capacitive structure 801 can also be configured on the path between the first stacked electronic device D3 and the first connection terminal 605, or on the path between the first stacked electronic device D3 and the first potential terminal 606. For example, the first additional capacitive structure 801 can also be set on path 17. The second additional capacitive structure 802 is configured on the path between the second stacked electronic device D4 and the second connection terminal 607, or on the path between the second stacked electronic device D4 and the second potential terminal 608. For example, the second additional capacitive structure 802 can also be set on path 20; the third additional capacitive structure 803 is configured on the path between the third stacked electronic device D5 and the third connection terminal 609, or on the path between the second stacked electronic device D5 and the fourth connection terminal 610. For example, the third additional capacitive structure 803 can also be set on path 22;

In addition, the first additional inductive structure 901 can also be arranged on the path between the first connection terminal 605 and the first stacked electronic device D3; and/or, on the path between the first connection terminal 605 and the first additional capacitive structure 801; and/or, on the path between the first stacked electronic device D3 and the first additional capacitive structure 801; and/or, on the path between the first potential terminal 606 and the first additional capacitive structure 801; and/or, on the path between the first potential terminal 606 and the first stacked electronic device D3. For example, the first additional inductive structure 901 can also be arranged on the path 17;

The first additional inductive structure 901 can be formed as long as the projection of the plane perpendicular to the stacking direction of the first stacked electronic device is formed by at least one of a straight line, a fold line, an arc line, and a spiral line extending from a point; for example, the first additional inductive structure 901 can also be formed as a rectangle;

In addition, the second additional inductive structure 902 can also be arranged on the path between the second connection end 607 and the second stacked electronic device 4; and/or, on the path between the second connection end 607 and the second additional capacitive structure 802; and/or, on the path between the second stacked electronic device D4 and the second additional capacitive structure 802; and/or, on the path between the second potential end 608 and the second additional capacitive structure 802; and/or, on the path between the second potential end 608 and the second stacked electronic device D4. For example, the second additional inductive structure 902 can also be arranged on the path 20;

In addition, the second additional inductive structure 902 can be formed as long as the projection of the plane perpendicular to the stacking direction of the second stacked electronic device is formed by at least one of a straight line, a fold line, an arc line, and a spiral line extending from a point; for example, the first additional inductive structure The structure 902 may also be formed in a rectangular shape.

In addition, although in the embodiment, it is described that the capacitive structure of the third stacked electronic device D5 is composed of three electrodes E09, electrode E10, and electrode E11, the capacitive structure of the stacked electronic device in the integrated filter of the present application and the first to third additional capacitive structures can also be composed of more than three metallized electrodes that are in a facing relationship.

In addition, the first common terminal 603 and the first connection terminal 605 of the first module, the third connection terminal 609 of the third module, and the fourth additional capacitive structure may also share the same metallized electrode; the second common terminal and the second connection terminal of the second module, the fourth connection terminal of the third module, and the fourth additional capacitive structure may also share the same metallized electrode;

In addition, the first common terminal 603 may be formed on the first module 704 or on the third module 703 ; the first common terminal 604 may be formed on the second module 705 or on the third module 703 .

In addition, the first additional inductive structure 901 may also be formed on the surface of the dielectric layer of the multi-layer medium layer of the filter or between the dielectric layers. The second additional inductive structure 902 may also be formed on the surface of the integrated filter mounting carrier or inside the mounting carrier.

In addition, the metallized electrodes constituting the first additional capacitive structure 801, the second additional capacitive structure 802, and the third additional capacitive structure 803 may also be formed on the surface of the dielectric layer of the multi-layer medium layer of the filter.

The integrated filter 5 of implementation mode V of the present application is described below. The integrated filter 5 involved in implementation mode V is different from implementation mode IV in that it also includes a fourth additional capacitive structure, which can further improve the low-frequency out-of-band suppression capability of the filter;

39 is a circuit diagram of the circuit structure of an integrated filter 5 according to implementation V. Based on the integrated filter 4 , the integrated filter 5 further configures a fourth additional capacitive structure 804 on the coupling path between the second common terminal 604 and the second input-output terminal 602 .

The integrated filter 4 comprises a first input-output terminal 601, a second input-output terminal 602, a first module 704, a second module 705, a third module 703, a first common terminal 603 and a second common terminal 604, a fourth additional capacitive structure 804, a path 11, a path 12, a path 13, a path 14, a path 15 and a path 16; the first input-output terminal 601, the second input-output terminal 602, the first common terminal 603 and the second common terminal 604 are made of one or more metallized materials such as Ag, Au, and Cu;

The first module 704 includes a first connection terminal 605, a first stacked electronic device D3, a first additional capacitive structure 801, a first potential terminal 606, a first additional inductive structure 903, a path 17, and a path 18. The first connection terminal 605 is made of a metallized material, the first stacked electronic device D3 is the structure of the stacked electronic device in the aforementioned embodiment or a modified example thereof, the first additional capacitive structure 801 is formed by coupling a plurality of metallized electrodes facing each other, the first additional inductive structure 903 is made of a metallized material, and the first potential terminal 606 is made of a metallized material for connecting to a reference ground. Path 17 connects the first connection terminal 605 to the first stacked electronic device D3, path 18 connects the first stacked electronic device D3 to the first potential terminal 606, and the first additional capacitive structure 801 and the first additional inductive structure 903 are arranged on path 18 between the first stacked electronic device D3 and the first potential terminal 606. Starting from the side of the first stacked electronic device D3, the first additional capacitive structure 801 and the first additional inductive structure 903 are connected in sequence.

The second module 705 includes a second connection terminal 607, a second potential terminal 608, a second stacked electronic device D4, a second additional capacitive structure 802, a second additional inductive structure 904, a path 19, and a path 20. The second connection terminal 607 is made of a metalized material, the second stacked electronic device D4 is the structure of the stacked electronic device in the aforementioned embodiment or a modified example thereof, the second additional capacitive structure 802 is formed by coupling a plurality of metalized electrodes facing each other, the second additional inductive structure 904 is made of a metalized material, and the second potential terminal 608 is made of a metalized material for connecting to a reference ground. Path 19 connects the second connection terminal 607 to the second stacked electronic device D4, path 20 connects the second stacked electronic device D4 to the second potential terminal 608, and the second additional capacitive structure 802 and the second additional inductive structure 904 are arranged on path 19 between the second stacked electronic device D4 and the second connection terminal 607. Starting from the second connection terminal 607 side, the second additional capacitive structure 802 and the second additional inductive structure 904 are connected in sequence.

The third module 703 includes a third connection terminal 609, a fourth connection terminal 610, a third stacked electronic device D5, a third additional capacitive structure 803, a path 21, and a path 22. The third connection terminal 609 and the fourth connection terminal 610 are made of metalized materials. The third stacked electronic device D5 is the structure of the stacked electronic device in the above embodiment or a modified example thereof. The additional capacitive structure 803 is formed by coupling a plurality of metallized electrodes facing each other. Path 21 connects the third connection terminal 609 to the third stacked electronic device D5, and path 22 connects the third stacked electronic device D5 to the fourth connection terminal 610. The third additional capacitive structure 803 is disposed on path 21.

The first connection terminal 605 of the first module 704 is connected to the first common terminal 603 through a path 12, the third connection terminal 609 of the third module 703 is connected to the first common terminal 603 through a path 13, and the first common terminal 603 is connected to the first input-output terminal 601 through a path 11. The second connection terminal 607 of the second module 705 is connected to the second common terminal 604 through a path 14, the second common terminal 604 is connected to the fourth connection terminal 610 of the third module through a path 15, the second common terminal 604 is connected to one end of the fourth additional capacitive structure 804, the other end of the fourth additional capacitive structure 804 is connected to the second input-output terminal 602, and the fourth additional capacitive structure 804 is arranged on a path 16 between the second common terminal 604 and the second input-output terminal 602.

Next, the structure of the integrated filter 5 will be described with reference to FIG. 39 to FIG. 52 .

FIG. 40 and FIG. 41 are perspective views of the first module 704 of the integrated filter 5 of Embodiment V. Referring to FIG. 40 to FIG. 41, the first module 704 of the integrated filter 5 is formed in a multilayer medium layer 105. The multilayer medium layer 105 is formed by stacking a plurality of dielectric layers along a stacking direction, and the dielectric layers can be composed of one or more dielectric materials such as gallium arsenide, silicon carbide, silicon nitride, aluminum nitride, aluminum oxide, glass, silicon oxide, etc. The first connection terminal 605 in the first module 704 and the capacitive structure of the first stacked electronic device D3 share the same metallized electrode E29, and the capacitive structure of the first stacked electronic device D3 also includes a metallized electrode E30, which is formed on different dielectric layers and faces each other with the electrode E29, and is coupled to form the capacitive structure of the first stacked electronic device D3. The electrode E30 is located below the electrode E29 along the stacking direction. Two via conductors 409 penetrate the dielectric layer along the stacking direction. The via conductors 409 can be formed by through holes made of one or more metallized materials such as Ag, Au, Cu, etc., or can be formed by solid cylinders made of one or more metallized materials such as Ag, Au, Cu, etc. One end of one via conductor 409 is connected to electrode E29, and the other end is connected to the first pattern conductor 212. One end of the other via conductor 409 is connected to the first pattern conductor 212, and the other end is connected to the metallized electrode E31. The first additional capacitive structure 801 is formed by coupling electrode E31 and metallized electrode E32. Electrode E31 and electrode E32 are formed on different dielectric layers and face each other. Electrode E32 is located below electrode E31 along the stacking direction. Electrode E29, electrode E30, electrode E31, and electrode E32 can be made of one or more metallized materials such as Ag, Au, Cu, etc. The first pattern conductor 212 is located above the electrode E29, the electrode E30, the electrode E31, and the electrode E32 along the stacking direction, and is composed of one or more metalized materials such as Ag, Au, and Cu, extending from one point in the form of a zigzag line to form a spiral shape, and the spiral shape contains a bent zigzag line. The two ends of the first pattern conductor 212 are respectively connected to two via conductors 409. The electrode E32 can be coupled to the first additional inductive structure 903 through a copper column. The first additional inductive structure 903 is composed of one or more metalized materials such as Ag, Au, and Cu, and is formed on the filter mounting carrier. It is extended from one point in the form of a zigzag line to form a spiral shape, and the spiral shape contains a bent zigzag line. The first potential terminal 606 is formed on the first additional inductive structure 903. The first potential terminal 606 is connected to the reference ground on the filter mounting carrier.

Fig. 42 is a transparent top view of the first module 704 of the integrated filter 5 according to Embodiment V. Referring to Fig. 42, the electrodes E29 and E30 constituting the capacitive structure of the first stacked electronic device D3 and the electrodes E31 and E32 constituting the first additional capacitive structure 801 are located below the first pattern conductor 212 along the stacking direction, and the projection of the first pattern conductor 212 on a plane perpendicular to the stacking direction of the first stacked electronic device D3 at least partially overlaps with the projection of the electrodes E29, E30, E31 and E32 on a plane perpendicular to the stacking direction of the first stacked electronic device D3. The first module 704 utilizes the capacitive structure of the first stacked electronic device D3 and the first additional capacitive structure 801 as a barrier between the first pattern conductor 212 and the mounting surface, and can confine most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D3 within the dielectric layer between the first pattern conductor 212 and the capacitive structure of the stacked electronic device D3 and the first additional capacitive structure 801, thereby increasing the stability of the electromagnetic field between the first pattern conductor 213 and the mounting surface, and reducing the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the performance of the integrated filter, thereby making the filter performance have a strong tolerance capability for mass manufacturing and application installation conditions.

FIG43 is a perspective view of the second module 705 of the integrated filter 5 according to Embodiment V. Referring to FIG43 , the second module 705 of the integrated filter 5 is formed in the multilayer medium layer 105. The second connection terminal 607 and the second additional capacitive structure 802 in the second module 705 share the same metallized electrode E33. The second additional capacitive structure 802 also includes The metallized electrode E34 is formed on different dielectric layers and faces the electrode E33, and is coupled to form a second additional capacitive structure. The metallized electrode E34 is located below the electrode E33 along the stacking direction. The metallized electrode E35 and the metallized electrode E36 are formed on different dielectric layers and face each other, and are coupled to form a capacitive structure of the second stacked electronic device D4. The metallized electrode E36 is located below the electrode E35 along the stacking direction. The electrode E35 is connected to one end of the second additional inductive structure 904 through a metal conductor. The second additional inductive structure 904 can be composed of one or more metallized materials such as Ag, Au, Cu, etc., and extends from a point in the form of a broken line to form a bent shape. The other end of the second additional inductive structure 904 is connected to the metallized electrode E34. The electrode E33, the electrode E34, the electrode E35 and the electrode E36 can be composed of one or more metallized materials such as Ag, Au, Cu, etc. Two via conductors 410 penetrate the dielectric layer along the stacking direction. The via conductors 410 may be formed by through holes made of one or more metallized materials such as Ag, Au, and Cu, or may be formed by solid cylinders made of one or more metallized materials such as Ag, Au, and Cu. One end of one via conductor 410 is connected to electrode E36 through a metal conductor, and the other end is connected to the first pattern conductor 213. One end of another via conductor 410 is connected to the first pattern conductor 213, and the other end is connected to electrode E35. The first pattern conductor 213 is located above electrode E33, electrode E34, electrode E35, electrode E36, and the second additional inductive structure 904 along the stacking direction, and is made of one or more metallized materials such as Ag, Au, and Cu. It extends from one point in the form of a zigzag line to form a spiral shape, and the spiral shape includes a bent zigzag line. The two ends of the first pattern conductor 213 are respectively connected to the two via conductors 410. The second potential end 608 is made of a metallized material and is formed on the metallized electrode E36. The second potential terminal 608 can be connected to the reference ground on the filter mounting carrier through a mounting interface in the form of a conductive bump, a BGA solder ball, a bump, a Cu-Pillar, etc.

Fig. 44 is a transparent top view of the second module 705 of the integrated filter 5 of Embodiment V. Referring to Fig. 44, the electrodes E35 and E36 constituting the capacitive structure of the second stacked electronic device D4 are located below the first pattern conductor 213 along the stacking direction, the electrodes E33 and E34 constituting the second additional capacitive structure 802 are located below the first pattern conductor 213 along the stacking direction, and the projection of the first pattern conductor 213 on a plane perpendicular to the stacking direction of the second stacked electronic device D4 at least partially overlaps with the projection of the electrodes E33, E34, E35, and E36 on a plane perpendicular to the stacking direction of the second stacked electronic device D4. The second module 705 utilizes the capacitive structure of the second stacked electronic device D4 and the second additional capacitive structure 802 as a barrier between the first pattern conductor 213 and the mounting surface, and can confine most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D4 within the dielectric layer between the first pattern conductor 213 and the capacitive structure of the stacked electronic device D4 and the second additional capacitive structure 802, thereby increasing the stability of the electromagnetic field between the first pattern conductor 213 and the mounting surface, and reducing the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the performance of the integrated filter, so that the filter performance has a strong tolerance capability for mass manufacturing and application installation conditions.

FIG. 45 is a perspective view of the third module 703 of the integrated filter 5 of Embodiment V. Referring to FIG. 45 , the third module 703 of the integrated filter 5 is formed in the multilayer medium layer 105. The third connection terminal 609 in the third module 703 and the third additional capacitive structure 803 share the same metallized electrode E37. The third additional capacitive structure 803 also includes a metallized electrode E38, which is formed on a different dielectric layer from the electrode E37 and faces each other, and is coupled to form the third additional capacitive structure 803. The electrode E37 is located below the electrode E38 along the stacking direction. The metallized electrode E39 is formed in a bent shape, and is formed on a different dielectric layer from the electrode E38 and faces each other. The metallized electrode E40 and the electrode E39 are formed on different dielectric layers and face each other. The metallized electrode E38, the metallized electrode E39, and the electrode E40 are coupled together to form the capacitive structure in the third stacked electronic device D5. The metallized electrode E39 is located below the electrodes E38 and E40 along the stacking direction. The electrodes E37, E38, E39, and E40 can be made of one or more metallized materials such as Ag, Au, and Cu. Two via conductors 411 penetrate the dielectric layer along the stacking direction. One end of one via conductor 411 is connected to the metallized electrode E38, and the other end is connected to the first pattern conductor 214; one end of the other via conductor 411 is connected to the first pattern conductor 214, and the other end is connected to the metallized electrode E40. The via conductor 411 can be made of a through hole made of one or more metallized materials such as Ag, Au, and Cu, or a solid cylinder made of one or more metallized materials such as Ag, Au, and Cu. The first pattern conductor 214 is located above the electrodes E37, E38, E39, and E40 along the stacking direction, and is made of one or more metallized materials such as Ag, Au, and Cu. It extends from a point in the form of a zigzag line to form a spiral shape, and the spiral shape contains a bent zigzag line. The two ends of the first pattern conductor 214 are connected to the two via conductors 411 respectively. The capacitive structure in the third stacked electronic device D5 and the third additional capacitive structure 803 are The fourth connection terminal 610 and the capacitive structure in the third stacked electronic device D5 share the metallized electrode E40;

FIG46 is a transparent top view of the third module 703 of the integrated filter 5 of Embodiment V. Referring to FIG46 , the electrodes E38, E39, and E40 constituting the capacitive structure of the third stacked electronic device D5 are located below the first pattern conductor 214 along the stacking direction, and the electrodes E38 and E37 constituting the third additional capacitive structure 803 are located below the first pattern conductor 214 along the stacking direction; viewed from the stacking direction, the projections of the structures of the electrodes E38 and E39 on the plane perpendicular to the stacking direction partially overlap, and the projections of the structures of the electrodes E39 and E49 on the plane perpendicular to the stacking direction partially overlap. The projection of the first pattern conductor 214 on the plane perpendicular to the stacking direction of the third stacked electronic device D5 at least partially overlaps with the projection of the electrodes E37, E38, E39 and E40 on the plane perpendicular to the stacking direction. The third module 703 utilizes the capacitive structure of the third stacked electronic device D5 and the third additional capacitive structure 803 as a barrier between the first pattern conductor 214 and the mounting surface, and can confine most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D5 within the dielectric layer between the first pattern conductor 214 and the capacitive structure of the stacked electronic device D5 and the third additional capacitive structure 803, thereby increasing the stability of the electromagnetic field between the first pattern conductor 214 and the mounting surface, and reducing the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the performance of the integrated filter, so that the filter performance has a strong tolerance capability for mass manufacturing and application installation conditions.

FIG. 47 and FIG. 48 are perspective views of the integrated filter 5 of Embodiment V. Referring to FIG. 47 and FIG. 48, the first module 704, the second module 705 and the third module 703 are all formed in the multilayer medium layer 105. The first input/output terminal 601 of the integrated filter 5 is formed on the metallized electrode E41. The electrode E41 is connected to the electrode E29 of the first module 704 through a metal conductor, the first common terminal 603 and the first connection terminal 605 of the first module 704 share the electrode E29, and the electrode E29 is also connected to the electrode E37 of the third module 703. The second input/output terminal 602 of the integrated filter 5 is formed on the metallized electrode E42. The electrode E42 and the electrode E33 are formed on different dielectric layers and face each other, and are coupled to form a fourth additional capacitive structure 804. The metallized electrode E42 is located below the electrode E33 along the stacking direction. The fourth additional capacitive structure 804 shares the electrode E42 with the second input/output terminal 602. The second common terminal 604 shares the electrode E33 with the second connection terminal 607 of the second module and the fourth additional capacitive structure 804, and the electrode E33 is connected to the electrode E40 of the third module 703. At this time, the first connection terminal 605 of the first module 704 is connected to the first common terminal 603, the third connection terminal 609 of the third module 703 is connected to the first common terminal 603, and the first common terminal 603 is connected to the first input-output terminal 601; the second connection terminal 607 of the second module 705 is connected to the second common terminal 604, the second common terminal 604 is connected to the fourth connection terminal 610 of the third module, the second common terminal 604 is connected to one end of the fourth additional capacitive structure 804, and the other end of the fourth additional capacitive structure is connected to the second input-output terminal 602. Electrodes E41 and E42 are formed on the surface of the dielectric layer of the multilayer medium layer 104, and can be connected to the mounting surface of the integrated filter through mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillar, etc., and can be composed of one or more metallized materials such as Ag, Au, Cu, etc. The first additional inductive structure 903 is formed on the surface of the integrated filter mounting carrier, and can be connected to the electrode E32 through mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillar, etc. The internal structures and connection relationships of the first module 704, the second module 705, and the third module 703 are the same as described above. The arrangement layout direction of the first module 704, the second module 705, and the third module 703 is perpendicular to the stacking direction of the dielectric layer of the multilayer medium layer 105.

Compared with the integrated filter 4, the fourth additional capacitive structure 804 added to the integrated filter 5 has obvious blocking characteristics for low-frequency signals, while the transmission of high-frequency signals is not affected, which is beneficial to enhancing the filter's suppression performance for low-frequency out-of-band interference. The grounded first module 704 of the integrated filter 5 is loaded by the first additional capacitive structure 801 and the first additional inductive structure 903, which is beneficial to the introduction of multiple controllable transmission zero points. The grounded second module 705 is loaded by the second additional capacitive structure 802 and the second additional inductive structure 904, which is also beneficial to the introduction of multiple transmission zero points. The third module 703 is beneficial to the introduction of the transmission zero point of the integrated filter, thereby improving the selection characteristics of the integrated filter by utilizing the third module 703. Without the need for an additional resonator structure, multi-transmission zero-point filtering of the filter is realized, which effectively improves the frequency selection performance of the filter, and makes the filter have the advantages of simple structure, small size, and high out-of-band noise suppression performance. The loading of the third additional capacitive structure 803 can adjust the impedance matching between the third stacked electronic device D5 and the first module 701 and the second module 702. The fourth additional capacitive structure 804 can also flexibly adjust the impedance matching between the second input and output end and the second module 705 and the third module 703.

Since the first stacked electronic device D3, the second stacked electronic device D4, and the third stacked electronic device D5 are all structures of the stacked electronic devices in the aforementioned embodiments or their variations, based on the characteristics of the stacked electronic devices, the integrated filter 5 has the advantages of high frequency selectivity and miniaturization and can effectively reduce the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, Bumps, Cu-Pillars, etc. on the filter performance, so that the filter has a strong tolerance capability in mass manufacturing and application installation, which is conducive to improving the yield of large-scale production and delivery of filters.

Fig. 49 is a side view of the integrated filter 5 of Embodiment V when it is fixed to the mounting surface. Referring to Fig. 49, the first additional inductive structure 903 is arranged on the surface of the filter mounting carrier, and is located below the multilayer medium layer 105 along the stacking direction. The second additional inductive structure 904 is arranged on the lower surface of the multilayer medium layer 105, and is located between the first pattern conductor 213 and the integrated filter mounting surface along the stacking direction. The electrodes E29-E42 are located between the first pattern conductor 212, the first pattern conductor 213, the first pattern conductor 214 and the integrated filter mounting surface along the stacking direction.

FIG50 is a top view of the integrated filter 5 of Embodiment V when it is fixed to the mounting surface. FIG51 is a structural stereogram of the integrated filter 5 of Embodiment V when it is fixed to the mounting surface. Referring to FIG50 and FIG51, the layout of the first to third stacked electronic devices in the integrated filter 5 is that the projection of the first pattern conductor 214 of the third stacked electronic device D5 on the integrated filter mounting surface 504 is sandwiched between the projection of the first pattern conductor 212 of the first stacked electronic device D3 on the integrated filter mounting surface 504 and the projection of the first pattern conductor 213 of the second stacked electronic device D4 on the integrated filter mounting surface 504. The mounting surface 504 is a surface of a mounting carrier for fixing the integrated filter 5 or for fixing any electronic device composed of the integrated filter 5, and the mounting carrier is a substrate including at least one layer of metallized material or at least one layer of dielectric layer, such as a PCB substrate, ABF substrate, FCBGA substrate, silicon-based adapter board, glass-based adapter board, etc., which are composed of at least one layer of metallized material and at least one layer of dielectric layer. In this embodiment, the filter is fixed on the FCBGA substrate by metallized micro-bumps (BGA, Bump, Cu-pillar, etc.), and is interconnected with other components such as power amplifiers and low-noise amplifiers to realize the function of the RF front-end module. The projection of the first module 704 on the integrated filter mounting surface 504, the projection of the second module 705 on the integrated filter mounting surface 504, and the projection of the third module 703 on the integrated filter mounting surface 504 partially overlap. This compact structural layout can further reduce the size of the filter and realize the miniaturization design of the filter.

Figure 52 is a reflection and transmission characteristic diagram of the integrated filter 5 of the fifth embodiment. Referring to Figure 52, the first module 704 of the integrated filter 5 generates transmission zero TZ1 and transmission zero TZ5, and the second module 705 generates transmission zero TZ2 and transmission zero TZ4, and the above-mentioned transmission zero TZ1 and transmission zero TZ2 are on the left side of the passband, which improves the frequency selectivity of the left side of the passband. Transmission zero TZ4 and transmission zero TZ5 are on the right side of the passband, thereby improving the frequency selectivity of the right side of the passband. At the same time, the third module 703 generates a transmission zero TZ3 located on the right side of the passband, thereby improving the frequency selectivity of the right side of the passband. Compared with the reflection and transmission characteristics of the integrated filter 4 of Figure 38, the fourth additional capacitive structure 804 added to the integrated filter 5 enhances the suppression performance of low-frequency out-of-band interference signals.

In addition, the fourth additional capacitive structure 804 may also be formed by coupling three or more metallized electrodes formed on different dielectric layers and in a face-to-face relationship. In addition, the first additional inductive structure or the second additional inductive structure may also be formed inside the filter mounting carrier.

The integrated filter 6 of embodiment VI of the present application is described below. The integrated filter 6 involved in embodiment VI is different from embodiment V in that its third module includes more than one third additional capacitive structure, which can further enhance the tolerance capability of the filter in batch manufacturing and application installation state;

Fig. 53 is a circuit diagram of the circuit structure of the integrated filter 6 of Embodiment VI. Referring to Fig. 53, the integrated filter 6 comprises a first input-output terminal 601, a second input-output terminal 602, a first module 706, a second module 707, a third module 708, a first common terminal 603 and a second common terminal 604, a fifth additional capacitive structure 805, a path 11, a path 12, a path 13, a path 14, a path 15 and a path 16; the first input-output terminal 601, the second input-output terminal 602, the first common terminal 603 and the second common terminal 604 are made of one or more metallized materials such as Ag, Au, and Cu;

The first module 706 includes a first connection terminal 605, a first stacked electronic device D3, a first additional capacitive structure 801, The first potential terminal 606, the first additional inductive structure 905, the path 17, and the path 18. The first connection terminal 605 is made of a metalized material. The first stacked electronic device D3 is the structure of the stacked electronic device in the aforementioned embodiment or a modified example thereof. The first additional capacitive structure 801 is formed by coupling a plurality of metalized electrodes facing each other. The first additional inductive structure 905 is made of a metalized material. The first potential terminal 606 is made of a metalized material and is used to connect to the reference ground. The path 17 connects the first connection terminal 605 to the first stacked electronic device D3. The path 18 connects the first stacked electronic device D3 to the first potential terminal 606. The first additional capacitive structure 801 is arranged on the path 17, and the first additional inductive structure 905 is arranged on the path 18.

The second module 707 includes a second connection terminal 607, a second potential terminal 608, a second stacked electronic device D4, a second additional capacitive structure 802, a second additional inductive structure 906, a path 19, and a path 20. The second connection terminal 607 is made of a metalized material, the second stacked electronic device D4 is the structure of the stacked electronic device in the aforementioned embodiment or a modified example thereof, the second additional capacitive structure 802 is formed by coupling a plurality of metalized electrodes facing each other, the second additional inductive structure 906 is made of a metalized material, and the second potential terminal is made of a metalized material for connecting to a reference ground. The path 19 connects the second connection terminal 607 to the second stacked electronic device D4, the path 20 connects the second stacked electronic device D4 to the second potential terminal 608, the second additional capacitive structure 802 is arranged on the path 19, and the second additional inductive structure 906 is arranged on the path 20.

The third module 708 includes a third connection terminal 609, a fourth connection terminal 610, a third stacked electronic device D5, a third additional capacitive structure 803, a third additional capacitive structure 806, a path 21, and a path 22. The third connection terminal 609 and the fourth connection terminal 610 are made of metallized materials. The third stacked electronic device D5 is the structure of the stacked electronic device in the aforementioned embodiment or a modified example thereof. The third additional capacitive structure 803 and the third additional capacitive structure 806 are formed by coupling a plurality of metallized electrodes that face each other. The path 21 connects the third connection terminal 609 to the third stacked electronic device D5, the path 22 connects the third stacked electronic device D5 to the fourth connection terminal 610, the third additional capacitive structure 803 is arranged on the path 21, and the third additional capacitive structure 806 is arranged on the path 22.

The first connection terminal 605 of the first module 706 is connected to the first common terminal 603 through a path 12, and the third connection terminal 609 of the third module 708 is connected to the first common terminal 603 through a path 13. The second connection terminal 607 of the second module 705 is connected to the second common terminal 604 through a path 14, and the second common terminal 604 is connected to the fourth connection terminal 610 of the third module through a path 15, and the second common terminal 604 is connected to the second input-output terminal 602 through a path 16. The first common terminal 603 is connected to one end of the fifth additional capacitive structure 805, and the other end of the fifth additional capacitive structure 805 is connected to the first input-output terminal 601. The fifth additional capacitive structure 805 is arranged on the path 11 between the first common terminal 603 and the first input-output terminal 601.

Next, the structure of the integrated filter 6 will be described with reference to FIG. 53 to FIG. 66 .

FIG. 54 and FIG. 55 are perspective views of the first module 706 of the integrated filter 6 of Embodiment VI. Referring to FIG. 54 to FIG. 55, the first module 706 of the integrated filter 6 is formed in the multilayer medium layer 106. The multilayer medium layer 106 is formed by stacking a plurality of dielectric layers along the stacking direction. The dielectric layers can be composed of one or more dielectric materials such as gallium arsenide, silicon carbide, silicon nitride, aluminum nitride, aluminum oxide, glass, silicon oxide, etc. The first connection terminal 605 in the first module 706 and the first additional capacitive structure 801 share the same metallized electrode E43. The first additional capacitive structure 801 also includes a metallized electrode E44, which is formed on different dielectric layers and faces each other with the electrode E43, and is coupled to form the first additional capacitive structure 801. The electrode E43 is located below the electrode E44 along the stacking direction. Two via conductors 412 penetrate the dielectric layer along the stacking direction. The via conductors 412 can be formed by through holes made of one or more metallized materials such as Ag, Au, Cu, etc., or can be formed by solid cylinders made of one or more metallized materials such as Ag, Au, Cu, etc. One via conductor 412 is connected to the electrode E44 at one end, and connected to the first pattern conductor 215 at the other end. Another via conductor 412 is connected to the first pattern conductor 215 at one end, and connected to the metallized electrode E46 at the other end through a metal conductor. The capacitive structure of the first stacked electronic device D3 is formed by coupling the electrode E45 and the metallized electrode E46. The electrode E45 and the electrode E46 are formed on different dielectric layers and face each other. The electrode E45 is connected to the electrode E44, and the electrode E46 is located below the electrode E45 along the stacking direction. The electrodes E43, E44, E45, and E46 can be made of one or more metallized materials such as Ag, Au, Cu, etc. The first pattern conductor 215 is located above the electrodes E43, E44, E45, and E46 along the stacking direction, and is made of one or more metallized materials such as Ag, Au, and Cu, and extends from one point in the form of a broken line to form a spiral. The first pattern conductor 215 has two ends connected to two via conductors 412. The electrode E46 can be coupled to the first additional inductive structure 905 through a copper column. The first additional inductive structure 905 is composed of one or more metallized materials such as Ag, Au, Cu, etc., and is formed on the filter mounting carrier. It extends from one point in the form of a folded line to form a spiral shape, and the spiral contains a folded line. The first potential terminal 606 is formed on the first additional inductive structure 905. The first potential terminal 606 is connected to the reference ground on the filter mounting surface.

Fig. 56 is a transparent top view of the first module 706 of the integrated filter 6 of Embodiment VI. Referring to Fig. 56, the electrodes E46 and E45 constituting the capacitive structure of the first stacked electronic device D3 and the electrodes E44 and E43 constituting the first additional capacitive structure 801 are located below the first pattern conductor 215 along the stacking direction, and the projection of the first pattern conductor 215 on the plane perpendicular to the stacking direction of the first stacked electronic device D3 at least partially overlaps with the projection of the electrodes E43, E44, E45, and E46 on the plane perpendicular to the stacking direction of the first stacked electronic device D3. The first module 706 utilizes the capacitive structure of the first stacked electronic device D3 and the first additional capacitive structure 801 as a barrier between the first pattern conductor 215 and the mounting surface, and can confine most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D3 within the dielectric layer between the first pattern conductor 215 and the capacitive structure of the stacked electronic device D3 and the first additional capacitive structure 801, thereby increasing the stability of the electromagnetic field between the first pattern conductor 215 and the mounting surface, and reducing the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the performance of the integrated filter, thereby making the filter performance have a strong tolerance capability for mass manufacturing and application installation conditions.

FIG57 is a perspective view of the second module 707 of the integrated filter 6 of Embodiment VI. Referring to FIG57 , the second module 707 of the integrated filter 6 is formed in the multilayer medium layer 106. The second connection terminal 607 in the second module 707 shares the same metallized electrode E47 with the second additional capacitive structure 802. The second additional capacitive structure 802 also includes a metallized electrode E48, which is formed on different dielectric layers and faces the electrode E47, and is coupled to form the second additional capacitive structure 802. The electrode E47 is located below the electrode E48 along the stacking direction. The metallized electrode E49 and the metallized electrode E50 are formed on different dielectric layers and face each other, and are coupled to form the capacitive structure of the second stacked electronic device D4. The electrode E50 is located below the electrode E49 along the stacking direction. The electrode E48 is connected to the electrode E49. The electrode E50 is connected to one end of the second additional inductive structure 906. The second additional inductive structure 906 is made of one or more metallized materials such as Ag, Au, Cu, etc., and extends from one point in the form of a broken line to form a bent shape. The other end of the second additional inductive structure 906 is connected to the reference ground through a copper column. The electrodes E47, E48, E49 and E50 can be made of one or more metallized materials such as Ag, Au, Cu, etc. Two via conductors 413 penetrate the dielectric layer along the stacking direction. The via conductors 413 can be made of through holes made of one or more metallized materials such as Ag, Au, Cu, etc., or can be made of solid columns made of one or more metallized materials such as Ag, Au, Cu, etc. One end of one of the via conductors 413 is connected to the electrode E49, and the other end is connected to the first pattern conductor 216. One end of the other via conductor 413 is connected to the first pattern conductor 216, and the other end is connected to the second additional inductive structure 906 through a metal conductor. The first pattern conductor 216 is located above the electrode E47, the electrode E48, the electrode E49, the electrode E50, and the second additional inductive structure 906 along the stacking direction, and is made of one or more metallized materials such as Ag, Au, and Cu, extending from one point in the form of a zigzag line to form a spiral shape, and the spiral shape includes a bent zigzag line. The two ends of the first pattern conductor 216 are respectively connected to the two via conductors 413. The second potential end 608 is made of a metallized material, formed on the second additional inductive structure 906, and connected to the reference ground on the filter mounting carrier by means of a solder ball or a copper column.

Fig. 58 is a transparent top view of the second module 707 of the integrated filter 6 of Embodiment VI. Referring to Fig. 58, the electrodes E49 and E50 constituting the capacitive structure of the second stacked electronic device D4 are located below the first pattern conductor 216 along the stacking direction, the electrodes E47 and E48 constituting the second additional capacitive structure 802 are located below the first pattern conductor 216 along the stacking direction, and the projection of the first pattern conductor 216 on a plane perpendicular to the stacking direction of the second stacked electronic device D4 at least partially overlaps with the projection of the electrodes E47, E48, E49, and E50 on a plane perpendicular to the stacking direction of the second stacked electronic device D4. The second module 707 uses the capacitive structure of the second stacked electronic device D4 and the second additional capacitive structure 802 as a barrier between the first pattern conductor 216 and the mounting surface, and can confine most of the electromagnetic field that affects the fluctuation of the equivalent inductance of the stacked electronic device D4 within the dielectric layer between the first pattern conductor 216 and the capacitive structure of the stacked electronic device D4 and the first additional capacitive structure 802, thereby increasing the stability of the electromagnetic field between the first pattern conductor 216 and the mounting surface and reducing the electromagnetic field caused by conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. The height error of the mounting interface has a negative impact on the performance of the integrated filter, making the filter performance have a strong tolerance for batch manufacturing and application installation conditions.

FIG59 is a perspective view of the third module 708 of the integrated filter 6 of Embodiment VI. Referring to FIG59 , the third module 708 of the integrated filter 6 is formed in the multilayer medium layer 106. The third connection terminal 609 in the third module 708 and the third additional capacitive structure 803 share the same metallized electrode E51. The third additional capacitive structure 803 also includes metallized electrodes E52 and E53. The electrode E52 and the electrode E51 are formed on different dielectric layers and face each other. The electrode E53 and the electrode E52 are formed on different dielectric layers and face each other. The electrodes E51, E52, and E53 are coupled to form the third additional capacitive structure 803. The electrode E52 is located above the electrodes E51 and E53 along the stacking direction. The metallized electrode E54 and the electrode E55 are formed on different dielectric layers and face each other, the metallized electrode E55 and the electrode E56 are formed on different dielectric layers and face each other, and the metallized electrode E54, the metallized electrode E55 and the electrode E56 are coupled together to form a capacitive structure in the third stacked electronic device D5. Electrode E54 is connected to electrode E53 through a metal conductor. Metallized electrode E55 is located below electrodes E54 and E56 along the stacking direction. Metallized electrode E57 and metallized electrode E58 are formed on different dielectric layers and face each other, and are coupled to form a third additional capacitive structure 806. Electrode E57 is connected to electrode E56 and is located above electrode E58 along the stacking direction. Electrodes E51-E58 can be composed of one or more metallized materials such as Ag, Au, and Cu. Two via conductors 414 penetrate the dielectric layer in the stacking direction. One end of one via conductor 414 is connected to the metallized electrode E54, and the other end is connected to the first pattern conductor 217; one end of the other via conductor 414 is connected to the first pattern conductor 217, and the other end is connected to the metallized electrode E57. The via conductor 414 can be composed of a through hole composed of one or more metallized materials such as Ag, Au, Cu, etc., or a solid cylinder composed of one or more metallized materials such as Ag, Au, Cu, etc. The first pattern conductor 217 is located above the electrodes E51-E58 in the stacking direction, and can be composed of one or more metallized materials such as Ag, Au, Cu, etc., extending from a point in the form of a zigzag line to form a spiral shape, and the spiral shape contains a bent zigzag line. The fourth connection terminal 610 shares the metallized electrode E58 with the third additional capacitive structure 806;

Fig. 60 is a transparent top view of the third module 708 of the integrated filter 6 of Embodiment VI. Referring to Fig. 60, the electrodes E54, E55, and E56 constituting the capacitive structure of the third stacked electronic device D5 are located below the first pattern conductor 217 along the stacking direction, the electrodes E51, E52, and E53 constituting the third additional capacitive structure 803 are located below the first pattern conductor 217 along the stacking direction, and the electrodes E57 and E58 constituting the third additional capacitive structure 806 are located below the first pattern conductor 217 along the stacking direction; the projection of the first pattern conductor 217 on a plane perpendicular to the stacking direction of the third stacked electronic device D5 at least partially overlaps with the projection of the electrodes E51-E58 on a plane perpendicular to the stacking direction of the third stacked electronic device D5. The third module 708 utilizes the capacitive structure of the third stacked electronic device D5 and the third additional capacitive structure 803 and the third additional capacitive structure 806 as a barrier between the first pattern conductor 217 and the mounting surface, so that most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D5 can be bound within the dielectric layer between the first pattern conductor 217 and the capacitive structure, the third additional capacitive structure 803 and the third additional capacitive structure 806 of the stacked electronic device D5, thereby increasing the stability of the electromagnetic field between the first pattern conductor 217 and the mounting surface, reducing the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-pillars, etc. on the performance of the integrated filter, and making the filter performance have a strong tolerance capability for mass manufacturing and application installation conditions.

FIG61 and FIG62 are perspective views of the integrated filter 6 of Embodiment VI. Referring to FIG61 and FIG62, the first module 706, the second module 707 and the third module 708 are all formed in the multilayer medium layer 106. The first input-output terminal 601 of the integrated filter 6 is formed on the metallized electrode E59. The electrode E59 is connected to the metallized electrode E60 through a metal conductor. The electrode E60 and the electrode E61 are formed on different dielectric layers and face each other, and the electrodes E60 and E61 are coupled to form a fifth additional capacitive structure 805. The metallized electrode E61 is located below the electrode E60 along the stacking direction. The electrode E61 is connected to the electrode E43. The first common terminal 603 is formed on the electrode E43, and the electrode E43 is also connected to the electrode E51 of the third module 708. The second input-output terminal 602 of the integrated filter 6 is formed on the metallized electrode E62. The electrode E62 is connected to the electrode E47. The second common terminal 604 and the second connection terminal 607 of the second module share the electrode E47, and the electrode E47 is connected to the electrode E58 of the third module 703. At this time, the first connection terminal 605 of the first module 704 is connected to the first common terminal 603, the third connection terminal 609 of the third module 703 is connected to the first common terminal 603, the first common terminal 603 is connected to the fifth additional capacitive structure 805, and the fifth additional capacitive structure 805 is connected to the first input-output terminal 601; the second module The second connection terminal 607 of the block 705 is connected to the second common terminal 604, the second common terminal 604 is connected to the fourth connection terminal 610 of the third module, and the second common terminal 604 is connected to the second input-output terminal 602. Electrodes E59-E62 can be composed of one or more metallized materials such as Ag, Au, Cu, etc. Electrodes E59 and E62 are formed on the surface of the dielectric layer of the multilayer medium layer 106, and can be connected to the integrated filter mounting surface through mounting interfaces in the form of conductive bumps, BGA solder balls, Bumps, Cu-Pillar, etc., and can be composed of one or more metallized materials such as Ag, Au, Cu, etc. The first additional inductive structure 905 is formed on the integrated filter mounting carrier, and can be connected to the electrode E46 through mounting interfaces in the form of conductive bumps, BGA solder balls, Bumps, Cu-Pillar, etc. The internal structures and connection relationships of the first module 706, the second module 707 and the third module 708 are the same as described above. The arrangement direction of the first module 706 , the second module 707 and the third module 708 is perpendicular to the stacking direction of the dielectric layers of the multi-layer medium layer 106 .

Compared with the integrated filter 5, the third additional capacitive structure 806 added to the integrated filter 6 is arranged between the first pattern conductor 217 and the mounting surface as a barrier, which is conducive to constraining most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D5 in the dielectric layer between the first pattern conductor 217 and the third additional capacitive structure 806, increasing the stability of the electromagnetic field between the first pattern conductor 217 and the mounting surface, and further enhancing the tolerance of the enhanced filter in batch manufacturing and application installation. In addition, the third additional capacitive structure 806 is also conducive to increasing the flexibility of the integrated filter layout. The grounded first module 706 of the integrated filter 6 is loaded by the first additional capacitive structure 801 and the first additional inductive structure 905, which is conducive to the introduction of multiple controllable transmission zeros. The grounded second module 707 is loaded by the second additional capacitive structure 802 and the second additional inductive structure 906, which is also conducive to the introduction of multiple transmission zeros. The third module 703 is conducive to the introduction of the transmission zero of the integrated filter, thereby improving the selection characteristics of the integrated filter by using the third module 703. Without the need for an additional resonator structure, the multi-transmission zero-point filtering of the filter is realized, which effectively improves the frequency selectivity of the filter, and makes the filter have the advantages of simple structure, small size, and high out-of-band noise suppression performance. The loading of the third additional capacitive structure 803 and the third additional capacitive structure 806 can adjust the impedance matching between the third stacked electronic device D5 and the first module 706 and the second module 707. The fifth additional capacitive structure 805 can also flexibly adjust the impedance matching between the first input and output end and the first module 706 and the third module 703.

Since the first stacked electronic device D3, the second stacked electronic device D4, and the third stacked electronic device D5 are all structures of the stacked electronic devices in the aforementioned embodiments or their variations, based on the characteristics of the stacked electronic devices, the integrated filter 6 has the advantages of high frequency selectivity and miniaturization and can effectively reduce the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, Bumps, Cu-Pillars, etc. on the filter performance, so that the filter has a strong tolerance capability in mass manufacturing and application installation, which is conducive to improving the yield of large-scale production and delivery of filters.

FIG63 is a side view of the integrated filter 6 of implementation mode VI when it is fixed to the mounting surface. Referring to FIG63, the first additional inductive structure 905 is arranged on the surface of the filter mounting carrier, and is located below the multilayer medium layer 106 along the stacking direction. The second additional inductive structure 906 is arranged on the lower surface of the multilayer medium layer 106, and is located between the first pattern conductor 216 and the integrated filter mounting surface along the stacking direction. The electrodes E43-E62 are located between the first pattern conductor 215, the first pattern conductor 216, the first pattern conductor 217 and the integrated filter mounting surface along the stacking direction. In other embodiments, the first additional inductive structure or the second additional inductive structure can also be formed inside the filter mounting carrier. FIG64 is a top view of the integrated filter 6 of implementation mode VI when it is fixed to the mounting surface. FIG65 is a structural stereogram of the integrated filter 6 of implementation mode VI when it is fixed to the mounting surface. Referring to Figures 64 to 65, the layout of the first to third stacked electronic devices in the integrated filter 6 is that the projection of the first pattern conductor 217 of the third stacked electronic device D5 on the integrated filter mounting surface 505 is sandwiched between the projection of the first pattern conductor 215 of the first stacked electronic device D3 on the integrated filter mounting surface 505 and the projection of the first pattern conductor 216 of the second stacked electronic device D4 on the integrated filter mounting surface 505. The mounting surface 505 is a surface of a mounting carrier for fixing the integrated filter 6 or for fixing any electronic device composed of the integrated filter 6. The mounting carrier is a substrate including at least one layer of metallized material or at least one layer of dielectric layer, such as a PCB substrate, ABF substrate, FCBGA substrate, silicon-based adapter board, glass-based adapter board, etc. composed of at least one layer of metallized material and at least one layer of dielectric layer. In this embodiment, the filter is fixed on the FCBGA substrate through metallized micro-bumps (BGA, Bump, Cu-pillar, etc.), and is interconnected with other components such as power amplifiers and low-noise amplifiers to realize the function of the RF front-end module. The projection of the first module 706 on the integrated filter mounting surface 505, the projection of the second module 707 on the integrated filter mounting surface 505, and the projection of the third module 708 on the integrated filter mounting surface 506. The projections on the filter mounting surface 505 partially overlap, and this compact structural layout can further reduce the size of the filter and realize the miniaturized design of the filter.

FIG66 is a reflection and transmission characteristic diagram of the integrated filter 6 of the sixth embodiment. Referring to FIG66 , the first module 706 of the integrated filter 6 generates transmission zeros TZ1 and TZ5, and the second module 707 generates transmission zeros TZ2 and TZ4. The transmission zeros TZ1 and TZ2 are on the left side of the passband, which improves the frequency selectivity of the left side of the passband. The transmission zeros TZ4 and TZ5 are on the right side of the passband, thereby improving the frequency selectivity of the right side of the passband. At the same time, the third module 708 generates a transmission zero TZ3 located on the right side of the passband, thereby improving the frequency selectivity of the right side of the passband.

The integrated filter 7 of embodiment VII of the present application is described below. The integrated filter 7 involved in embodiment VII is different from embodiment VI in that it includes two sixth additional capacitive structures, and the additional capacitive structures and additional inductive structures in the first module and the second module of the integrated filter 7 are arranged at different positions in the path from those of the integrated filter 6.

Fig. 67 is a circuit diagram of the circuit structure of the integrated filter 7 of Embodiment VII. The integrated filter 7 comprises a first input-output terminal 601, a second input-output terminal 602, a first module 709, a second module 710, a third module 711, a first common terminal 603 and a second common terminal 604, a sixth additional capacitive structure 807, a sixth additional capacitive structure 808, a path 11, a path 12, a path 13, a path 14, a path 15 and a path 16; the first input-output terminal 601, the second input-output terminal 602, the first common terminal 603 and the second common terminal 604 are made of one or more metallized materials such as Ag, Au, and Cu;

The first module 709 includes a first connection terminal 605, a first stacked electronic device D3, a first additional capacitive structure 801, a first potential terminal 606, a first additional inductive structure 907, a path 17, and a path 18. The first connection terminal 605 is made of a metallized material, the first stacked electronic device D3 is the structure of the stacked electronic device in the aforementioned embodiment or a modified example thereof, the first additional capacitive structure 801 is formed by coupling a plurality of metallized electrodes facing each other, the first additional inductive structure 907 is made of a metallized material, and the first potential terminal 606 is made of a metallized material for connecting to a reference ground. Path 17 connects the first connection terminal 605 to the first stacked electronic device D3, path 18 connects the first stacked electronic device D3 to the first potential terminal 606, and the first additional capacitive structure 801 and the first additional inductive structure 907 are arranged on path 18 between the first stacked electronic device D3 and the first potential terminal 606. Starting from the side of the first stacked electronic device D3, the first additional capacitive structure 801 and the first additional inductive structure 907 are connected in sequence.

The second module 710 includes a second connection terminal 607, a second potential terminal 608, a second stacked electronic device D4, a second additional capacitive structure 802, a second additional inductive structure 908, a path 19, and a path 20. The second connection terminal 607 is made of a metalized material, the second stacked electronic device D4 is the structure of the stacked electronic device in the aforementioned embodiment or a modified example thereof, the second additional capacitive structure 802 is formed by coupling a plurality of metalized electrodes facing each other, the second additional inductive structure 908 is made of a metalized material, and the second potential terminal is made of a metalized material for connecting to a reference ground. Path 19 connects the second connection terminal 607 to the second stacked electronic device D4, and path 20 connects the second stacked electronic device D4 to the second potential terminal 608. The second additional capacitive structure 802 and the second additional inductive structure 908 are arranged on path 20 between the second stacked electronic device D4 and the second potential terminal 608, and are connected in sequence from the side of the second stacked electronic device D4 in the order of the second additional capacitive structure 802 and the second additional inductive structure 908.

The third module 711 includes a third connection terminal 609, a fourth connection terminal 610, a third stacked electronic device D5, a third additional capacitive structure 803, a third additional capacitive structure 806, a path 21, and a path 22. The third connection terminal 609 and the fourth connection terminal 610 are made of metallized materials. The third stacked electronic device D5 is the structure of the stacked electronic device in the aforementioned embodiment or a modified example thereof. The third additional capacitive structure 803 and the third additional capacitive structure 806 are formed by coupling a plurality of metallized electrodes that face each other. The path 21 connects the third connection terminal 609 to the third stacked electronic device D5, the path 22 connects the third stacked electronic device D5 to the fourth connection terminal 610, the third additional capacitive structure 803 is arranged on the path 21, and the third additional capacitive structure 806 is arranged on the path 22.

The first connection terminal 605 of the first module 709 is connected to the first common terminal 603 via a path 12, and the third connection terminal 609 of the third module 711 is connected to the first common terminal 603 via a path 13. The second connection terminal 607 of the second module 710 is connected to the second common terminal 604 via a path 14, and the second common terminal 604 is connected to the fourth connection terminal 610 of the third module via a path 15. The first common terminal 603 is connected to one end of the sixth additional capacitive structure 808, and the sixth additional capacitive structure 808 The other end of the sixth additional capacitive structure 808 is connected to the first input-output terminal 601, and the sixth additional capacitive structure 808 is arranged on the path 11 between the first common terminal 603 and the first input-output terminal 601. The second common terminal 604 is connected to one end of the sixth additional capacitive structure 807, and the other end of the sixth additional capacitive structure 807 is connected to the second input-output terminal 602. The sixth additional capacitive structure 807 is arranged on the path 16 between the second common terminal 604 and the second input-output terminal 602.

Next, the structure of the integrated filter 7 will be described with reference to FIGS. 67 to 80 .

FIG68 and FIG69 are perspective views of the first module 709 of the integrated filter 7 of Embodiment VII. Referring to FIG68 and FIG69, the first module 709 of the integrated filter 7 is formed in the multilayer medium layer 107. The multilayer medium layer 107 is formed by stacking a plurality of dielectric layers along the stacking direction, and the dielectric layers can be composed of one or more dielectric materials such as gallium arsenide, silicon carbide, silicon nitride, aluminum nitride, aluminum oxide, glass, silicon oxide, etc. The first connection terminal 605 in the first module 709 and the capacitive structure of the first stacked electronic device D3 share the same metallized electrode E63, and the capacitive structure of the first stacked electronic device D3 also includes a metallized electrode E64 and an electrode E65, the electrode E64 and the electrode E63 are formed on different dielectric layers and face each other, and the electrode E65 and the electrode E65 are formed on different dielectric layers and face each other, and the electrodes E63, E64, and E65 are coupled together to form the capacitive structure of the first stacked electronic device D3. Electrode E64 is located below electrodes E63 and E65 along the stacking direction. Two via conductors 415 penetrate the dielectric layer along the stacking direction. The via conductors 415 can be composed of through holes composed of one or more metallized materials such as Ag, Au, Cu, etc., or can be composed of solid cylinders composed of one or more metallized materials such as Ag, Au, Cu, etc. One end of one via conductor 415 is connected to electrode E63, and the other end is connected to the first pattern conductor 218. One end of another via conductor 415 is connected to the first pattern conductor 218, and the other end is connected to the metallized electrode E65. The first additional capacitive structure 801 is formed by coupling electrode E65 and metallized electrode E66. Electrode E65 and electrode E66 are formed on different dielectric layers and face each other. The first additional capacitive structure 801 shares electrode E65 with the first stacked electronic device D3. Electrode E66 is located below electrode E65 along the stacking direction. Electrode E63, electrode E64, electrode E65, and electrode E66 can be made of one or more metalized materials such as Ag, Au, and Cu. The first pattern conductor 218 is located above the electrodes E63, electrode E64, electrode E65, and electrode E66 along the stacking direction, and is made of one or more metalized materials such as Ag, Au, and Cu, extending from one point in the form of a zigzag line to form a spiral shape, and the spiral shape contains a bent zigzag line. The two ends of the first pattern conductor 218 are respectively connected to two via conductors 415. Electrode E66 can be coupled to the first additional inductive structure 907 through a copper column. The first additional inductive structure 907 is made of one or more metalized materials such as Ag, Au, and Cu, and is formed on the surface of the filter mounting carrier. It is extended from one point in the form of a zigzag line to form a spiral shape, and the spiral shape contains a bent zigzag line. The first potential terminal 606 is formed on the first additional inductive structure 907. The first potential terminal 606 is connected to the reference ground on the filter mounting surface.

Fig. 70 is a transparent top view of the first module 709 of the integrated filter 7 of Embodiment VII. Referring to Fig. 70, the electrodes E63, E64, and E65 constituting the capacitive structure of the first stacked electronic device D3 and the electrodes E65 and E66 constituting the first additional capacitive structure 801 are located below the first pattern conductor 218 along the stacking direction, and the projection of the first pattern conductor 218 on the plane perpendicular to the stacking direction of the first stacked electronic device D3 at least partially overlaps with the projection of the electrodes E63, E64, E65, and E66 on the plane perpendicular to the stacking direction of the first stacked electronic device D3. The first module 709 utilizes the capacitive structure of the first stacked electronic device D3 and the first additional capacitive structure 801 as a barrier between the first pattern conductor 218 and the mounting surface, and can confine most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D3 within the dielectric layer between the first pattern conductor 218 and the capacitive structure of the stacked electronic device D3 and the first additional capacitive structure 801, thereby increasing the stability of the electromagnetic field between the first pattern conductor 218 and the mounting surface, and reducing the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the performance of the integrated filter, thereby making the filter performance have a strong tolerance capability for mass manufacturing and application installation conditions.

FIG71 is a perspective view of the second module 710 of the integrated filter 7 of Embodiment VII. Referring to FIG71 , the second module 710 of the integrated filter 7 is formed in the multilayer medium layer 107. The second connection terminal 607 in the second module 710 and the capacitive structure of the second stacked electronic device D4 share the same metallized electrode E67. The capacitive structure of the second stacked electronic device D4 also includes metallized electrodes E68, E69, E70, and E71. Electrode E68 and electrode E67 are formed on different dielectric layers and face each other. Electrode E69 and electrode E68 are formed on different dielectric layers and face each other. Electrode E70 and electrode E69 are formed on different dielectric layers and face each other. Electrode E71 and electrode E70 are formed on different dielectric layers and face each other. Electrode E67, electrode E68, electrode E69, electrode E70, and electrode E71 are coupled together. Together, they form the capacitive structure of the second stacked electronic device D4; electrodes E68 and E70 are located below electrodes E67, E69, and E71 along the stacking direction. The metallized electrode E71 and the metallized electrode E72 are formed on different dielectric layers and face each other, and are coupled to form a second additional capacitive structure 802. Electrode E72 is located below electrode E71 along the stacking direction. The second additional capacitive structure 802 shares the metallized electrode E71 with the capacitive structure of the second stacked electronic device D4. Electrode E72 is connected to one end of a second additional inductive structure 908, and the second additional inductive structure 908 is composed of one or more metallized materials such as Ag, Au, and Cu, and extends from one point in the form of a broken line to form a bent shape. The other end of the second additional inductive structure 908 is connected to the second potential end 608. Electrodes E67-E72 can be composed of one or more metallized materials such as Ag, Au, and Cu. Two via conductors 416 penetrate the dielectric layer in the stacking direction. The via conductors 416 can be formed by through holes made of one or more metallized materials such as Ag, Au, Cu, etc., or can be formed by solid cylinders made of one or more metallized materials such as Ag, Au, Cu, etc. One end of one via conductor 416 is connected to electrode E67, and the other end is connected to the first pattern conductor 219. One end of another via conductor 416 is connected to the first pattern conductor 219, and the other end is connected to electrode E71. The first pattern conductor 219 is located above the electrodes E67-E72 and the second additional inductive structure 908 in the stacking direction, and is made of one or more metallized materials such as Ag, Au, Cu, etc. It extends from a point in the form of a zigzag line to form a spiral shape, and the spiral shape contains a bent zigzag line. The two ends of the first pattern conductor 219 are respectively connected to the two via conductors 416. The second potential terminal 608 is made of metalized material and can be connected to the reference ground on the filter mounting surface through a mounting interface in the form of a conductive bump, a BGA solder ball, a bump, a Cu-Pillar, etc.

Fig. 72 is a transparent top view of the second module 710 of the integrated filter 7 of Embodiment VII. Referring to Fig. 72, the electrodes E67-E71 constituting the capacitive structure of the second stacked electronic device D4 are located below the first pattern conductor 219 along the stacking direction, the electrodes E71 and E72 constituting the second additional capacitive structure 802 are located below the first pattern conductor 219 along the stacking direction, and the projection of the first pattern conductor 219 on the plane perpendicular to the stacking direction of the second stacked electronic device D4 at least partially overlaps with the projection of the electrodes E67-E72 on the plane perpendicular to the stacking direction of the second stacked electronic device D4. The second module 710 utilizes the capacitive structure of the second stacked electronic device D4 and the second additional capacitive structure 802 as a barrier between the first pattern conductor 219 and the mounting surface, and can confine most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D4 within the dielectric layer between the first pattern conductor 219 and the capacitive structure of the stacked electronic device D4 and the first additional capacitive structure 802, thereby increasing the stability of the electromagnetic field between the first pattern conductor 219 and the mounting surface, and reducing the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillars, etc. on the performance of the integrated filter, thereby making the filter performance have a strong tolerance capability for mass manufacturing and application installation conditions.

FIG73 is a perspective view of the third module 711 of the integrated filter 7 of Embodiment VII. Referring to FIG73 , the third module 711 of the integrated filter 7 is formed in the multilayer medium layer 107. The third connection terminal 609 in the third module 711 and the third additional capacitive structure 803 share the same metallized electrode E73. The third additional capacitive structure 803 also includes a metallized electrode E74 and an electrode E75. The electrode E74 and the electrode E73 are formed on different dielectric layers and face each other. The electrode E75 and the electrode E74 are formed on different dielectric layers and face each other. The electrodes E73, E74, and E75 are coupled to form the third additional capacitive structure 803. The electrode E74 is located below the electrodes E73 and E75 along the stacking direction. The metallized electrode E76 and the electrode E75 are formed on different dielectric layers and face each other, the metallized electrode E77 and the electrode E76 are formed on different dielectric layers and face each other, and the metallized electrode E75, the metallized electrode E76 and the electrode E77 are coupled together to form a capacitive structure in the third stacked electronic device D5. The metallized electrode E76 is located below the electrode E75 and the electrode E77 along the stacking direction. The metallized electrode E77 and the metallized electrode E78 are formed on different dielectric layers and face each other, the metallized electrode E78 and the metallized electrode E79 are formed on different dielectric layers and face each other, and the electrodes E77, the electrodes E78 and the electrodes E79 are coupled together to form a third additional capacitive structure 806. The metallized electrode E78 is located below the electrodes E77 and the electrodes E79 along the stacking direction. The third additional capacitive structure 806 shares the electrode E77 with the capacitive structure in the third stacked electronic device D5. The electrodes E73-E79 can be composed of one or more metallized materials such as Ag, Au, and Cu. Two via conductors 417 penetrate the dielectric layer in the stacking direction. One via conductor 417 is connected to the metallized electrode E75 at one end and to the first pattern conductor 220 at the other end. Another via conductor 417 is connected to the first pattern conductor 220 at one end and to the metallized electrode E77 at the other end. The via conductor 417 can be formed by a through hole made of one or more metallized materials such as Ag, Au, and Cu, or a solid column made of one or more metallized materials such as Ag, Au, and Cu. The first pattern conductor 220 is located above the electrodes E73-E79 in the stacking direction and is made of one or more metallized materials such as Ag, Au, and Cu. The fourth connection terminal 610 and the third additional capacitive structure 806 share the metallized electrode E79.

Fig. 74 is a transparent top view of the third module 711 of the integrated filter 7 of Embodiment VII. Referring to Fig. 74, the electrodes E75, E76, and E77 constituting the capacitive structure of the third stacked electronic device D5 are located below the first pattern conductor 220 along the stacking direction, the electrodes E73, E74, and E75 constituting the third additional capacitive structure 803 are located below the first pattern conductor 220 along the stacking direction, and the electrodes E77, E78, and E79 constituting the third additional capacitive structure 806 are located below the first pattern conductor 220 along the stacking direction; the projection of the first pattern conductor 220 on a plane perpendicular to the stacking direction of the third stacked electronic device D5 at least partially overlaps with the projection of the electrodes E73-E79 on a plane perpendicular to the stacking direction of the third stacked electronic device D5. The third module 711 utilizes the capacitive structure of the third stacked electronic device D5 and the third additional capacitive structure 803 and the third additional capacitive structure 806 as a barrier between the first pattern conductor 220 and the mounting surface, so that most of the electromagnetic fields that affect the fluctuation of the equivalent inductance of the stacked electronic device D5 can be bound within the dielectric layer between the first pattern conductor 220 and the capacitive structure, the third additional capacitive structure 803 and the third additional capacitive structure 806 of the stacked electronic device D5, thereby increasing the stability of the electromagnetic field between the first pattern conductor 220 and the mounting surface, reducing the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-pillars, etc. on the performance of the integrated filter, and making the filter performance have a strong tolerance capability for mass manufacturing and application installation conditions.

FIG. 75 and FIG. 76 are perspective views of the integrated filter 7 of Embodiment VII. Referring to FIG. 75 to FIG. 76, the first module 709, the second module 710 and the third module 711 are all formed in the multilayer medium layer 107. The first input-output terminal 601 of the integrated filter 6 is formed on the metallized electrode E80. The electrode E81 and the electrode E80 are formed on different medium layers and face each other, and the electrodes E80 and E81 are coupled to form the sixth additional capacitive structure 808. The electrode E81 is located above the electrode E80 along the stacking direction. The electrode E81 is connected to the electrode E63. The first common terminal 603 is formed on the electrode E63, and the electrode E63 is also connected to the electrode E73 of the third module 711. The second input-output terminal 602 of the integrated filter 7 is formed on the metallized electrode E82. The electrode E83 and the electrode E82 are formed on different medium layers and face each other, and the electrodes E82 and E83 are coupled to form the sixth additional capacitive structure 807. Electrode E82 is located below electrode E83 along the stacking direction. Electrode E83 is connected to electrode E67. The second common terminal 604 and the second connection terminal 607 of the second module share electrode E67, and electrode E67 is connected to electrode E79 of the third module 711. At this time, the first connection terminal 605 of the first module 709 is connected to the first common terminal 603, the third connection terminal 609 of the third module 711 is connected to the first common terminal 603, the first common terminal 603 is connected to the sixth additional capacitive structure 808, and the sixth additional capacitive structure 808 is connected to the first input-output terminal 601; the second connection terminal 607 of the second module 710 is connected to the second common terminal 604, the second common terminal 604 is connected to the fourth connection terminal 610 of the third module, the second common terminal 604 is connected to the sixth additional capacitive structure 807, and the sixth additional capacitive structure 807 is connected to the second input-output terminal 602. Electrodes E80-E83 can be composed of one or more metallized materials such as Ag, Au, and Cu. Electrode E80 and electrode E82 are formed on the surface of the dielectric layer of the multilayer medium layer 107, and can be connected to the mounting surface of the integrated filter through mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillar, etc., and can be composed of one or more metallized materials such as Ag, Au, Cu, etc. The first additional inductive structure 907 is formed on the mounting surface of the integrated filter, and can be connected to the electrode E66 through mounting interfaces in the form of conductive bumps, BGA solder balls, bumps, Cu-Pillar, etc. The internal structure and connection relationship of the first module 709, the second module 710 and the third module 711 are the same as described above. The arrangement layout direction of the first module 709, the second module 710 and the third module 711 is perpendicular to the stacking direction of the dielectric layer of the multilayer medium layer 107.

The grounded first module 709 of the integrated filter 7 is loaded by the first additional capacitive structure 801 and the first additional inductive structure 907, which is conducive to the introduction of multiple controllable transmission zero points. The grounded second module 710 is loaded by the second additional capacitive structure 802 and the second additional inductive structure 908, which is also conducive to the introduction of multiple transmission zero points. The third module 711 includes a third additional capacitive structure 803 and a third additional capacitive structure 806, so that the third module 711 can not only introduce a transmission zero point in the transmission response, but also more flexibly adjust the impedance matching between the third stacked electronic device D5 and the first module 709 and the second module 710. Without the need for an additional resonator structure, multi-transmission zero-point filtering of the filter is achieved, which effectively improves the frequency selection performance of the filter, so that the filter has the advantages of simple structure, small size, and high out-of-band noise suppression performance. The sixth additional capacitive structure 807 can be set to more flexibly adjust the impedance matching between the second input and output terminal 602 and the second module 710 and the third module 711. The sixth additional capacitive structure 808 can be more flexible. The impedance matching between the first input-output terminal 601 and the first module 709 and the third module 711 is adjusted accordingly.

Since the first stacked electronic device D3, the second stacked electronic device D4, and the third stacked electronic device D5 are all structures of the stacked electronic devices in the aforementioned embodiments or their variations, based on the characteristics of stacked electronic devices, the integrated filter 7 has the advantages of high frequency selectivity and miniaturization and can effectively reduce the adverse effects of height errors of mounting interfaces in the form of conductive bumps, BGA solder balls, Bumps, Cu-Pillars, etc. on the filter performance, so that the filter has a strong tolerance capability in mass manufacturing and application installation, which is conducive to improving the yield of large-scale production and delivery of filters.

FIG. 77 is a side view of the integrated filter 7 of Embodiment VII when it is fixed to the mounting surface. Referring to FIG. 77 , the first additional inductive structure 907 is formed on the surface of the filter mounting carrier and is located below the multilayer medium layer 107 along the stacking direction. The second additional inductive structure 907 is formed on the lower surface of the multilayer medium layer 107 and is located between the first pattern conductor 219 and the integrated filter mounting surface along the stacking direction. The electrodes E63-E83 are located between the first pattern conductor 218, the first pattern conductor 219, the first pattern conductor 220 and the integrated filter mounting surface along the stacking direction. In other embodiments, the first additional inductive structure may also be formed inside the filter mounting carrier.

FIG. 78 is a top view of the integrated filter 7 of Embodiment VII when it is fixed to the mounting surface. FIG. 79 is a structural stereogram of the integrated filter 7 of Embodiment VII when it is fixed to the mounting surface. Referring to FIGS. 78 to 79, the layout of the first to third stacked electronic devices in the integrated filter 7 is that the projection of the first pattern conductor 220 of the third stacked electronic device D5 on the integrated filter mounting surface 507 is sandwiched between the projection of the first pattern conductor 218 of the first stacked electronic device D3 on the integrated filter mounting surface 507 and the projection of the first pattern conductor 219 of the second stacked electronic device D4 on the integrated filter mounting surface 507. The mounting surface 507 is the surface of the mounting carrier for fixing the integrated filter 7 or for fixing any electronic device composed of the integrated filter 7, and the mounting carrier is a substrate including at least one layer of metallized material or at least one layer of dielectric layer, such as a PCB substrate, ABF substrate, FCBGA substrate, silicon-based adapter board, glass-based adapter board, etc., which are composed of at least one layer of metallized material and at least one layer of dielectric layer. In this embodiment, the filter is fixed on the FCBGA substrate by metallized micro-bumps (BGA, Bump, Cu-pillar, etc.), and is interconnected with other components such as power amplifiers and low-noise amplifiers to realize the function of the RF front-end module. The projection of the first module 709 on the integrated filter mounting surface 507, the projection of the second module 710 on the integrated filter mounting surface 507, and the projection of the third module 711 on the integrated filter mounting surface 507 partially overlap. This compact structural layout can further reduce the size of the filter and realize the miniaturization design of the filter.

FIG80 is a reflection and transmission characteristic diagram of the integrated filter 7 of the seventh embodiment. Referring to FIG80 , the return loss characteristic of the integrated filter 7 is good. The first module 709 generates a transmission zero point TZ1 and a transmission zero point TZ5. The second module 710 generates a transmission zero point TZ2 and a transmission zero point TZ4. The transmission zero point TZ1 and the transmission zero point TZ2 are on the left side of the passband, thereby improving the frequency selectivity of the left side of the passband. The transmission zero point TZ4 and the transmission zero point TZ5 are on the right side of the passband, thereby improving the frequency selectivity of the right side of the passband. At the same time, the third module 711 generates a transmission zero point TZ3 located on the right side of the passband, thereby improving the frequency selectivity of the right side of the passband.

FIG81 is a circuit diagram of the filter circuit 1 according to Embodiment VIII of the present application. First, the structure of the filter circuit 1 according to Embodiment VIII of the present application is described with reference to FIG81. The filter circuit 1 comprises: a first input-output electrode 1001, a second input-output electrode 1002, a first band-stop function unit 2001A, a second band-stop function unit 2002A, a third band-stop function unit 2003A, a first matching function unit 3001A, a second matching function unit 3002A, a third matching function unit 3003A, a fourth matching function unit 3004A, a fifth matching function unit 3005A, a sixth matching function unit 3006A, a seventh matching function unit 3007A, an eighth matching function unit 3008A, a first potential terminal 4001, and a second potential terminal 4002. The first input-output electrode 1001 is connected to one end of the first matching functional unit 3001A, the other end of the first matching functional unit 3001A is simultaneously connected to one end of the second matching functional unit 3002A and one end of the fifth matching functional unit 3005A, the other end of the second matching functional unit 3002A is connected to one end of the first band-stop functional unit 2001A, the other end of the first band-stop functional unit 2001A is connected to one end of the third matching functional unit 3003A, the other end of the third matching functional unit 3003A is simultaneously connected to one end of the fourth matching functional unit 3004A and one end of the seventh matching functional unit 3007A, the other end of the fourth matching functional unit 3004A is connected to the second input-output electrode 1002, the other end of the fifth matching functional unit 3005A is connected to one end of the second band-stop functional unit 2002A, the other end of the second band-stop functional unit 2002A is connected to one end of the sixth matching functional unit 3006A, the other end of the sixth matching functional unit 3006A is connected to the first potential end 4001, and the seventh matching functional unit 3007A is connected to the first potential end 4001. The other end of the matching function unit 3007A is connected to one end of the third band-stop function unit 2003A, the other end of the third band-stop function unit 2003A is connected to one end of the eighth matching function unit 3008A, and the other end of the eighth matching function unit 3008A is connected to the second potential end 4002. Among them, the first potential end 4001 and the second potential end 4002 are equipotential with the reference ground. The first band-stop function unit 2001A, the second band-stop function unit 2002A, and the third band-stop function unit 2003A are two-port networks with attenuation poles in their transmission characteristics. The first matching function unit 3001A-the eighth matching function unit 3008A are two-port networks. When the first input-output electrode 1001 is used to access an input signal, the second input-output electrode 1002 is used to provide an output signal, or, when the first input-output electrode 1001 provides an output signal, the second input-output electrode 1002 is used to access an input signal.

FIG82 is a schematic diagram of a two-port network of the first to eighth matching functional units. Referring to FIG82, the first matching functional unit, the second matching functional unit, the third matching functional unit, the fourth matching functional unit, the fifth matching functional unit, the sixth matching functional unit, the seventh matching functional unit, and the eighth matching functional unit are two-port networks, each including two ports Port1 and Port2, _V1 is the total voltage between Port1 and reference point 1, _I1 is the total current of Port1, _V2 is the total voltage between Port2 and reference point 2, and _I2 is the total current of Port2. The relationship between the voltage and current between the matching functional units Port1 and Port2 is represented by the admittance matrix [Y], and the admittance matrix [Y] of the first to eighth matching functional units is:

In the filter circuit 1, the first matching functional unit 3001A and the fourth matching functional unit 3004A are composed of elements whose imaginary part of admittance is equal to zero, and the imaginary part of _Y11 in the admittance matrix [Y] of the first matching functional unit 3001A and the fourth matching functional unit 3004A is equal to zero.

In the filter circuit 1, the second matching functional unit 3002A and the third matching functional unit 3003A are composed of elements whose imaginary part of admittance is greater than zero, and the imaginary part of _Y11 in the admittance matrix [Y] of the second matching functional unit 3002A and the third matching functional unit 3003A is greater than zero.

In the filter circuit 1, the sixth matching functional unit 3006A is composed of elements whose imaginary part of admittance is less than zero, and the fifth matching functional unit 3005A is composed of elements whose imaginary part of admittance is greater than zero. The imaginary part of _Y11 in the admittance matrix [Y] of the sixth matching functional unit 3006A is less than zero, and the imaginary part of _Y11 in the admittance matrix [Y] of the fifth matching functional unit 3005A is greater than zero.

In the filter circuit 1, the eighth matching functional unit 3008A is composed of elements whose imaginary part of admittance is less than zero, and the seventh matching functional unit 3007A is composed of elements whose imaginary part of admittance is greater than zero. The imaginary part of _Y11 in the admittance matrix [Y] of the eighth matching functional unit 3008A is less than zero, and the imaginary part of _Y11 in the admittance matrix [Y] of the seventh matching functional unit 3007A is greater than zero.

The configuration forms, properties and parameters of the first to eighth matching functional units can be configured in a diversified manner, thereby achieving flexible deployment of the number and positions of transmission zero points of the filtering circuit, so that the filtering circuit disclosed in the present application has the advantage of being able to customize the circuit's out-of-band suppression performance and selection characteristic response as required.

Fig. 83 is a schematic diagram of the structure of the first band-stop functional unit 2001A of the filter circuit 1 according to Embodiment VIII. Referring to Fig. 83, the first band-stop functional unit 2001A in the filter circuit 1 comprises a first element 5001 whose imaginary part of admittance is greater than zero and a second element 5002 whose imaginary part of admittance is less than zero, and the first element 5001 whose imaginary part of admittance is greater than zero and the second element 5002 whose imaginary part of admittance is less than zero are connected in parallel.

Fig. 84 is a schematic diagram of the structure of the second band-stop functional unit 2002A of the filter circuit 1 according to Embodiment VIII. Referring to Fig. 84, the second band-stop functional unit 2002A in the filter circuit 1 comprises a third element 5003 whose imaginary part of admittance is greater than zero, a fourth element 5004 whose imaginary part of admittance is less than zero, and a potential terminal 7001. The third element 5003 whose imaginary part of admittance is greater than zero, the fourth element 5004 whose imaginary part of admittance is less than zero, and the potential terminal 7001 are connected in series. The potential terminal 7001 is at the same potential as the reference ground.

The first element 5001, the second element 5002, the third element 5003, and the fourth element 5004 are all two-port elements. FIG85 is a schematic diagram of a two-port network of elements. Referring to FIG85, the element includes two ports Port3 and Port4, _V1 is the total voltage between Port3 and reference point 3, _I1 is the total current of Port3, _V2 is the total voltage between Port4 and reference point 4, and _I2 is the total current of Port4. The relationship between the voltage and current between Port3 and Port4 is represented by the admittance matrix [Y], then the first The admittance matrix [Y] of the element 5001, the second element 5002, the third element 5003, and the fourth element 5004 is:

The imaginary part of the admittance of the first element 5001 is greater than zero, and the imaginary part of Y ₁₁ in the admittance matrix [Y] of the first element 5001 is greater than zero. The imaginary part of the admittance of the second element 5002 is less than zero, and the imaginary part of Y ₁₁ in the admittance matrix [Y] of the second element 5002 is less than zero. The imaginary part of the admittance of the third element 5003 is greater than zero, and the imaginary part of Y ₁₁ in the admittance matrix [Y] of the third element 5003 is greater than zero. The imaginary part of the admittance of the fourth element 5004 is less than zero, and the imaginary part of Y ₁₁ in the admittance matrix [Y] of the fourth element 5004 is less than zero.

Fig. 86 is a transmission characteristic diagram of the first band-stop functional unit 2001A of the filter circuit 1 according to Embodiment VIII. Referring to Fig. 86, when the signal is transmitted through the first band-stop functional unit 2001A, at the frequency _f0 , the energy of the signal passing through the band-stop functional unit reaches a minimum value, which is the attenuation pole of the transmission characteristic of the band-stop functional unit.

The configuration of the third band-stop functional unit 2003A in the filter circuit 1 is the same as that of the second band-stop functional unit 2002A in the filter circuit 1 in Implementation VIII.

FIG87 is a top view of the structure of the filter circuit 1 according to Embodiment VIII. FIG88 is a stereoscopic view of the structure of the filter circuit 1 according to Embodiment VIII. Referring to FIG87 and FIG88, the first input-output electrode 1001, the second input-output electrode 1002, the first band-stop function unit 2001A, the second band-stop function unit 2002A, the third band-stop function unit 2003A, the first matching function unit 3001A, the second matching function unit 3002A, the third matching function unit 3003A, the fourth matching function unit 3004A, the fifth matching function unit 3005A, the sixth matching function unit 3006A, the seventh matching function unit 3007A, the eighth matching function unit 3008A, the first potential end 4001, and the second potential end 4002 of the filter circuit 1 are formed on a dielectric 6001, and the dielectric 6001 can be composed of one or more dielectric materials such as gallium arsenide, silicon carbide, silicon nitride, aluminum nitride, aluminum oxide, glass, and silicon oxide.

The first matching functional unit 3001A is formed as a metallized microstrip line, and the imaginary part of its admittance is zero. One end of the first matching functional unit 3001A is connected to the first input-output electrode 1001, and the other end of the first matching functional unit 3001A is connected to the second matching functional unit 3002A. The first input-output electrode 1001 is formed as a metallized electrode. The second matching functional unit 3002A is formed as two metallized electrodes facing each other on different dielectric planes, and the imaginary part of its admittance is greater than zero. The second matching functional unit 3002A is connected to the first band-stop functional unit 2001A. The first band-stop functional unit 2001A is formed by three metallized electrodes and a metallized spiral coil structure connected in parallel, and the two metallized electrodes are respectively connected to the two ends of the metallized spiral coil. Another metallized electrode is arranged below the two metallized electrodes connected to the metallized spiral coil structure, and partially overlaps with the two metallized electrodes above in the vertical direction. The imaginary part of the admittance of the metallized spiral coil structure is less than zero, and the imaginary part of the admittance of the structure composed of three metallized electrodes is greater than zero. The fifth matching functional unit 3005A is formed by coupling two opposite metallized electrodes on different dielectric planes, and the imaginary part of its admittance is greater than zero. The second matching functional unit 3002A is connected to one electrode of the fifth matching functional unit 3005A, and the other electrode of the fifth matching functional unit 3005A is connected to the second band-stop functional unit 2002A. The second band-stop functional unit 2002A is formed by two mutually facing metallized electrodes on different dielectric planes, a metallized spiral grounding coil structure and a reference ground in series, and the imaginary part of the admittance of the structure composed of the two mutually facing metallized electrodes is greater than zero. The metallized spiral grounding coil structure is composed of a metallized trace arranged around, a grounding electrode in the center, and a metallized through hole connected to the grounding electrode and penetrating a dielectric substrate, and the metallized through hole is connected to the reference ground GND below the substrate. The imaginary part of the admittance of the metallized spiral grounding coil structure is less than zero. The second band-stop functional unit 2002A is connected to one end of the sixth matching functional unit 3006A. The sixth matching functional unit 3006A is composed of a metallized spiral coil structure, and the imaginary part of its admittance is less than zero. The other end of the sixth matching functional unit 3006A is connected to the first potential terminal 4001. The first potential terminal 4001 is composed of a grounding electrode located at the center of the spiral coil of the matching functional unit 3006A and a metallized through hole that penetrates the dielectric substrate and is connected to the grounding electrode, and is used to connect to the reference ground GND below the substrate. The third matching functional unit 3003A is connected to the first band-stop functional unit 2001A. The third matching functional unit 3003A is formed as two metallized electrodes facing each other on different dielectric planes, and the imaginary part of its admittance is greater than zero. The seventh matching functional unit 3007A is formed by coupling two opposite metallized electrodes on different dielectric planes, and the imaginary part of its admittance is greater than zero. The third matching functional unit 3003A is connected to an electrode of the seventh matching functional unit 3007A. Another electrode of the unit 3007A is connected to the third band-stop functional unit 2003A. The third band-stop functional unit 2003A is formed by two mutually facing metallized electrodes on different dielectric planes, a metallized spiral grounding coil structure and a reference ground in series, and the imaginary part of the admittance of the structure formed by the two mutually facing metallized electrodes is greater than zero. The metallized spiral grounding coil structure is composed of a metallized routing arranged around, a grounding electrode in the center and a metallized through hole penetrating the dielectric substrate connected to the grounding electrode, and the metallized through hole is connected to the reference ground GND below the substrate. The imaginary part of the admittance of the metallized spiral grounding coil structure is less than zero. The third band-stop functional unit 2003A is connected to one end of the eighth matching functional unit 3008A, and the eighth matching functional unit 3008A is composed of a metallized spiral coil structure, and the imaginary part of its admittance is less than zero. The other end of the eighth matching functional unit 3008A is connected to the second potential terminal 4002. The second potential end 4002 is composed of a ground electrode located at the center of the spiral coil of the matching functional unit 3008A and a metallized through hole connected to the ground electrode and penetrating the dielectric substrate, and is used to connect to the reference ground GND below the substrate. The fourth matching functional unit 3004A is formed as a metallized microstrip line, and the imaginary part of its admittance is zero. One end of the fourth matching functional unit 3004A is connected to the second input-output electrode 1002, and the other end is connected to the third matching functional unit 3003A. The second input-output electrode 1002 is formed as a metallized electrode. The structures of the first input-output electrode 1001, the second input-output electrode 1002, the first band-stop functional unit 2001A, the second band-stop functional unit 2002A, the third band-stop functional unit 2003A, the first matching functional unit 3001A, the second matching functional unit 3002A, the third matching functional unit 3003A, the fourth matching functional unit 3004A, the fifth matching functional unit 3005A, the sixth matching functional unit 3006A, the seventh matching functional unit 3007A, the eighth matching functional unit 3008A, the first potential end 4001, and the second potential end 4002 can be composed of one or more metallized materials such as Ag, Au, and Cu.

The filter circuit 1 utilizes the first to third band-stop functional units as the main structure of the circuit, and through the coordinated configuration with the first to eighth matching functional units around the band-stop functional units, realizes the multi-transmission zero point characteristics of the frequency response of the filter circuit when the number of main functional units is equivalent to the number of main functional units in the low-order bandpass filter and there is no need to configure additional resonator structures, thereby improving the out-of-band suppression performance of the filter circuit, and making the filter circuit have the advantages of miniaturization and high frequency selection characteristics.

FIG89 is a graph showing the insertion loss and return loss characteristics of the filter circuit 1 of Embodiment VIII. Referring to FIG89 , the filter circuit 1 can generate five different transmission zeros TZ1, TZ2, TZ3, TZ4 and TZ5 outside the passband. Among them, TZ1 generated by the second band-stop functional unit 2002A and TZ2 generated by the third band-stop functional unit 2003A are located on the left side of the passband, which improves the low-frequency out-of-band suppression performance of the filter circuit 1. TZ3 generated by the first band-stop functional unit 2001A, and TZ4 and TZ5 generated by loading the matching functional unit are located on the right side of the passband, which improves the high-frequency out-of-band suppression performance of the filter circuit 1.

The above describes the implementation VIII of the present application, but the present application is not necessarily limited to the above implementation VIII, and various changes can be made without departing from the scope of the subject matter. For example, the second matching function unit 3002A and the third matching function unit 3003A can also be composed of elements whose imaginary part of admittance is equal to zero.

The sixth matching functional unit may also be composed of an element whose imaginary part of admittance is greater than zero, and in this case, the fifth matching functional unit is composed of an element whose imaginary part of admittance is less than zero. In addition, the eighth matching functional unit may also be composed of an element whose imaginary part of admittance is greater than zero, and in this case, the seventh matching functional unit is composed of an element whose imaginary part of admittance is less than zero. In addition, the configuration of the first band-stop functional unit 2001A may also be the same as the second band-stop functional unit 2002A of the filter circuit 1 mentioned in Implementation VIII. In addition, the configuration of the second band-stop functional unit 2002A or the third band-stop functional unit 2003A may also be the same as the first band-stop functional unit 2001A mentioned in the filter circuit 1 of Implementation VIII.

The filter circuit 2 of implementation mode IX of the present application is described below.

The difference between the filter circuit 2 proposed in Implementation IX and the filter circuit 1 proposed in one implementation is that the structures of the second band-stop function unit, the first matching function unit, and the fourth matching function unit are different.

FIG90 is a circuit diagram of the filter circuit 2 according to Embodiment IX. Referring to FIG90 , the filter circuit 2 includes: a first input-output electrode 1001, a second input-output electrode 1002, a first band-stop function unit 2001B, a second band-stop function unit 2002B, a third band-stop function unit 2003B, a first matching function unit 3001B, a second matching function unit 3002B, a third matching function unit 3003B, a fourth matching function unit 3004B, a fifth matching function unit 3005B, a sixth matching function unit 3006B, a seventh matching function unit 3007B, an eighth matching function unit 3008B, a first potential terminal 4001, and a second potential terminal 4002. The first input-output electrode 1001 is connected to one end of the first matching function unit 3001B, and the first The other end of the matching functional unit 3001B is simultaneously connected to one end of the second matching functional unit 3002B and one end of the fifth matching functional unit 3005B, the other end of the second matching functional unit 3002B is connected to one end of the first band-stop functional unit 2001B, the other end of the first band-stop functional unit 2001B is connected to one end of the third matching functional unit 3003B, the other end of the third matching functional unit 3003B is simultaneously connected to one end of the fourth matching functional unit 3004B and one end of the seventh matching functional unit 3007B, the other end of the fourth matching functional unit 3004B is connected to the second input-output electrode 1 002, the other end of the fifth matching functional unit 3005B is connected to one end of the second band-stop functional unit 2002B, the other end of the second band-stop functional unit 2002B is connected to one end of the sixth matching functional unit 3006B, the other end of the sixth matching functional unit 3006B is connected to the first potential end 4001, the other end of the seventh matching functional unit 3007B is connected to one end of the third band-stop functional unit 2003B, the other end of the third band-stop functional unit 2003B is connected to one end of the eighth matching functional unit 3008B, and the other end of the eighth matching functional unit 3008B is connected to the second potential end 4002. The first potential end 4001 and the second potential end 4002 are at the same potential as the reference ground. The band-stop functional unit 2001B, the band-stop functional unit 2002B, and the band-stop functional unit 2003B are two-port networks with attenuation poles in their transmission characteristics. The first matching functional unit 3001B to the eighth matching functional unit 3008B are two-port networks. When the first input-output electrode 1001 is used to receive an input signal, the second input-output electrode 1002 is used to provide an output signal, or when the first input-output electrode 1001 provides an output signal, the second input-output electrode 1002 is used to receive an input signal.

In the filter circuit 2, the first matching functional unit 3001B, the second matching functional unit 3002B, the third matching functional unit 3003B, and the fourth matching functional unit 3004B are composed of elements whose imaginary part of admittance is greater than zero, and the imaginary part of _Y11 in the admittance matrix [Y] of the first matching functional unit 3001B, the second matching functional unit 3002B, the third matching functional unit 3003B, and the fourth matching functional unit 3004B is greater than zero.

In the filtering circuit 2, the sixth matching functional unit 3006B is composed of elements whose imaginary part of admittance is less than zero, and the fifth matching functional unit 3005B is composed of elements whose imaginary part of admittance is greater than zero. The imaginary part of _Y11 in the admittance matrix [Y] of the sixth matching functional unit 3006B is less than zero, and the imaginary part of _Y11 in the admittance matrix [Y] of the fifth matching functional unit 3005B is greater than zero.

In the filtering circuit 2, the eighth matching functional unit 3008B is composed of elements whose imaginary part of admittance is less than zero, and the seventh matching functional unit 3007B is composed of elements whose imaginary part of admittance is greater than zero. The imaginary part of _Y11 in the admittance matrix [Y] of the eighth matching functional unit 3008B is less than zero, and the imaginary part of _Y11 in the admittance matrix [Y] of the seventh matching functional unit 3007B is greater than zero.

The filter circuit 2 can configure the structure, properties and parameters of the first to eighth matching functional units in a diversified manner, so as to realize the flexible deployment of the number and position of the transmission zero points of the filter circuit, so that the filter circuit disclosed in the present application has the advantage of being able to customize the circuit out-of-band suppression performance and selection characteristic response according to requirements.

The first band-stop function unit 2001B of the filter circuit 2 is constructed in the same manner as the first band-stop function unit 2001A of the filter circuit 1 in one embodiment. The second band-stop function unit 2002B of the filter circuit 2 is constructed in the same manner as the first band-stop function unit 2001A of the filter circuit 1 in one embodiment. The third band-stop function unit 2003B of the filter circuit 2 is constructed in the same manner as the second band-stop function unit 2002A of the filter circuit 1 in one embodiment.

Fig. 91 is a top view of the structure of the filter circuit 2 according to Embodiment IX. Fig. 92 is a stereoscopic view of the structure of the filter circuit 2 according to Embodiment IX. Referring to Fig. 91 to Fig. 92, the first input-output electrode 1001, the second input-output electrode 1002, the first band-stop function unit 2001B, the second band-stop function unit 2002B, the third band-stop function unit 2003B, the first matching function unit 3001B, the second matching function unit 3002B, the third matching function unit 3003B, the fourth matching function unit 3004B, the fifth matching function unit 3005B, the sixth matching function unit 3006B, the seventh matching function unit 3007B, the eighth matching function unit 3008B, the first potential end 4001, and the second potential end 4002 of the filter circuit 2 are formed on a dielectric 6002, and the dielectric 6002 can be composed of one or more dielectric materials such as gallium arsenide, silicon carbide, silicon nitride, aluminum nitride, aluminum oxide, glass, and silicon oxide.

The first matching functional unit 3001B is formed as two metallized electrodes facing each other on different dielectric planes, and the imaginary part of the admittance is greater than zero. One electrode of the first matching functional unit 3001B is connected to the first input-output electrode 1001, and the other electrode is connected to the second matching functional unit 3002B. The first input-output electrode 1001 is formed as a metallized electrode. The second matching functional unit 3002B is formed as two metallized electrodes facing each other on different dielectric planes. The first band-stop function unit 2001B is formed by connecting three metallized electrodes and a metallized spiral coil structure in parallel, wherein two metallized electrodes are connected to both ends of the metallized spiral coil respectively, and another metallized electrode is arranged below the two metallized electrodes connected to the metallized spiral coil structure, and partially overlaps with the two metallized electrodes above in the vertical direction. The imaginary part of the admittance of the metallized spiral coil structure is less than zero, and the imaginary part of the admittance of the structure formed by the three metallized electrodes is greater than zero. The fifth matching function unit 3005B is formed by coupling two opposite metallized electrodes on different dielectric planes, and the imaginary part of its admittance is greater than zero. The second matching function unit 3002B is connected to one electrode of the fifth matching function unit 3005B, and the other electrode of the fifth matching function unit 3005B is connected to the second band-stop function unit 2002B. The second band-stop function unit 2002B is formed by two mutually facing metallized electrodes and metallized spiral coil structures on different dielectric planes in parallel, and the imaginary part of the admittance of the structure formed by the two mutually facing metallized electrodes is greater than zero. The metallized spiral coil structure is formed by a metallized microstrip line arranged in a circle, and the two ends of the spiral coil structure are respectively connected to the two mutually facing metallized electrodes. The imaginary part of the admittance of the metallized spiral coil structure is less than zero. A metallized electrode of the second band-stop function unit 2002B is connected to one end of the sixth matching function unit 3006B, and the sixth matching function unit 3006B is composed of a metallized spiral coil structure, and the imaginary part of its admittance is less than zero. The other end of the sixth matching function unit 3006B is connected to the first potential end 4001. The first potential end 4001 is composed of a ground electrode located at the center of the spiral coil of the sixth matching function unit 3006B and a metallized through hole penetrating the dielectric substrate connected to the ground electrode, and is used to connect to the reference ground GND below the substrate. The third matching functional unit 3003B is connected to the first band-stop functional unit 2001B. The third matching functional unit 3003B is formed as two metallized electrodes facing each other on different dielectric planes, and the imaginary part of its admittance is greater than zero. The seventh matching functional unit 3007B is formed by coupling two opposite metallized electrodes on different dielectric planes, and the imaginary part of its admittance is greater than zero. The third matching functional unit 3003B is connected to one electrode of the seventh matching functional unit 3007B, and the other electrode of the seventh matching functional unit 3007B is connected to the third band-stop functional unit 2003B. The third band-stop functional unit 2003B is formed by two metallized electrodes facing each other on different dielectric planes, a metallized spiral grounding coil structure and a reference ground in series, and the imaginary part of the admittance of the structure formed by the two metallized electrodes facing each other is greater than zero. The metallized spiral grounding coil structure is composed of a metallized microstrip line arranged around, a grounding electrode at the center, and a metallized through hole connected to the grounding electrode and penetrating the dielectric substrate, and the metallized through hole is connected to the reference ground GND below the substrate. The imaginary part of the admittance of the metallized spiral grounding coil structure is less than zero. The third band-stop functional unit 2003B is connected to one end of the eighth matching functional unit 3008B, and the eighth matching functional unit 3008B is composed of a metallized spiral coil structure, and the imaginary part of its admittance is less than zero. The other end of the eighth matching functional unit 3008B is connected to the second potential end 4002. The second potential end 4002 is composed of a grounding electrode located at the center of the spiral coil of the eighth matching functional unit 3008B and a metallized through hole connected to the grounding electrode and penetrating the dielectric substrate, and is used to connect to the reference ground GND below the substrate. The fourth matching functional unit 3004B is formed as two metallized electrodes facing each other on different dielectric planes, and the imaginary part of its admittance is greater than zero. One end of the fourth matching functional unit 3004B is connected to the second input-output electrode 1002, and the other end of the fourth matching functional unit 3004B is connected to the third matching functional unit 3003B. The second input-output electrode 1002 is formed as a metallized electrode. The structures of the first input-output electrode 1001, the second input-output electrode 1002, the first band-stop functional unit 2001B, the second band-stop functional unit 2002B, the third band-stop functional unit 2003B, the first matching functional unit 3001B, the second matching functional unit 3002B, the third matching functional unit 3003B, the fourth matching functional unit 3004B, the fifth matching functional unit 3005B, the sixth matching functional unit 3006B, the seventh matching functional unit 3007B, the eighth matching functional unit 3008B, the first potential end 4001, and the second potential end 4002 can be composed of one or more metallized materials such as Ag, Au, and Cu.

The difference between the filter circuit 2 in this embodiment and the filter circuit 1 in one embodiment is that the configuration of the second band-stop functional unit, the first matching functional unit, and the fourth matching functional unit has changed. The second band-stop functional unit is changed to be composed of an element whose imaginary part of the admittance is greater than zero and an element whose imaginary part of the admittance is less than zero connected in parallel, and the first matching functional unit and the fourth matching functional unit are changed to be composed of an element whose imaginary part of the admittance is greater than zero, which can improve the filter circuit's ability to suppress low-frequency out-of-band signals. It is explained that the filter circuit proposed in this application has the ability to achieve flexible deployment of the number and position of transmission zero points of the filter circuit by configuring the properties and parameters of the functional units constituting the circuit in a diversified manner, so that the filter circuit disclosed in this application has the ability to adjust the circuit's out-of-band suppression performance and select characteristic response according to needs. Advantages of custom configuration.

The filter circuit 2 utilizes the first to third band-stop functional units as the main structure of the circuit, and through the coordinated configuration with the first to eighth matching functional units around the band-stop functional units, realizes the multi-transmission zero point characteristics of the filter circuit frequency response when the number of main functional units is equivalent to the number of main functional units in the low-order bandpass filter and there is no need to configure additional resonator structures, thereby improving the out-of-band suppression performance of the filter circuit and making the filter circuit have the advantages of miniaturization and high frequency selection characteristics.

FIG93 is a characteristic diagram of insertion loss and return loss of the filter circuit 2 of implementation mode IX. Referring to FIG93 , the filter circuit 2 can generate 5 different transmission zeros TZ1, TZ2, TZ3, TZ4 and TZ5 outside the passband. Among them, TZ1 generated by the second band-stop functional unit 2002B and TZ2 generated by the third band-stop functional unit 2003B are located on the left side of the passband, which improves the low-frequency out-of-band suppression performance of the filter circuit 2. The first matching functional unit and the fourth matching functional unit improve the low-frequency out-of-band suppression performance of the filter circuit 2. TZ3 generated by the first band-stop functional unit 2001B, and TZ4 and TZ5 generated by loading the matching functional unit are located on the right side of the passband, which improves the high-frequency out-of-band suppression performance of the filter circuit 2.

The filter circuit 3 of implementation mode X of the present application is described below.

The filter circuit 3 of Embodiment X is different from the filter circuit 2 of Embodiment IX in that the fifth matching function unit, the sixth matching function unit, the seventh matching function unit, and the eighth matching function unit are configured differently.

94 is a circuit diagram of the filter circuit 3 according to Embodiment X. Referring to FIG94 , the filter circuit 3 includes a first input-output electrode 1001, a second input-output electrode 1002, a first band-stop functional unit 2001C, a second band-stop functional unit 2002C, a third band-stop functional unit 2003C, a first matching functional unit 3001C, a second matching functional unit 3002C, a third matching functional unit 3003C, a fourth matching functional unit 3004C, a fifth matching functional unit 3005C, a sixth matching functional unit 3006C, a seventh matching functional unit 3007C, an eighth matching functional unit 3008C, a first potential terminal 4001, and a second potential terminal 4002. The first input-output electrode 1001 is connected to one end of the first matching functional unit 3001C, the other end of the first matching functional unit 3001C is simultaneously connected to one end of the second matching functional unit 3002C and one end of the fifth matching functional unit 3005C, the other end of the second matching functional unit 3002C is connected to one end of the first band-stop functional unit 2001C, the other end of the first band-stop functional unit 2001C is connected to one end of the third matching functional unit 3003C, the other end of the third matching functional unit 3003C is simultaneously connected to one end of the fourth matching functional unit 3004C and one end of the seventh matching functional unit 3007C, the fourth matching functional unit 300 The other end of the fifth matching functional unit 3005C is connected to the second input-output electrode 1002, the other end of the fifth matching functional unit 3005C is connected to one end of the second band-stop functional unit 2002C, the other end of the second band-stop functional unit 2002C is connected to one end of the sixth matching functional unit 3006C, the other end of the sixth matching functional unit 3006C is connected to the first potential end 4001, the other end of the seventh matching functional unit 3007C is connected to one end of the third band-stop functional unit 2003C, the other end of the third band-stop functional unit 2003C is connected to one end of the eighth matching functional unit 3008C, and the other end of the eighth matching functional unit 3008C is connected to the second potential end 4002. The first potential end 4001 and the second potential end 4002 are at the same potential as the reference ground. The first band-stop functional unit 2001C, the second band-stop functional unit 2002C, and the third band-stop functional unit 2003C are two-port networks with attenuation poles in their transmission characteristics. The first matching functional unit 3001C to the eighth matching functional unit 3008C are two-port networks. When the first input-output electrode 1001 is used to receive an input signal, the second input-output electrode 1002 is used to provide an output signal; or, when the first input-output electrode 1001 provides an output signal, the second input-output electrode 1002 is used to receive an input signal.

The first matching functional unit 3001C, the second matching functional unit 3002C, the third matching functional unit 3003C and the fourth matching functional unit 3004C in the filtering circuit 2 are composed of elements whose imaginary part of admittance is greater than zero, and the imaginary part of _Y11 in the admittance matrix [Y] of the first matching functional unit 3001C, the second matching functional unit 3002C, the third matching functional unit 3003C and the fourth matching functional unit 3004C is greater than zero.

The sixth matching functional unit 3006C in the filtering circuit 2 is composed of a two-port element whose imaginary part of admittance is greater than zero and a two-port element whose imaginary part of admittance is less than zero connected in series, the fifth matching functional unit 3005C is composed of an element whose imaginary part of admittance is equal to zero, the imaginary part of _Y11 in the admittance matrix [Y] of the two-port element whose imaginary part of admittance is less than zero in the sixth matching functional unit 3006C is less than zero, the imaginary part of _Y11 in the admittance matrix [Y] of the two-port element whose imaginary part of admittance is greater than zero in the sixth matching functional unit 3006C is greater than zero, and the imaginary part of _Y11 in the admittance matrix [Y] of the fifth matching functional unit 3005C is equal to zero.

The eighth matching functional unit 3008C in the filtering circuit 2 is composed of a two-port element whose imaginary part of admittance is greater than zero and a two-port element whose imaginary part of admittance is less than zero connected in series, the seventh matching functional unit 3007C is composed of an element whose imaginary part of admittance is equal to zero, the imaginary part of _{Y11 in the admittance matrix [Y] of the two-port element whose imaginary part of admittance is less than zero in the eighth matching functional unit 3008C is less than zero, the imaginary part of Y11} _in the admittance matrix [Y] of the two-port element whose imaginary part of admittance is greater than zero in the eighth matching functional unit 3008C is greater than zero, and the imaginary part of _Y11 in the admittance matrix [Y] of the seventh matching functional unit 3007C is equal to zero.

The first band-stop function unit 2001C of the filter circuit 3 is constructed in the same manner as the first band-stop function unit 2001A of the filter circuit 1 in one embodiment. The second band-stop function unit 2002C of the filter circuit 3 is constructed in the same manner as the first band-stop function unit 2001A of the filter circuit 1 in one embodiment. The third band-stop function unit 2003C of the filter circuit 3 is constructed in the same manner as the second band-stop function unit 2002A of the filter circuit 1 in one embodiment.

Fig. 95 is a top view of the structure of the filter circuit 3 of embodiment X. Fig. 96 is a stereoscopic view of the structure of the filter circuit 3 of embodiment X. Referring to Fig. 95 to Fig. 96, the first input-output electrode 1001, the second input-output electrode 1002, the first band-stop function unit 2001C, the second band-stop function unit 2002C, the third band-stop function unit 2003C, the first matching function unit 3001C, the second matching function unit 3002C, the third matching function unit 3003C, the fourth matching function unit 3004C, the fifth matching function unit 3005C, the sixth matching function unit 3006C, the seventh matching function unit 3007C, the eighth matching function unit 3008C, the first potential end 4001, and the second potential end 4002 of the filter circuit 3 are formed on a dielectric 603, and the dielectric 603 can be composed of one or more dielectric materials such as gallium arsenide, silicon carbide, silicon nitride, aluminum nitride, aluminum oxide, glass, and silicon oxide.

The first matching functional unit 3001C is formed as two mutually facing metallized electrodes on different dielectric planes, and the imaginary part of the admittance thereof is greater than zero. One electrode of the first matching functional unit 3001C is connected to the first input-output electrode 1001, and the other electrode is connected to the second matching functional unit 3002C. The first input-output electrode 1001 is formed as a metallized electrode. The second matching functional unit 3002C is formed as two mutually facing metallized electrodes on different dielectric planes, and the imaginary part of the admittance thereof is greater than zero. The second matching functional unit 3002C is connected to the first band-stop functional unit 2001C. The first band-stop functional unit 2001C is formed by three metallized electrodes and a metallized spiral coil structure connected in parallel, two metallized electrodes are respectively connected to the two ends of the metallized spiral coil, and another metallized electrode is arranged below the two metallized electrodes connected to the metallized spiral coil structure, and partially overlaps with the two metallized electrodes above in the vertical direction. The imaginary part of the admittance of the metallized spiral coil structure is less than zero, and the imaginary part of the admittance of the structure composed of three metallized electrodes is greater than zero. The fifth matching functional unit 3005C is composed of a metallized electrode. The second matching functional unit 3002B is connected to one end of the fifth matching functional unit 3005C, and the other end of the fifth matching functional unit 3005C is connected to the second band-stop functional unit 2002C. The second band-stop functional unit 2002C is formed by two metallized electrodes facing each other on different dielectric planes and a metallized spiral coil structure in parallel, and the imaginary part of the admittance of the structure composed of the two metallized electrodes facing each other is greater than zero. The metallized spiral coil structure is formed by a metallized microstrip line arranged in a surrounding manner, and the two ends of the spiral coil structure are respectively connected to two metallized electrodes facing each other. The imaginary part of the admittance of the metallized spiral coil structure is less than zero. A metallized electrode of the second band-stop functional unit 2002C is connected to one end of the sixth matching functional unit 3006C. The sixth matching functional unit 3006C is composed of two metallized electrodes facing each other on different dielectric planes and a metallized spiral coil structure connected in series. The imaginary part of the admittance of the structure composed of the two metallized electrodes facing each other is greater than zero, and the imaginary part of the admittance of the metallized spiral coil structure is less than zero. One end of the metallized spiral coil structure of the sixth matching functional unit 3006C is connected to a metallized electrode of the sixth matching functional unit 3006C, and the other end is connected to the first potential terminal 4001. The first potential terminal 4001 is composed of a ground electrode located at the center of the spiral coil of the sixth matching functional unit 3006C and a metallized through hole connected to the ground electrode and penetrating the dielectric substrate, and is used to connect to the reference ground GND below the substrate. The third matching functional unit 3003C is connected to the first band-stop functional unit 2001C. The third matching functional unit 3003C is formed as two metallized electrodes facing each other on different dielectric planes, and the imaginary part of the admittance thereof is greater than zero. The seventh matching functional unit 3007C is formed by one metallized electrode. The matching function unit 3003C is connected to one end of the seventh matching function unit 3007C, and the other end of the seventh matching function unit 3007C is connected to the third band-stop function unit 2003C. The third band-stop function unit 2003C is formed by two mutually facing metallized electrodes on different dielectric planes, a metallized spiral grounding coil structure and a reference ground in series, and the imaginary part of the admittance of the structure formed by the two mutually facing metallized electrodes is greater than zero. The metallized spiral grounding coil structure is composed of a metallized microstrip line arranged in a surrounding manner, a grounding electrode at the center, and a metallized through hole penetrating a dielectric substrate connected to the grounding electrode, and the metallized through hole is connected to the reference ground GND below the substrate. The imaginary part of the admittance of the metallized spiral grounding coil structure is less than zero. The third band-stop function unit 2003C is connected to one end of the eighth matching function unit 3008C. The eighth matching function unit 3008C is formed by two mutually facing metallized electrodes and a metallized spiral coil structure connected in series on different dielectric planes. The imaginary part of the admittance of the structure formed by the two mutually facing metallized electrodes is greater than zero, and the imaginary part of the admittance of the metallized spiral coil structure is less than zero. One end of the metallized spiral coil structure of the eighth matching function unit 3008C is connected to a metallized electrode of the eighth matching function unit 3008C, and the other end is connected to the second potential end 4002. The second potential end 4002 is formed by a ground electrode located at the center of the spiral coil of the matching function unit 3008C and a metallized through hole connected to the ground electrode and penetrating the dielectric substrate, and is used to connect to the reference ground GND below the substrate. The fourth matching function unit 3004C is formed by two mutually facing metallized electrodes on different dielectric planes, and the imaginary part of its admittance is greater than zero. One end of the fourth matching functional unit 3004C is connected to the second input-output electrode 1002, and the other end is connected to the third matching functional unit 3003C. The second input-output electrode 1002 is formed as a metallized electrode. The first input-output electrode 1001, the second input-output electrode 1002, the first band-stop functional unit 2001C, the second band-stop functional unit 2002C, the third band-stop functional unit 2003C, the first matching functional unit 3001C, the second matching functional unit 3002C, the third matching functional unit 3003C, the fourth matching functional unit 3004C, the fifth matching functional unit 3005C, the sixth matching functional unit 3006C, the seventh matching functional unit 3007C, the eighth matching functional unit 3008C, the first potential end 4001, and the second potential end 4002 may be formed of one or more metallized materials such as Ag, Au, and Cu.

The difference between the filter circuit 3 in this embodiment and the filter circuit 2 in one embodiment is that the configuration of the fifth matching function unit, the sixth matching function unit, the seventh matching function unit, and the eighth matching function unit is changed. The fifth matching function unit and the seventh matching function unit are changed to be composed of elements whose imaginary part of the admittance is equal to zero, and the sixth matching function unit and the eighth matching function unit are changed to be composed of the sixth matching function unit being composed of a two-port element whose imaginary part of the admittance is greater than zero and a two-port element whose imaginary part of the admittance is less than zero connected in series. It is explained that the filter circuit proposed in this application has the advantage of being able to flexibly deploy the number and position of the transmission zero points of the filter circuit by configuring the properties and parameters of the functional units constituting the circuit in a diversified manner, so that the filter circuit disclosed in this application has the advantage of being able to customize the circuit out-of-band suppression performance and selection characteristic response according to requirements.

The filter circuit 3 utilizes the first to third band-stop functional units as the main structure of the circuit, and through the coordinated configuration with the first to eighth matching functional units around the band-stop functional units, realizes the multi-transmission zero point characteristics of the filter circuit frequency response when the number of main functional units is equivalent to the number of main functional units in the low-order bandpass filter and there is no need to configure additional resonator structures, thereby improving the out-of-band suppression performance of the filter circuit, and making the filter circuit have the advantages of miniaturization and high frequency selection characteristics.

FIG97 is a graph showing the insertion loss and return loss characteristics of the filter circuit 3 of implementation mode X. Referring to FIG97 , the filter circuit 3 can generate five different transmission zeros TZ1, TZ2, TZ3, TZ4 and TZ5 outside the passband. Among them, TZ1 generated by the second band-stop function unit 2002C and TZ2 generated by the third band-stop function unit 2003C are located on the left side of the passband, which improves the low-frequency out-of-band suppression performance of the filter circuit 3. The first matching function unit and the fourth matching function unit improve the low-frequency out-of-band suppression performance of the filter circuit 3. TZ3 generated by the first band-stop function unit 2001C, and TZ4 and TZ5 generated by loading the matching function unit are located on the right side of the passband, which improves the high-frequency out-of-band suppression performance of the filter circuit 3.

It is clear from the above description that the present application can be implemented in various forms and modifications. Therefore, within the scope of the equivalents of the claims, the present application can be implemented in forms other than the best form described above.

In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and are not intended to be used in conjunction with the accompanying drawings. It indicates or implies that the device or element mentioned must have a specific orientation, be constructed and operate in a specific orientation, and therefore it should not be understood as limiting the present application.

In addition, the terms "first", "second", "third", "fourth", "fifth", and "sixth" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the feature. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined.

Claims

A stacked electronic device, comprising:

A multi-layer medium layer, wherein the multi-layer medium layer is formed by stacking a plurality of dielectric layers along a stacking direction;

a first pattern conductor, wherein the first pattern conductor is formed such that when viewed from the stacking direction, its projection on a plane perpendicular to the stacking direction is centered at a point and arranged around the point; the first pattern conductor is formed on the surface of the dielectric layer or between the dielectric layers;

at least two via conductors, the via conductors penetrating the dielectric layer along the stacking direction; the first pattern conductor is coupled to the via conductors;

A capacitive structure, wherein the capacitive structure is formed by coupling a plurality of metallized electrodes that are in a mutually facing relationship; the first pattern conductor is coupled to the capacitive structure through the via conductor; the first pattern conductor, the capacitive structure, the via conductor and the coupling path therebetween form a three-dimensional integrated closed loop in a three-dimensional space;

A projection of the first pattern conductor on a plane perpendicular to the stacking direction at least partially overlaps with a projection of a plurality of metallized electrodes of the capacitive structure on a plane perpendicular to the stacking direction.
According to the stacked electronic device according to claim 1, wherein the capacitive structure is arranged between the first pattern conductor and the mounting surface along the stacking direction, the mounting surface is the surface of a mounting carrier, the mounting carrier is a carrier for mounting or fixing the stacked electronic device, or is a carrier for mounting or fixing any electronic device composed of the stacked electronic device; the projection of the first pattern conductor on the mounting surface at least partially overlaps with the projection of a plurality of metallized electrodes of the capacitive structure that are in a facing relationship with each other on the mounting surface.
The stacked electronic device according to claim 1, wherein a plurality of metallized electrodes of the capacitive structure are formed on the surface of the dielectric layer or between the dielectric layers in a mutually facing relationship.
The stacked electronic device according to claim 1, wherein the capacitive structure is formed by three or more metallized electrodes that are in a facing relationship with each other.
The stacked electronic device according to claim 1, wherein the projection of the first pattern conductor on a plane perpendicular to the stacking direction is formed by extending a fold line around a point with the point as the center.
The stacked electronic device according to claim 1, wherein a projection of the first pattern conductor on a plane perpendicular to the stacking direction is formed by extending an arc around a point with a point as the center.
The stacked electronic device according to claim 1, wherein a projection of the first pattern conductor on a plane perpendicular to the stacking direction is formed by spirally extending around a point with the point as the center.
The stacked electronic device according to claim 1, wherein a projection of said first pattern conductor on a plane perpendicular to said stacking direction is formed in a combination of a spiral line and a zigzag line.
The stacked electronic device according to claim 1 further comprises a first external terminal and a second external terminal, wherein the first external terminal and the second external terminal are formed of a metallized material, and the first external terminal and the second external terminal are formed on the three-dimensionally integrated closed loop.
The stacked electronic device according to claim 1 further includes at least one second pattern conductor formed on the surface of the dielectric layer or between the dielectric layers, wherein the second pattern conductor is formed so that when viewed from the stacking direction, its projection on the plane perpendicular to the stacking direction is centered on a point and is arranged around the point; the second pattern conductor is coupled to the first pattern conductor through the via conductor, and the second pattern conductor is coupled to the capacitive structure; the second pattern conductor, the first pattern conductor, the capacitive structure, the via conductor and the coupling paths therebetween form a three-dimensional integrated closed loop in three-dimensional space.
The stacked electronic device according to claim 10, wherein the second pattern conductor is arranged between the first pattern conductor and the mounting surface along the stacking direction, the mounting surface is the surface of the mounting carrier, the mounting carrier is a carrier for mounting or fixing the stacked electronic device, or is a carrier for mounting or fixing any electronic device composed of the stacked electronic device; the projection of the first pattern conductor on the mounting surface is parallel to the plurality of capacitive structures. The projections of the metallized electrodes on the mounting surface at least partially overlap.
The stacked electronic device according to claim 10, wherein the projection of the second pattern conductor on a plane perpendicular to the stacking direction is formed by extending from a point by at least one of a straight line, a fold line, an arc line, and a spiral line.
An integrated filter comprises a first input-output terminal, a second input-output terminal, a first module, a second module, a third module, a first common terminal and a second common terminal; the first input-output terminal, the second input-output terminal, the first common terminal and the second common terminal are formed of metallized materials;

The first module comprises a first connection terminal, a first potential terminal, a first stacked electronic device, and at least one first additional capacitive structure; the first connection terminal is formed of a metallized material; the first stacked electronic device is a stacked electronic device according to any one of claims 1 to 12; the first additional capacitive structure is formed by coupling a plurality of metallized electrodes that are facing each other; the first additional capacitive structure is arranged on a coupling path between the first stacked electronic device and the first connection terminal, or the first additional capacitive structure is arranged on a coupling path between the first stacked electronic device and the first potential terminal;

The second module comprises a second connection terminal, a second potential terminal, a second stacked electronic device, and at least one second additional capacitive structure; the second connection terminal is formed of a metallized material; the second stacked electronic device is a stacked electronic device according to any one of claims 1 to 12; the second additional capacitive structure is formed by coupling a plurality of metallized electrodes facing each other; the second additional capacitive structure is arranged on a coupling path between the second stacked electronic device and the second connection terminal, or the second additional capacitive structure is arranged on a coupling path between the second stacked electronic device and the second potential terminal;

The third module comprises a third connection terminal, a fourth connection terminal, a third stacked electronic device, and at least one third additional capacitive structure; the third connection terminal and the fourth connection terminal are formed of metallized materials; the third stacked electronic device is a stacked electronic device according to any one of claims 1 to 12; the third additional capacitive structure is formed by coupling a plurality of metallized electrodes facing each other; the third additional capacitive structure is arranged on a coupling path between the third stacked electronic device and the third connection terminal, and/or the third additional capacitive structure is arranged on a coupling path between the third stacked electronic device and the fourth connection terminal;

The first connection end of the first module and the third connection end of the third module are coupled to the first common end, and the first common end is coupled to the first input-output end; the second connection end of the second module and the fourth connection end of the third module are coupled to the second common end, and the second common end is coupled to the second input-output end.
The integrated filter according to claim 13, wherein the first module further comprises at least one first additional inductive structure, wherein the first additional inductive structure is arranged on a coupling path between a first connection end of the first module and a first stacked electronic device of the first module; and/or,

The first additional inductive structure is arranged on a coupling path between a first connection end of the first module and a first additional capacitive structure of the first module; and/or,

The first additional inductive structure is arranged on a coupling path between the first stacked electronic device of the first module and the first additional capacitive structure of the first module; and/or,

The first additional inductive structure is arranged on a coupling path between a first potential end of the first module and a first additional capacitive structure of the first module; and/or,

The first additional inductive structure is arranged on a coupling path between a first potential end of the first module and a first stacked electronic device of the first module;

The second module further comprises at least one second additional inductive structure, wherein the second additional inductive structure is arranged on a coupling path between a second stacked electronic device of the second module and a second connection end of the second module; and/or,

The second additional inductive structure is arranged on a coupling path between a second connection end of the second module and a second additional capacitive structure of the second module; and/or,

The second additional inductive structure is arranged on a coupling path between the second stacked electronic device of the second module and the second additional capacitive structure of the second module; and/or,

The second additional inductive structure is arranged between the second potential end of the second module and the second additional inductive structure of the second module. Adding capacitive structures to the coupling paths; and/or,

The second additional inductive structure is arranged on a coupling path between a second potential end of the second module and a second stacked electronic device of the second module;

The first additional inductive structure and the second additional inductive structure are formed of metallized materials.
According to the integrated filter according to claim 14, the projection of the first additional inductive structure on the plane perpendicular to the stacking direction of the first stacked electronic device is formed by extending from a point by at least one of a straight line, a broken line, an arc line, and a spiral line; the first additional inductive structure is arranged between the first pattern conductor and the mounting surface of the first stacked electronic device along the stacking direction of the first stacked electronic device, and the mounting surface is the surface of the mounting carrier, and the mounting carrier is a carrier for mounting or fixing the integrated filter, or a carrier for mounting or fixing any electronic device composed of the integrated filter.
According to the integrated filter according to claim 14, the projection of the second additional inductive structure on the plane perpendicular to the stacking direction of the second stacked electronic device is formed by extending from a point by at least one of a straight line, a broken line, an arc line, and a spiral line; the second additional inductive structure is arranged between the first pattern conductor and the mounting surface of the second stacked electronic device along the stacking direction of the second stacked electronic device, and the mounting surface is the surface of the mounting carrier, and the mounting carrier is a carrier for mounting or fixing the integrated filter, or a carrier for mounting or fixing any electronic device composed of the integrated filter.
According to the integrated filter according to claim 14, the first additional inductive structure and the second additional inductive structure can be formed on the surface of the mounting carrier or inside the mounting carrier, and the mounting carrier is a carrier for mounting or fixing the integrated filter, or a carrier for mounting or fixing any electronic device composed of the integrated filter.
The integrated filter according to claim 13, wherein the first to third additional capacitive structures include fourth to sixth metallized electrodes, the fourth metallized electrode and the fifth metallized electrode are formed in different dielectric layers and face each other, and the fifth metallized electrode and the sixth metallized electrode are formed in different dielectric layers and face each other.
According to the integrated filter of claim 18, the overlapping parts of the projections of the fourth metallized planar electrode and the fifth metallized planar electrode on the mounting surface do not overlap with the overlapping parts of the projections of the fifth metallized planar electrode and the sixth metallized planar electrode on the mounting surface; the mounting surface is the surface of a mounting carrier, and the mounting carrier is a carrier for mounting or fixing the integrated filter, or a carrier for mounting or fixing any electronic device composed of the integrated filter.
The integrated filter according to claim 13, wherein the positional relationship among the first stacked electronic device, the second stacked electronic device, and the third stacked electronic device is configured as follows: a projection of the first pattern conductor of the third stacked electronic device on a mounting surface is sandwiched between a projection of the first pattern conductor of the first stacked electronic device on the mounting surface and a projection of the first pattern conductor of the second stacked electronic device on the mounting surface, the mounting surface being a surface of a mounting carrier, the mounting carrier being a carrier for mounting or fixing the integrated filter, or a carrier for mounting or fixing any electronic device composed of the integrated filter; or,

A projection of the first pattern conductor of the third stacked electronic device on a plane perpendicular to the stacking direction is sandwiched between a projection of the first pattern conductor of the first stacked electronic device on a plane perpendicular to the stacking direction and a projection of the first pattern conductor of the second stacked electronic device on a plane perpendicular to the stacking direction.
According to the integrated filter of claim 13, the projection of the first module on the mounting surface, the projection of the second module on the mounting surface and the projection of the third module on the mounting surface partially overlap, the mounting surface is the surface of the mounting carrier, and the mounting carrier is a carrier for mounting or fixing the integrated filter, or is a carrier for mounting or fixing any electronic device composed of the integrated filter.
The integrated filter according to claim 13, wherein the plurality of metallized electrodes of the first additional capacitive structure that are in a facing relationship with each other can be formed on the surface of a dielectric layer or between dielectric layers in the first stacked electronic device;

The second additional capacitive structure may have a plurality of metallized electrodes in a mutually facing relationship formed on the first The surface of a dielectric layer or between dielectric layers in a two-layer stacked electronic device;

The plurality of metallized electrodes of the third additional capacitive structure that are in facing relationship with each other may be formed on the surface of a dielectric layer or between dielectric layers in the third stacked electronic device.
The integrated filter according to claim 13, wherein a projection of the first additional capacitive structure on a plane perpendicular to the stacking direction of the first stacked electronic device at least partially overlaps with a projection of the first pattern conductor of the first stacked electronic device on a plane perpendicular to the stacking direction of the first stacked electronic device;

The projection of the second additional capacitive structure on a plane perpendicular to the stacking direction of the second stacked electronic device at least partially overlaps with the projection of the first pattern conductor of the second stacked electronic device on a plane perpendicular to the stacking direction of the second stacked electronic device;

A projection of the third additional capacitive structure on a plane perpendicular to the stacking direction of the third stacked electronic device at least partially overlaps with a projection of the first pattern conductor of the third stacked electronic device on a plane perpendicular to the stacking direction of the third stacked electronic device.
The integrated filter according to claim 13, further comprising at least one fourth additional capacitive structure; wherein the fourth additional capacitive structure is configured on a coupling path between the first input-output terminal and the first common terminal; and/or,

The fourth additional capacitive structure is configured on a coupling path between the second input-output terminal and the second common terminal;

The fourth additional capacitive structure is formed by coupling a plurality of metallized electrodes in a facing relationship with each other.
The integrated filter according to claim 24, wherein the fourth additional capacitive structure comprises seventh to ninth metallized electrodes, the seventh metallized electrode and the eighth metallized electrode are formed in different dielectric layers and face each other, and the eighth metallized electrode and the ninth metallized electrode are formed in different dielectric layers and face each other.
The integrated filter according to claim 14, wherein the first connection terminal is formed on a first stacked electronic device of the first module; or

The first connection end is coupled to the first stacked electronic device of the first module; or,

The first connection end is formed on a first additional capacitive structure of the first module; or,

The first connection end is coupled to a first additional capacitive structure of the first module; or,

The first connection end is formed on the first additional inductive structure of the first module; or,

The first connection end is coupled to a first additional inductive structure of the first module;

The first potential terminal is formed on the first stacked electronic device of the first module; or,

The first potential terminal is coupled to the first stacked electronic device of the first module; or,

The first potential terminal is formed on a first additional capacitive structure of the first module; or,

The first potential terminal is coupled to a first additional capacitive structure of the first module; or,

The first potential terminal is formed on a first additional inductive structure of the first module; or,

The first potential terminal is coupled to a first additional inductive structure of the first module;

The second connection terminal is formed on the second stacked electronic device of the second module; or,

The second connection end is coupled to the second stacked electronic device of the second module; or,

The second connection end is formed on a second additional capacitive structure of the second module; or,

The second connection terminal is coupled to a second additional capacitive structure of the second module; or,

The second connection end is formed on the second additional inductive structure of the second module; or,

The second connection end is coupled to a second additional inductive structure of the second module;

The second potential terminal is formed on the second stacked electronic device of the second module; or,

The second potential terminal is coupled to the second stacked electronic device of the second module; or,

The second potential terminal is formed on a second additional capacitive structure of the second module; or,

The second potential terminal is coupled to a second additional capacitive structure of the second module; or,

The second potential terminal is formed on a second additional inductive structure of the second module; or,

The second potential terminal is coupled to a second additional inductive structure of the second module;

The third connection terminal is formed on the third stacked electronic device of the third module; or,

The third connection terminal is coupled to the third stacked electronic device of the third module; or,

The third connection terminal is formed on the third additional capacitive structure of the third module; or,

The third connection terminal is coupled to the third additional capacitive structure of the third module;

The fourth connection terminal is formed on the third stacked electronic device of the third module; or,

The fourth connection terminal is coupled to the third stacked electronic device of the third module; or,

The fourth connection terminal is formed on the third additional capacitive structure of the third module; or,

The fourth connection terminal is coupled to the third additional capacitive structure of the third module.
The integrated filter according to claim 14, wherein the first connection terminal and the first stacked electronic device of the first module share the same metallized electrode; or

The first connection terminal and the first additional capacitive structure of the first module share the same metallized electrode; or,

The first connection end and the first additional inductive structure of the first module share a same metallized electrode;

The first potential end and the first stacked electronic device of the first module share the same metallized electrode; or,

The first potential terminal and the first additional capacitive structure of the first module share the same metallized electrode; or,

The first potential terminal and the first additional inductive structure of the first module share a same metallized electrode;

The second connection end and the second stacked electronic device of the second module share the same metallized electrode; or,

The second connection terminal and the second additional capacitive structure of the second module share the same metallized electrode; or,

The second connection end and the second additional inductive structure of the second module share a same metallized electrode;

The second potential end and the second stacked electronic device of the second module share the same metallized electrode; or,

The second potential terminal and the second additional capacitive structure of the second module share the same metallized electrode; or,

The second potential terminal and the second additional inductive structure of the second module share a same metallized electrode;

The third connection terminal and the third stacked electronic device of the third module share the same metallized electrode; or,

The third connection terminal and the third additional capacitive structure of the third module share the same metallized electrode;

The fourth connection terminal and the third stacked electronic device of the third module share the same metallized electrode; or,

The fourth connection terminal and the third additional capacitive structure of the third module share a same metallized electrode.
The integrated filter according to claim 13, wherein the first common terminal is formed on the first module, or the first common terminal is formed on the third module;

The second common terminal is formed on the second module, or the second common terminal is formed on the third module.
The integrated filter according to claim 13, wherein the first common terminal and the first connection terminal of the first module share the same metallized electrode; or, the first common terminal and the third connection terminal of the third module share the same metallized electrode;

The second common terminal and the second connection terminal of the second module share a same metallized electrode; or, the second common terminal and the fourth connection terminal of the third module share a same metallized electrode.
According to the integrated filter of claim 13, the first common terminal shares the same metallized electrode with the first connection terminal of the first module and the third connection terminal of the third module; the second common terminal shares the same metallized electrode with the second connection terminal of the second module and the fourth connection terminal of the third module.
According to the integrated filter of claim 24, the first common terminal shares the same metallized electrode with the first connection terminal of the first module, the third connection terminal of the third module, and the fourth additional capacitive structure; the second common terminal shares the same metallized electrode with the second connection terminal of the second module, the fourth connection terminal of the third module, and the fourth additional capacitive structure.
The integrated filter according to claim 13, wherein the first pattern conductor, capacitive structure, via conductor and coupling paths therebetween of the first stacked electronic device form a three-dimensional integrated closed loop in three-dimensional space on a plane perpendicular to the long side of the multilayer medium layer of the integrated filter, the first pattern conductor, capacitive structure, via conductor and coupling paths therebetween of the second stacked electronic device form a three-dimensional integrated closed loop in three-dimensional space on a plane perpendicular to the long side of the multilayer medium layer of the integrated filter, and the first pattern conductor, capacitive structure, via conductor and coupling paths therebetween of the third stacked electronic device form a three-dimensional integrated closed loop in three-dimensional space on a plane perpendicular to the long side of the multilayer medium layer of the integrated filter. The projections of the multi-layer medium layers of the integrated filter on the plane perpendicular to the long sides thereof at least partially overlap.
The integrated filter according to claim 14, further comprising at least one fifth additional capacitive structure; wherein the fifth additional capacitive structure is configured on a coupling path between the first input-output terminal and the first common terminal; and/or, the fifth additional capacitive structure is configured on a coupling path between the second input-output terminal and the second common terminal; the fifth additional capacitive structure is formed by coupling a plurality of metallized electrodes that are in a mutually facing relationship;

The first additional capacitive structure of the first module is configured on a coupling path between the first stacked electronic device and the first connection end, and the first additional inductive structure of the first module is configured on a coupling path between the first potential end of the first module and the first stacked electronic device of the first module;

The second additional capacitive structure of the second module is configured on the coupling path between the second stacked electronic device and the second connection end, and the second additional inductive structure of the second module is configured on the coupling path between the second potential end of the second module and the second stacked electronic device of the second module.
The integrated filter according to claim 14, further comprising at least one sixth additional capacitive structure; wherein the sixth additional capacitive structure is configured on a coupling path between the first input-output terminal and the first common terminal; and/or, the sixth additional capacitive structure is configured on a coupling path between the second input-output terminal and the second common terminal; the sixth additional capacitive structure is formed by coupling a plurality of metallized electrodes that are in a mutually facing relationship;

The first additional capacitive structure of the first module is configured on a coupling path between the first stacked electronic device and the first potential end, the first additional inductive structure of the first module is configured on a coupling path between the first additional capacitive structure of the first module and the first stacked electronic device of the first module, or the first additional inductive structure of the first module is configured on a coupling path between the first additional capacitive structure of the first module and the first potential end;

The second additional capacitive structure of the second module is configured on the coupling path between the second stacked electronic device and the second potential end, the second additional inductive structure of the second module is configured on the coupling path between the second additional capacitive structure of the second module and the second stacked electronic device of the second module, or the second additional inductive structure of the second module is configured on the coupling path between the second additional capacitive structure of the second module and the second potential end.
An electronic device comprising the stacked electronic device according to any one of claims 1 to 12 or the integrated filter according to any one of claims 13 to 34.
A filter circuit comprises: a first input-output electrode, a second input-output electrode, a first band-stop function unit, a second band-stop function unit, a third band-stop function unit, a first matching function unit, a second matching function unit, a third matching function unit, a fourth matching function unit, a fifth matching function unit, a sixth matching function unit, a seventh matching function unit, an eighth matching function unit, a first potential end, and a second potential end; wherein,

The first input-output electrode is connected to one end of the first matching functional unit, the other end of the first matching functional unit is simultaneously connected to one end of the second matching functional unit and one end of the fifth matching functional unit, the other end of the second matching functional unit is connected to one end of the first band-stop functional unit, the other end of the first band-stop functional unit is connected to one end of the third matching functional unit, the other end of the third matching functional unit is simultaneously connected to one end of the fourth matching functional unit and one end of the seventh matching functional unit, the other end of the fourth matching functional unit is connected to the second input-output electrode, the other end of the fifth matching functional unit is connected to one end of the second band-stop functional unit, the other end of the second band-stop functional unit is connected to one end of the sixth matching functional unit, the other end of the sixth matching functional unit is connected to the first potential end, the other end of the seventh matching functional unit is connected to one end of the third band-stop functional unit, the other end of the third band-stop functional unit is connected to one end of the eighth matching functional unit, and the other end of the eighth matching functional unit is connected to the second potential end;

The first to third band-stop functional units are all two-port networks with attenuation poles in their transmission characteristics;

The first to eighth matching functional units are all two-port networks.
The filter circuit according to claim 36, wherein the first potential terminal and the second potential terminal are at the same potential as the reference ground.
According to the filtering circuit according to claim 36, the first matching function unit, the second matching function unit, the third matching function unit, and the fourth matching function unit are composed of elements whose imaginary part of admittance is greater than zero, or are composed of elements whose imaginary part of admittance is equal to zero.
According to the filtering circuit of claim 36, the sixth matching functional unit is composed of elements whose imaginary part of admittance is greater than zero, and the fifth matching functional unit is composed of elements whose imaginary part of admittance is less than zero; or, the sixth matching functional unit is composed of elements whose imaginary part of admittance is less than zero, and the fifth matching functional unit is composed of elements whose imaginary part of admittance is greater than zero; or, the sixth matching functional unit is composed of elements whose imaginary part of admittance is greater than zero and elements whose imaginary part of admittance is less than zero connected in series, and the fifth matching functional unit is composed of elements whose imaginary part of admittance is equal to zero.
The filtering circuit according to claim 36, wherein the eighth matching functional unit is composed of elements whose imaginary part of admittance is greater than zero, and the seventh matching functional unit is composed of elements whose imaginary part of admittance is less than zero; or, the eighth matching functional unit is composed of elements whose imaginary part of admittance is less than zero, and the seventh matching functional unit is composed of elements whose imaginary part of admittance is greater than zero; or, the eighth matching functional unit is composed of elements whose imaginary part of admittance is greater than zero and elements whose imaginary part of admittance is less than zero connected in series, and the seventh matching functional unit is composed of elements whose imaginary part of admittance is equal to zero.
The filter circuit according to any one of claims 36 to 40, wherein the first band-stop functional unit comprises an element whose imaginary part of admittance is greater than zero and an element whose imaginary part of admittance is less than zero, and the element whose imaginary part of admittance is greater than zero and the element whose imaginary part of admittance is less than zero are connected in parallel; or, the first band-stop functional unit comprises an element whose imaginary part of admittance is greater than zero, an element whose imaginary part of admittance is less than zero and a third potential terminal, and the element whose imaginary part of admittance is greater than zero, the element whose imaginary part of admittance is less than zero and the third potential terminal are connected in series;

The second band-stop functional unit comprises an element whose imaginary part of admittance is greater than zero and an element whose imaginary part of admittance is less than zero, and the element whose imaginary part of admittance is greater than zero and the element whose imaginary part of admittance is less than zero are connected in parallel; or, the second band-stop functional unit comprises an element whose imaginary part of admittance is greater than zero, an element whose imaginary part of admittance is less than zero and a fourth potential terminal, and the element whose imaginary part of admittance is greater than zero, the element whose imaginary part of admittance is less than zero and the fourth potential terminal are connected in series;

The third band-stop functional unit includes an element whose imaginary part of admittance is greater than zero and an element whose imaginary part of admittance is less than zero, and the element whose imaginary part of admittance is greater than zero and the element whose imaginary part of admittance is less than zero are connected in parallel; or, the third band-stop functional unit includes an element whose imaginary part of admittance is greater than zero, an element whose imaginary part of admittance is less than zero and a fifth potential terminal, and the element whose imaginary part of admittance is greater than zero, the element whose imaginary part of admittance is less than zero and the fifth potential terminal are connected in series.
The filter circuit according to claim 41, wherein the third potential terminal, the fourth potential terminal, and the fifth potential terminal are at the same potential as the reference ground.
A circuit comprising the filter circuit described in any one of claims 36-42.