WO2024166389A1 - Display device - Google Patents

Abstract

According to the present invention, a first metal film, a first inorganic insulating film (13), a first semiconductor film that is formed of a polysilicon, a second inorganic insulating film (15), a second metal film, a third inorganic insulating film (17), a third metal film, a second semiconductor film that is formed of an oxide semiconductor, a fourth inorganic insulating film (19) and a fourth metal film are sequentially stacked. A second TFT (9B) of each subpixel is provided with a third terminal electrode (18c) and a fourth terminal electrode (18d), which are formed of the third metal film and are electrically connected respectively to a third conductor region (19aa) and a fourth conductor region (19ab) of a second semiconductor layer (19a) that is formed of the second semiconductor film. In a display area (D), a plurality of wiring lines that extend parallel to one another are formed of the first metal film.

Description

Display device

The present invention relates to a display device.

In recent years, as an alternative to liquid crystal display devices, self-emitting organic electroluminescence (EL) display devices using organic EL elements have been attracting attention. In these organic EL display devices, multiple thin film transistors (TFTs) are provided for each subpixel, which is the smallest unit of an image. Well-known examples of the semiconductor layers that make up the TFTs include semiconductor layers made of polysilicon with high mobility and semiconductor layers made of oxide semiconductors such as In-Ga-Zn-O with low leakage current.

For example, Patent Document 1 discloses a display device having a hybrid structure in which a first TFT using a polysilicon semiconductor and a second TFT using an oxide semiconductor are formed on a substrate.

JP 2020-17558 A

In the display device having the hybrid structure disclosed in the above Patent Document 1, the semiconductor layer made of an oxide semiconductor is electrically connected via a metal layer that contacts the semiconductor layer, so that contact holes for electrically connecting to the semiconductor layer made of a polysilicon semiconductor and the semiconductor layer made of an oxide semiconductor can be formed at the same time, and electrical connection to the semiconductor layer made of an oxide semiconductor can be easily made. However, in the display device having the hybrid structure disclosed in the above Patent Document 1, the wiring cross capacitance at the intersection of the wiring (e.g., gate line) formed in the same layer and made of the same material as the gate electrode of the second TFT using an oxide semiconductor and the wiring (e.g., source line) formed in the same layer and made of the same material as the source electrode and drain electrode of the second TFT tends to be large, so there is room for improvement.

The present invention was made in consideration of these points, and its purpose is to facilitate electrical connection with a semiconductor layer made of an oxide semiconductor and to reduce the wiring cross capacitance.

In order to achieve the above object, the display device according to the present invention is a display device comprising a base substrate, and a thin film transistor layer provided on the base substrate, in which a first metal film, a first inorganic insulating film, a first semiconductor film made of polysilicon, a second inorganic insulating film, a second metal film, a third inorganic insulating film, a third metal film, a second semiconductor film made of an oxide semiconductor, a fourth inorganic insulating film, and a fourth metal film are laminated in this order, and the thin film transistor layer is provided with a first thin film transistor having a first semiconductor layer formed by the first semiconductor film, and a second thin film transistor having a second semiconductor layer formed by the second semiconductor film, for each sub-pixel constituting a display area, and the first thin film transistor is provided with a first semiconductor layer having a first conductor region and a second conductor region spaced apart from each other and a first channel region defined between the first conductor region and the second conductor region, and a second thin film transistor having a second semiconductor layer formed by the second semiconductor film, and a first channel region defined between the first conductor region and the second conductor region and a second thin film transistor having a second semiconductor layer formed by the second semiconductor film. The second thin film transistor includes a first gate electrode formed of the second metal film and provided through an inorganic insulating film, a first terminal electrode and a second terminal electrode provided by the third metal film so as to be spaced apart from each other and electrically connected to the first conductor region and the second conductor region, respectively. The second thin film transistor includes the second semiconductor layer in which the third conductor region and the fourth conductor region are defined so as to be spaced apart from each other and a second channel region is defined between the third conductor region and the fourth conductor region, a second gate electrode provided on the second semiconductor layer through the fourth inorganic insulating film and formed of the fourth metal film, and a third terminal electrode and a fourth terminal electrode provided by the third metal film so as to be spaced apart from each other and electrically connected to the third conductor region and the fourth conductor region, respectively. The display region is characterized in that a plurality of wirings extending parallel to each other are provided by the first metal film.

The present invention makes it easy to establish electrical connection with a semiconductor layer made of an oxide semiconductor and reduces the wiring cross capacitance.

FIG. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention. FIG. 2 is a plan view of a display region of the organic EL display device according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view of a display region of the organic EL display device according to the first embodiment of the present invention. FIG. 4 is an equivalent circuit diagram of a TFT layer constituting the organic EL display device according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view of a light emission control TFT 9f and an anode discharge TFT 9g that constitute the TFT layer of the organic EL display device according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view of a writing TFT 9c constituting a TFT layer of the organic EL display device according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view of a power supply TFT 9e that constitutes a TFT layer of the organic EL display device according to the first embodiment of the present invention. FIG. 8 is a cross-sectional view of an initialization TFT 9a constituting a TFT layer of the organic EL display device according to the first embodiment of the present invention. FIG. 9 is a cross-sectional view showing an organic EL layer constituting the organic EL display device according to the first embodiment of the present invention. FIG. 10 is a cross-sectional view of a display region of an organic EL display device according to a second embodiment of the present invention.

The following describes in detail the embodiments of the present invention with reference to the drawings. Note that the present invention is not limited to the following embodiments.

First Embodiment
1 to 9 show a first embodiment of a display device according to the present invention. In the following embodiments, an organic EL display device having an organic EL element layer is exemplified as a display device having a light emitting element layer. Here, FIG. 1 is a plan view showing a schematic configuration of an organic EL display device 50a of this embodiment. Also, FIGS. 2 and 3 are a plan view and a cross-sectional view of a display region D of the organic EL display device 50a. Also, FIG. 4 is an equivalent circuit diagram of a TFT layer 30a constituting the organic EL display device 50a. Also, FIG. 5 is a cross-sectional view of a light emission control TFT 9f and an anode discharge TFT 9g constituting the TFT layer 30a. Also, FIG. 6 is a cross-sectional view of a write TFT 9c constituting the TFT layer 30a. Also, FIG. 7 is a cross-sectional view of a power supply TFT 9e constituting the TFT layer 30a. Also, FIG. 8 is a cross-sectional view of an initialization TFT 9a constituting the TFT layer 30a. Also, FIG. 9 is a cross-sectional view showing an organic EL layer 33 constituting the organic EL display device 50a.

As shown in FIG. 1, the organic EL display device 50a includes, for example, a rectangular display area D for displaying images, and a frame area F provided around the periphery of the display area D. Note that in this embodiment, a rectangular display area D is illustrated, but this rectangular shape also includes, for example, an approximately rectangular shape with arc-shaped sides, arc-shaped corners, or a shape with a notch in one of the sides.

In the display region D, as shown in FIG. 2, a plurality of sub-pixels P are arranged in a matrix. In addition, in the display region D, as shown in FIG. 2, for example, a sub-pixel P having a red light-emitting region Er for displaying red, a sub-pixel P having a green light-emitting region Eg for displaying green, and a sub-pixel P having a blue light-emitting region Eb for displaying blue are arranged adjacent to each other. In the display region D, for example, one pixel is composed of three adjacent sub-pixels P having a red light-emitting region Er, a green light-emitting region Eg, and a blue light-emitting region Eb.

A terminal portion T is provided at the end of the frame region F on the positive side in the X direction in FIG. 1 so as to extend in one direction (the Y direction in FIG. 1). In addition, as shown in FIG. 1, in the frame region F, between the display region D and the terminal portion T, a folding portion B is provided extending in one direction (the Y direction in FIG. 1) that can be folded, for example, 180° (in a U-shape) with the Y direction in FIG. as the folding axis.

As shown in FIG. 3, the organic EL display device 50a includes a resin substrate 10 provided as a base substrate, a TFT layer 30a provided on the resin substrate 10, an organic EL element layer 40 provided as a light emitting element layer on the TFT layer 30a, and a sealing film 45 provided on the organic EL element layer 40.

The resin substrate 10 is made of an organic resin material such as polyimide resin.

3, the TFT layer 30a includes a first base coat film 11 and a second base coat film 13 provided in order on the resin substrate 10, four first TFTs 9A, three second TFTs 9B, and one capacitor 9h (see FIG. 4) provided for each subpixel P on the second base coat film 13, and a second interlayer insulating film 22 and a planarization film 23 provided in order on each of the first TFTs 9A, each of the second TFTs 9B, and each of the capacitors 9h. Here, as shown in FIG. 2, the TFT layer 30a is provided with a plurality of gate lines 21g extending parallel to each other in the X direction in the figure. Also, as shown in FIG. 2, the TFT layer 30a is provided with a plurality of light emission control lines 21e extending parallel to each other in the X direction in the figure. Also, as shown in FIG. 2, the TFT layer 30a is provided with a plurality of second initialization power lines 16i extending parallel to each other in the X direction in the figure. As shown in FIG. 2, each light emission control line 21e is provided adjacent to each gate line 21g and each second initialization power line 16i. As shown in FIG. 2, the TFT layer 30a is provided with a plurality of source lines 12f as a plurality of wirings that extend parallel to each other in the Y direction in the figure. As shown in FIG. 2, the TFT layer 30a is provided with a plurality of power lines 12g as a plurality of wirings that extend parallel to each other in the Y direction in the figure. As shown in FIG. 2, each power line 12g is provided adjacent to each source line 12f.

In the TFT layer 30a, as shown in FIG. 3, a first base coat film 11, a first metal film, a second base coat film (first inorganic insulating film) 13, a first semiconductor film, a first gate insulating film (second inorganic insulating film) 15, a second metal film, a first interlayer insulating film (third inorganic insulating film) 17, a third metal film, a second semiconductor film, a second gate insulating film (fourth inorganic insulating film) 20, a fourth metal film, a second interlayer insulating film (fifth inorganic insulating film) 22, and a planarization film 23 are laminated in this order on a resin substrate 10. Here, the source line 12f and the power line 12g are formed of the first metal film. The second initialization power line 16i is formed of the second metal film. The gate line 21g and the light emission control line 21e are formed of the fourth metal film. In this embodiment, the second initialization power line 16i is formed from the second metal film. However, the second initialization power line may be formed from the third metal film. In this case, the second initialization power line is spaced apart from the source line 12f and the power line 12g in the thickness direction more than when the second initialization power line is formed from the second metal film. This makes it possible to reduce the wiring cross capacitance between the second initialization power line and the source line 12f and the power line 12g.

The first base coat film 11, the second base coat film 13, the first gate insulating film 15, the first interlayer insulating film 17, the second gate insulating film 20 and the second interlayer insulating film 22 are each composed of a single layer or a laminated film of an inorganic insulating film such as silicon nitride, silicon oxide, silicon oxynitride, etc. Here, the side of the first interlayer insulating film 17 facing the second semiconductor layer 19a (described later) and the side of the second gate insulating film 20 facing the second semiconductor layer 19a are each composed of, for example, a silicon oxide film.

As shown in FIG. 3, the first TFT 9A includes a first semiconductor layer 14a provided on the second base coat film 13, a first gate electrode 16a provided on the first semiconductor layer 14a via a first gate insulating film 15, and a first terminal electrode 18a and a second terminal electrode 18b provided on the first interlayer insulating film 17 so as to be spaced apart from each other.

The first semiconductor layer 14a is formed by the first semiconductor film made of polysilicon such as LTPS (low temperature polysilicon), and as shown in FIG. 3, includes a first conductor region 14aa and a second conductor region 14ab that are spaced apart from each other, and a first channel region 14ac that is defined between the first conductor region 14aa and the second conductor region 14ab.

As shown in FIG. 3, the first gate electrode 16a is provided so as to overlap the first channel region 14ac of the first semiconductor layer 14a, and is configured to control the conduction between the first conductor region 14aa and the second conductor region 14ab of the first semiconductor layer 14a. Here, the first gate electrode 16a is formed of the second metal film, similar to the second initialization power line 16i.

As shown in FIG. 3, the first terminal electrode 18a and the second terminal electrode 18b are electrically connected to the first conductor region 14aa and the second conductor region 14ab of the first semiconductor layer 14a, respectively, through contact holes formed in the laminated film of the first gate insulating film 15 and the first interlayer insulating film 17. Here, the first terminal electrode 18a and the second terminal electrode 18b are formed from the third metal film.

As shown in FIG. 3, the second TFT 9B includes a second semiconductor layer 19a provided on the first interlayer insulating film 17, a second gate electrode 21a provided on the second semiconductor layer 19a via a second gate insulating film 20, and a third terminal electrode 18c and a fourth terminal electrode 18d provided on the first interlayer insulating film 17 so as to be spaced apart from each other via the second semiconductor layer 19a.

The second semiconductor layer 19a is formed of a second semiconductor film made of an oxide semiconductor such as In-Ga-Zn-O, and includes a third conductor region 19aa and a fourth conductor region 19ab that are defined to be spaced apart from each other, and a second channel region 19ac that is defined between the third conductor region 19aa and the fourth conductor region 19ab, as shown in FIG. 3. Also, on the resin substrate 10 side of the second semiconductor layer 19a, a lower light-shielding layer 12a formed of the first metal film is provided, as shown in FIG. 3. The lower light-shielding layer 12a is provided so as to overlap the second semiconductor layer 19a of the second TFT 9B in a plan view. Here, the In-Ga-Zn-O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited. The In-Ga-Zn-O-based semiconductor may be amorphous or crystalline. As the crystalline In-Ga-Zn-O-based semiconductor, a crystalline In-Ga-Zn-O-based semiconductor in which the c-axis is oriented approximately perpendicular to the layer surface is preferable. In addition, instead of the In-Ga-Zn-O-based semiconductor, another oxide semiconductor may be included. As the other oxide semiconductor, for example, an In-Sn-Zn-O-based semiconductor (for example, In ₂ O ₃ -SnO ₂ -ZnO; InSnZnO) may be included. Here, the In-Sn-Zn-O-based semiconductor is a ternary oxide of In (indium), Sn (tin) and Zn (zinc). Other oxide semiconductors may include In-Al-Zn-O based semiconductors, In-Al-Sn-Zn-O based semiconductors, Zn-O based semiconductors, In-Zn-O based semiconductors, Zn-Ti-O based semiconductors, Cd-Ge-O based semiconductors, Cd-Pb-O based semiconductors, CdO (cadmium oxide), Mg-Zn-O based semiconductors, In-Ga-Sn-O based semiconductors, In-Ga-O based semiconductors, Zr-In-Zn-O based semiconductors, Hf-In-Zn-O based semiconductors, Al-Ga-Zn-O based semiconductors, Ga-Zn-O based semiconductors, In-Ga-Zn-Sn-O based semiconductors, InGaO ₃ (ZnO) ₅ , magnesium zinc oxide (Mg _x Zn _1-x O), cadmium zinc oxide (Cd _x Zn _1-x O), and the like. As the Zn—O-based semiconductor, ZnO in an amorphous state, a polycrystalline state, a microcrystalline state in which the amorphous state and the polycrystalline state are mixed, or a semiconductor in which no impurity element is added may be used, to which one or more impurity elements selected from among group 1 elements, group 13 elements, group 14 elements, group 15 elements, group 17 elements, and the like are added.

As shown in FIG. 3, the second gate electrode 21a is provided so as to overlap the second channel region 19ac of the second semiconductor layer 19a, and is configured to control the conduction between the third conductor region 19aa and the fourth conductor region 19ab of the second semiconductor layer 19a. Here, the second gate electrode 21a is formed of the fourth metal film, similar to the gate line 21g and the light emission control line 21e.

As shown in FIG. 3, the third terminal electrode 18c and the fourth terminal electrode 18d are in contact with the first interlayer insulating film 17 side of the third conductor region 19aa of the second semiconductor layer 19a and the first interlayer insulating film 17 side of the fourth conductor region 19ab, respectively, and are electrically connected to the third conductor region 19aa and the fourth conductor region 19ab of the second semiconductor layer 19a, respectively. Here, the third terminal electrode 18c and the fourth terminal electrode 18d are formed of the third metal film, similar to the first terminal electrode 18a and the second terminal electrode 18b.

In this embodiment, the four first TFTs 9A having a first semiconductor layer 14a formed of polysilicon are exemplified by a writing TFT 9c, a driving TFT 9d, a power supply TFT 9e, and a light emission control TFT 9f, which will be described later, and the three second TFTs 9B having a second semiconductor layer 19a formed of an oxide semiconductor are exemplified by an initialization TFT 9a, a compensation TFT 9b, and an anode discharge TFT 9g, which will be described later (see FIG. 4). In the equivalent circuit diagram of FIG. 4, the first terminal electrodes 18a and second terminal electrodes 18b of each of the TFTs 9c, 9d, 9e, and 9f are indicated by circled numbers 1 and 2, and the third terminal electrodes 18c and fourth terminal electrodes 18d of each of the TFTs 9a, 9b, and 9g are indicated by circled numbers 3 and 4. In addition, the equivalent circuit diagram of FIG. 4 shows the pixel circuit of the sub-pixel P in the nth row and mth column, but also includes a part of the pixel circuit of the sub-pixel P in the (n-1)th row and mth column. In addition, in the equivalent circuit diagram of FIG. 4, the power supply line 12g that supplies the high power supply voltage ELVDD also serves as the first initialization power supply line, but the power supply line 12g and the first initialization power supply line may be provided separately. In addition, the same voltage as the low power supply voltage ELVSS is input to the second initialization power supply line 16i, but this is not limited thereto, and a voltage different from the low power supply voltage ELVSS that turns off the organic EL element 35 described later may be input.

As shown in Figures 4 and 8, in each subpixel P, the initialization TFT 9a has its second gate electrode 21a electrically connected to the gate line 21g (n-1) of the previous stage (n-1 stage), its third terminal electrode 18c electrically connected to the lower conductive layer of the capacitor 9h described below, the third terminal electrode (18c) of the compensation TFT 9b, and the first gate electrode (16a) of the drive TFT 9d, and its fourth terminal electrode 18d electrically connected to the power line 12g.

As shown in FIG. 4, in each subpixel P, the compensation TFT 9b has its second gate electrode (21a) electrically connected to the gate line 21g(n) of its own stage (nth stage), its third terminal electrode (18c) electrically connected to the lower conductive layer of the capacitor 9h described below, the third terminal electrode (18c) of the initialization TFT 9a, and the first gate electrode (16a) of the driving TFT 9d, and its fourth terminal electrode (18d) electrically connected to the second terminal electrode (18b) of the power supply TFT 9e and the first terminal electrode (18a) of the driving TFT 9d.

As shown in Figures 4 and 6, in each subpixel P, the first gate electrode 16a of the write TFT 9c is electrically connected to the gate line 21g(n) of its own stage (nth stage), its first terminal electrode 18a is electrically connected to the corresponding source line 12f, and its second terminal electrode 18b is electrically connected to the second terminal electrode (18b) of the drive TFT 9d and the first terminal electrode (18a) of the emission control TFT 9f.

As shown in FIG. 4, in each subpixel P, the driving TFT 9d has its first gate electrode (16a) electrically connected to the third terminal electrodes (18c) of the initialization TFT 9a and the compensation TFT 9b, and to the lower conductive layer of the capacitor 9h described later, its first terminal electrode (18a) electrically connected to the fourth terminal electrode (18d) of the compensation TFT 9b and the second terminal electrode (18b) of the power supply TFT 9e, and its second terminal electrode (18b) electrically connected to the second terminal electrode (18b) of the writing TFT 9c and the first terminal electrode (18a) of the emission control TFT 9f. Here, the driving TFT 9d is configured to control the drive current of the organic EL element 35.

As shown in Figures 4 and 7, in each subpixel P, the power supply TFT 9e has its first gate electrode 16a electrically connected to the emission control line 21e of its own stage (nth stage), its first terminal electrode 18a electrically connected to the power supply line 12g, and its second terminal electrode 18b electrically connected to the first terminal electrode (18a) of the driving TFT 9d and the fourth terminal electrode (18d) of the compensation TFT 9b.

As shown in Figures 4 and 5, in each subpixel P, the first gate electrode 16a of the emission control TFT 9f is electrically connected to the emission control line 21e of its own row (nth row), the first terminal electrode 18a is electrically connected to the second terminal electrodes (18b) of the drive TFT 9d and the write TFT 9c, and the second terminal electrode 18b is electrically connected via the connection electrode 18j to the third terminal electrode 18c of the anode discharge TFT 9g, the upper conductive layer of the capacitor 9h described later, and the first electrode 31 of the organic EL element 35 described later.

As shown in Figures 4 and 5, in each subpixel P, the anode discharge TFT 9g has its second gate electrode 21a electrically connected to the gate line 21g(n) of its own stage (nth stage), its third terminal electrode 18c electrically connected via a connection electrode 18j to the second terminal electrode 18b of the emission control TFT 9f, the upper conductive layer of the capacitor 9h described later, and the first electrode 31 of the organic EL element 35 described later, and its fourth terminal electrode 18d electrically connected to the second initialization power line 16i.

The capacitor 9h includes, for example, a lower conductive layer (not shown) formed of the second metal film, a first interlayer insulating film 17 provided to cover the lower conductive layer, and an upper conductive layer (not shown) provided on the first interlayer insulating film 17 to overlap the lower conductive layer and formed of the third metal film. As shown in FIG. 4, in each subpixel P, the lower conductive layer of the capacitor 9h is electrically connected to the first gate electrode (16a) of the driving TFT 9d and the third terminal electrodes (18c) of the initialization TFT 9a and compensation TFT 9b, and the upper conductive layer is electrically connected to the third terminal electrode (18c) of the anode discharge TFT 9g, the second terminal electrode (18b) of the light emission control TFT 9f, and the first electrode 31 of the organic EL element 35 described later.

The planarization film 23 has a flat surface in the display area D and is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (spin on glass) material.

As shown in FIG. 3, the organic EL element layer 40 includes a plurality of organic EL elements 35 arranged as a plurality of light-emitting elements in a matrix pattern corresponding to a plurality of sub-pixels P, and edge covers 32 arranged in a lattice pattern common to all the sub-pixels P so as to cover the peripheral edge of the first electrode 31 of each organic EL element 35, which will be described later.

As shown in FIG. 3, in each subpixel P, the organic EL element 35 includes a first electrode 31 provided on the planarization film 23 of the TFT layer 30a, an organic EL layer 33 provided on the first electrode 31, and a second electrode 34 provided on the organic EL layer 33.

The first electrode 31 is electrically connected to the second terminal electrode 18b of the light emission control TFT 9f of each sub-pixel P through a contact hole formed in the laminated film of the second interlayer insulating film 22 and the planarization film 23. The first electrode 31 has a function of injecting holes (positive holes) into the organic EL layer 33. In addition, the first electrode 31 is more preferably formed of a material having a large work function in order to improve the efficiency of hole injection into the organic EL layer 33. Here, examples of materials constituting the first electrode 31 include metal materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). The material constituting the first electrode 31 may be, for example, an alloy such as astatine (At)/astatine oxide (AtO ₂ ). The material constituting the first electrode 31 may be, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). The first electrode 31 may be formed by stacking a plurality of layers made of the above materials. Examples of compound materials having a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).

As shown in FIG. 9, the organic EL layer 33 includes a hole injection layer 1, a hole transport layer 2, a light-emitting layer 3, an electron transport layer 4, and an electron injection layer 5, which are arranged in this order on the first electrode 31.

The hole injection layer 1 is also called an anode buffer layer, and has the function of bringing the energy levels of the first electrode 31 and the organic EL layer 33 closer together and improving the efficiency of hole injection from the first electrode 31 to the organic EL layer 33. Here, examples of materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

The hole transport layer 2 has the function of improving the efficiency of transporting holes from the first electrode 31 to the organic EL layer 33. Here, examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, zinc selenide, etc.

The light-emitting layer 3 is a region where holes and electrons are injected from the first electrode 31 and the second electrode 34, respectively, and where the holes and electrons recombine when a voltage is applied by the first electrode 31 and the second electrode 34. Here, the light-emitting layer 3 is formed from a material with high luminous efficiency. Examples of materials constituting the light-emitting layer 3 include metal oxinoid compounds [8-hydroxyquinoline metal complexes], naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazole derivatives, styryl derivatives, styrylamine derivatives, bisstyrylbenzene derivatives, tristyrylbenzene derivatives, perylene derivatives, perinone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, aquidine derivatives, phenoxazone, quinacridone derivatives, rubrene, poly-p-phenylenevinylene, polysilane, and the like.

The electron transport layer 4 has the function of efficiently transferring electrons to the light-emitting layer 3. Here, examples of materials constituting the electron transport layer 4 include organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, fluorenone derivatives, silole derivatives, and metal oxinoid compounds.

The electron injection layer 5 has a function of bringing the energy levels of the second electrode 34 and the organic EL layer 33 closer to each other and improving the efficiency of electron injection from the second electrode 34 to the organic EL layer 33, and this function makes it possible to reduce the driving voltage of the organic EL element 35. The electron injection layer 5 is also called a cathode buffer layer. Here, examples of materials constituting the electron injection layer 5 include inorganic alkali compounds such as lithium fluoride (LiF), magnesium fluoride (MgF ₂ ), calcium fluoride (CaF ₂ ), strontium fluoride (SrF ₂ ), and barium fluoride (BaF ₂ ), aluminum oxide (Al ₂ O ₃ ), and strontium oxide (SrO).

3, the second electrode 34 is provided in common to all the sub-pixels P so as to cover each organic EL layer 33 and the edge cover 32. The second electrode 34 has a function of injecting electrons into the organic EL layer 33. In addition, the second electrode 34 is more preferably made of a material having a small work function in order to improve the efficiency of electron injection into the organic EL layer 33. Here, examples of materials constituting the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). The second electrode 34 may be formed of an alloy such as magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), sodium (Na)/potassium (K), astatine (At)/astatine oxide (AtO ₂ ), lithium (Li)/aluminum (Al), lithium (Li)/calcium (Ca)/aluminum (Al), or lithium fluoride (LiF)/calcium (Ca)/aluminum (Al). The second electrode 34 may be formed of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). The second electrode 34 may be formed by stacking a plurality of layers made of the above materials. Examples of materials with a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), sodium (Na)/potassium (K), lithium (Li)/aluminum (Al), lithium (Li)/calcium (Ca)/aluminum (Al), and lithium fluoride (LiF)/calcium (Ca)/aluminum (Al).

The edge cover 32 is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG material.

As shown in FIG. 3, the sealing film 45 is provided to cover the second electrode 34, and includes a first inorganic sealing film 41, an organic sealing film 42, and a second inorganic sealing film 43 laminated in that order on the second electrode 34, and has the function of protecting the organic EL layer 33 of the organic EL element 35 from moisture and oxygen.

The first inorganic sealing film 41 and the second inorganic sealing film 43 are composed of an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film.

The organic sealing film 42 is made of an organic resin material such as, for example, acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, or polyamide resin.

In the organic EL display device 50a configured as described above, in each subpixel P, first, the light-emitting control line 21e is selected and deactivated, causing the organic EL element 35 to enter a non-light-emitting state. In this non-light-emitting state, the preceding gate line 21g(n-1) is selected, and a gate signal is input to the initialization TFT 9a via that gate line 21g(n-1), causing the initialization TFT 9a to enter an ON state, the high power supply voltage ELVDD of the power supply line 12g is applied to the capacitor 9h, and the driving TFT 9d enters an ON state. This causes the charge in the capacitor 9h to be discharged, and the voltage applied to the gate electrode of the driving TFT 9d is initialized. Next, the gate line 21g(n) of the current stage is selected and activated, so that the compensation TFT 9b and the writing TFT 9c are turned on, and a predetermined voltage corresponding to the source signal transmitted through the corresponding source line 12f is written into the capacitor 9h through the driving TFT 9d in a diode-connected state, and the anode discharge TFT 9g is turned on, and an initialization signal is applied to the first electrode 31 of the organic EL element 35 through the second initialization power line 19i, resetting the charge accumulated in the first electrode 31. After that, the light emission control line 21e is selected, the power supply TFT 9e and the light emission control TFT 9f are turned on, and a drive current corresponding to the voltage applied to the gate electrode of the driving TFT 9d is supplied from the power line 12g to the organic EL element 35. In this way, in the organic EL display device 50a, the organic EL element 35 emits light at a luminance corresponding to the drive current in each sub-pixel P, and an image is displayed.

Next, a method for manufacturing the organic EL display device 50a of this embodiment will be described. The method for manufacturing the organic EL display device 50a includes a TFT layer forming process, an organic EL element layer forming process, and a sealing film forming process.

<TFT layer formation process>
First, for example, a silicon oxide film (thickness: about 150 nm) or the like is formed on a resin substrate 10 formed on a glass substrate by, for example, a plasma CVD (Chemical Vapor Deposition) method to form a first base coat film 11. Form.

Next, a molybdenum film (about 250 nm thick) or the like is formed by, for example, sputtering on the substrate surface on which the first base coat film 11 has been formed, and the first metal film is then patterned to form the lower light-shielding layer 12a, source line 12f, power line 12g, etc.

Furthermore, a silicon oxide film (thickness: about 300 nm) is formed by, for example, plasma CVD on the substrate surface on which the lower light-shielding layer 12a etc. are formed, thereby forming a second base coat film 13.

After that, an amorphous silicon film (about 50 nm thick) is formed on the substrate surface on which the second base coat film 13 has been formed, for example, by plasma CVD, and the amorphous silicon film is crystallized by laser annealing or the like to form a first semiconductor film made of polysilicon, and then the first semiconductor film is patterned to form the first semiconductor layer 14a.

Next, a silicon oxide film (about 125 nm thick) is formed by, for example, plasma CVD on the substrate surface on which the first semiconductor layer 14a is formed to form the first gate insulating film 15, and then a molybdenum film (about 200 nm thick) is formed by, for example, sputtering to form a second metal film, which is then patterned to form the first gate electrode 16a, the second initialization power line 16i, etc.

Furthermore, by doping impurity ions such as phosphorus using the first gate electrode 16a as a mask, a portion of the first semiconductor layer 14a is made conductive, thereby forming a first conductor region 14aa, a second conductor region 14ab, and a first channel region 14ac in the first semiconductor layer 14a.

Then, on the substrate surface where a portion of the first semiconductor layer 14a has been made conductive, a silicon nitride film (about 150 nm) and a silicon oxide film (about 50 nm thick) are sequentially formed, for example, by plasma CVD, and then contact holes are formed in the laminated film of the silicon nitride film and the silicon oxide film to form the first interlayer insulating film 17.

Next, a titanium film (approximately 50 nm thick), a copper film (approximately 400 nm thick), an ITO film (approximately 50 nm thick), etc. are sequentially formed by, for example, a sputtering method on the substrate surface on which the first interlayer insulating film 17 has been formed, and after forming a third metal film, the third metal film is patterned to form the first terminal electrode 18a, the second terminal electrode 18b, the third terminal electrode 18c, the fourth terminal electrode 18d, etc.

Furthermore, on the substrate surface on which the first terminal electrode 18a etc. are formed, an oxide semiconductor film (with a thickness of about 30 nm) such as _InGaZnO4 is formed by, for example, a sputtering method to form a second semiconductor film, and then the second semiconductor film is patterned to form the second semiconductor layer 19a.

After that, a silicon oxide film (about 100 nm thick) is formed on the substrate surface on which the second semiconductor layer 19a is formed, for example, by plasma CVD, and then a molybdenum film (about 200 nm thick) is formed by sputtering to form a fourth metal film, and the silicon oxide film and the fourth metal film are patterned to form the second gate insulating film 20 from the silicon oxide film, and the second gate electrode 21a, gate line 21g, light emission control line 21e, etc. from the fourth metal film.

Then, a silicon oxide film (about 500 nm thick) is formed by, for example, plasma CVD on the substrate surface on which the second gate insulating film 20 and other layers are formed, to form the second interlayer insulating film 22. Note that a portion of the second semiconductor layer 19a is made conductive by heat treatment after the formation of the second interlayer insulating film 22, and a third conductor region 19aa, a fourth conductor region 19ab, and a second channel region 19ac are formed in the second semiconductor layer 19a.

Furthermore, an acrylic photosensitive resin film (about 2 μm thick) is applied to the substrate surface on which the second interlayer insulating film 22 is formed, for example, by spin coating or slit coating, and then the applied film is pre-baked, exposed, developed, and post-baked to form a planarization film 23 with contact holes.

Finally, the second interlayer insulating film 22 exposed from the contact hole in the planarization film 23 is removed, and the contact hole is made to reach the second terminal electrode 18b of the light-emission control TFT 9f.

In this manner, the TFT layer 30a can be formed.

<Organic EL element layer formation process>
On the planarization film 23 of the TFT layer 30a formed in the TFT layer formation process, a first electrode 31, an edge cover 32, an organic EL layer 33 (a hole injection layer 1, a hole transport layer 24, a hole transport layer 26, a hole transport layer 28, a hole transport layer 29, a hole transport layer 30a, a hole transport layer 31, a hole transport layer 32, a hole transport layer 33, a hole transport layer 34, a hole transport layer 35, a hole transport layer 36, a hole transport layer 37, a hole transport layer 38, a hole transport layer 39 ... The organic EL element layer 40 is formed by forming the layer 2, the light-emitting layer 3, the electron transport layer 4, the electron injection layer 5, and the second electrode 34.

<Sealing film forming process>
First, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is deposited by plasma CVD using a mask on the substrate surface on which the organic EL element layer 40 formed in the organic EL element layer formation process is formed, thereby forming a first inorganic sealing film 41.

Next, an organic resin material such as an acrylic resin is deposited on the substrate surface on which the first inorganic sealing film 41 is formed, for example by an inkjet method, to form an organic sealing film 42.

Then, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is deposited by plasma CVD using a mask on the substrate surface on which the organic sealing film 42 has been formed, forming a second inorganic sealing film 43, thereby forming a sealing film 45.

Finally, a protective sheet (not shown) is attached to the substrate surface on which the sealing film 45 has been formed, and then laser light is applied from the glass substrate side of the resin substrate 10 to peel the glass substrate from the underside of the resin substrate 10, and a protective sheet (not shown) is attached to the underside of the resin substrate 10 from which the glass substrate has been peeled off.

In this manner, the organic EL display device 50a of this embodiment can be manufactured.

As described above, in the organic EL display device 50a of this embodiment, in the second TFT 9B having a second semiconductor layer 19a made of an oxide semiconductor provided in each subpixel P, the third terminal electrode 18c and the fourth terminal electrode 18d are in contact with the third conductor region 19aa and the fourth conductor region 19ab of the second semiconductor layer 19a from the resin substrate 10 side and are electrically connected, respectively. As a result, to form an electrical connection with the third conductor region 19aa and the fourth conductor region 19ab of the second semiconductor layer 19a, it is only necessary to form contact holes reaching the third terminal electrode 18c and the fourth terminal electrode 18d on the organic EL element layer 40 side closer to the third terminal electrode 18c and the fourth terminal electrode 18d, or to form contact holes reaching the third terminal electrode 18c and the fourth terminal electrode 18d on the resin substrate 10 side closer to the third terminal electrode 18c and the fourth terminal electrode 18d, without forming contact holes reaching the third conductor region 19aa and the fourth conductor region 19ab made of an oxide semiconductor that has low resistance to hydrofluoric acid, etc., thereby making it possible to easily form an electrical connection with the second semiconductor layer 19a made of an oxide semiconductor. In the TFT layer 30a, the first base coat film 11, the first metal film, the second base coat film 13, the first semiconductor film made of polysilicon, the first gate insulating film 15, the second metal film, the first interlayer insulating film 17, the third metal film, the second semiconductor film made of an oxide semiconductor, the second gate insulating film 20, and the fourth metal film are laminated in this order on the resin substrate 10, and in the display region (D), a plurality of source lines 12f and a plurality of power lines 12g formed by the first metal film are provided to extend parallel to each other. As a result, the gate lines 21g and the light emission control lines 21e formed by the fourth metal film are spaced apart from the source lines 12f and the power lines 12g in the thickness direction, so that the wiring cross capacitance between the gate lines 21g and the light emission control lines 21e and the source lines 12f and the power lines 12g can be reduced. Therefore, it is possible to facilitate electrical connection with the semiconductor layer made of an oxide semiconductor and reduce the wiring cross capacitance.

In addition, according to the organic EL display device 50a of this embodiment, the source line 12f and the power line 12g are formed of the first metal film, and the first terminal electrode 18a and the second terminal electrode 18b of the first TFT 9A and the third terminal electrode 18c and the fourth terminal electrode 18d of the second TFT 9B are formed of the third metal film, so that the source line 12f and the power line 12g and the first terminal electrode 18a, the second terminal electrode 18b, the third terminal electrode 18c and the fourth terminal electrode 18d are provided on different layers. As a result, the wiring extending to the display area D and the electrodes of the first TFT 9A and the second TFT 9B in each subpixel P of the display area D are formed on different layers, so that even with a high-definition pixel size for mobile applications, for example, wiring leakage between adjacent source lines 12f and power lines 12g can be suppressed.

In addition, according to the organic EL display device 50a of this embodiment, a lower light-shielding layer 12a formed of a first metal film is provided on the resin substrate 10 side of the second semiconductor layer 19a, so that it is possible to prevent light from entering the second channel region 19ac of the second semiconductor layer 19a and prevent impurity ions contained in the resin substrate 10 from reaching the second channel region 19ac.

Second Embodiment
Fig. 10 shows a second embodiment of a display device according to the present invention. Here, Fig. 10 is a cross-sectional view of a display region D of an organic EL display device 50b of this embodiment. Note that in the following embodiments, the same parts as those in Figs. 1 to 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the first embodiment, an organic EL display device 50a is illustrated having a TFT layer 30a provided with a lower light-shielding layer 12a, but in this embodiment, an organic EL display device 50b is illustrated having a TFT layer 30b provided with a lower light-shielding layer 12a and an upper light-shielding layer 24.

The organic EL display device 50b, like the organic EL display device 50a of the first embodiment, includes, for example, a rectangular display area D for displaying images, and a frame area F arranged around the periphery of the display area D.

As shown in FIG. 10, the organic EL display device 50b includes a resin substrate 10 provided as a base substrate, a TFT layer 30b provided on the resin substrate 10, an organic EL element layer 40 provided as a light emitting element layer on the TFT layer 30b, and a sealing film 45 provided on the organic EL element layer 40.

The TFT layer 30b, like the TFT layer 30a of the first embodiment, includes a first base coat film 11 and a second base coat film 13 provided in order on a resin substrate 10, four first TFTs 9A, three second TFTs 9B, and one capacitor 9h (see FIG. 4) provided for each subpixel P on the second base coat film 13, and a second interlayer insulating film 22 and a planarization film 23 provided in order on each of the first TFTs 9A, each of the second TFTs 9B, and each of the capacitors 9h. Here, like the TFT layer 30a of the first embodiment, the TFT layer 30b includes a plurality of gate lines 21g, a plurality of light emission control lines 21e, a plurality of second initialization power lines 16i, a plurality of source lines 12f, and a plurality of power lines 12g.

10, in the TFT layer 30b, a first base coat film 11, a first metal film, a second base coat film (first inorganic insulating film) 13, a first semiconductor film, a first gate insulating film (second inorganic insulating film) 15, a second metal film, a first interlayer insulating film (third inorganic insulating film) 17, a third metal film, a second semiconductor film, a second gate insulating film (fourth inorganic insulating film) 20, a fourth metal film, a second interlayer insulating film (fifth inorganic insulating film) 22, a fifth metal film, and a planarization film 23 are laminated in this order on a resin substrate 10. Here, in the TFT layer 30b, as shown in FIG. 10, an upper light-shielding layer 24 formed of the fifth metal film is provided on the organic EL element layer 40 side of the first TFT 9A and the second TFT 9B. The upper light-shielding layer 24 is arranged to overlap the first semiconductor layer 14a of the first TFT 9A and the second semiconductor layer 19a of the second TFT 9B in a plan view.

In the organic EL display device 50b configured as described above, like the organic EL display device 50a of the first embodiment, the organic EL element 35 in each subpixel P emits light with a luminance according to the drive current, thereby displaying an image.

The organic EL display device 50b of this embodiment can be manufactured by forming a molybdenum film (about 250 nm thick) or the like by sputtering, for example, on the substrate surface on which the second interlayer insulating film 22 is formed in the TFT layer formation step of the manufacturing method for the organic EL display device 50a of the first embodiment described above, forming a fifth metal film, and then patterning the fifth metal film to form the upper light-shielding layer 24, and further forming a planarization film 23 in the same manner as in the first embodiment described above to form the TFT layer 30b.

As described above, in the organic EL display device 50b of this embodiment, in the second TFT 9B having a second semiconductor layer 19a made of an oxide semiconductor provided in each subpixel P, the third terminal electrode 18c and the fourth terminal electrode 18d are in contact with the third conductor region 19aa and the fourth conductor region 19ab of the second semiconductor layer 19a from the resin substrate 10 side and are electrically connected, respectively. As a result, to form an electrical connection with the third conductor region 19aa and the fourth conductor region 19ab of the second semiconductor layer 19a, it is only necessary to form contact holes reaching the third terminal electrode 18c and the fourth terminal electrode 18d on the organic EL element layer 40 side closer to the third terminal electrode 18c and the fourth terminal electrode 18d, or to form contact holes reaching the third terminal electrode 18c and the fourth terminal electrode 18d on the resin substrate 10 side closer to the third terminal electrode 18c and the fourth terminal electrode 18d, without forming contact holes reaching the third conductor region 19aa and the fourth conductor region 19ab made of an oxide semiconductor that has low resistance to hydrofluoric acid, etc., thereby making it possible to easily form an electrical connection with the second semiconductor layer 19a made of an oxide semiconductor. In the TFT layer 30b, the first base coat film 11, the first metal film, the second base coat film 13, the first semiconductor film made of polysilicon, the first gate insulating film 15, the second metal film, the first interlayer insulating film 17, the third metal film, the second semiconductor film made of an oxide semiconductor, the second gate insulating film 20, and the fourth metal film are laminated in this order on the resin substrate 10, and in the display region (D), a plurality of source lines 12f and a plurality of power lines 12g formed of the first metal film are provided to extend parallel to each other. As a result, the gate lines 21g and the light emission control lines 21e formed of the fourth metal film are spaced apart from the source lines 12f and the power lines 12g in the thickness direction, so that the wiring cross capacitance between the gate lines 21g and the light emission control lines 21e and the source lines 12f and the power lines 12g can be reduced. Therefore, it is possible to facilitate electrical connection with the semiconductor layer made of an oxide semiconductor and reduce the wiring cross capacitance.

In addition, according to the organic EL display device 50b of this embodiment, the source line 12f and the power line 12g are formed of the first metal film, and the first terminal electrode 18a and the second terminal electrode 18b of the first TFT 9A and the third terminal electrode 18c and the fourth terminal electrode 18d of the second TFT 9B are formed of the third metal film, so that the source line 12f and the power line 12g and the first terminal electrode 18a, the second terminal electrode 18b, the third terminal electrode 18c and the fourth terminal electrode 18d are provided on different layers. As a result, the wiring extending to the display area D and the electrodes of the first TFT 9A and the second TFT 9B in each subpixel P of the display area D are formed on different layers, so that even with a high-definition pixel size for mobile applications, for example, wiring leakage between adjacent source lines 12f and power lines 12g can be suppressed.

In addition, according to the organic EL display device 50b of this embodiment, a lower light-shielding layer 12a formed of a first metal film is provided on the resin substrate 10 side of the second semiconductor layer 19a, so that it is possible to prevent light from entering the second channel region 19ac of the second semiconductor layer 19a and prevent impurity ions contained in the resin substrate 10 from reaching the second channel region 19ac.

In addition, according to the organic EL display device 50b of this embodiment, an upper light-shielding layer 24 is provided on the organic EL element layer 30 side of the first TFT 9A and the second TFT 9B. Therefore, even if stray light is generated from the light emitted by the organic EL element 35, it is difficult for the light to enter the first semiconductor layer 14a of the first TFT 9A and the second semiconductor layer 19a of the second TFT 9B, thereby improving the stability of the operation of the first TFT 9A and the second TFT 9B.

Other Embodiments
In each of the above embodiments, an organic EL display device is exemplified in which a first TFT having a first semiconductor layer formed of polysilicon and a second TFT having a second semiconductor layer formed of an oxide semiconductor are provided in each sub-pixel of the display region, but the first TFT may be provided in the frame region to configure a driving circuit such as a gate driver.

In addition, in each of the above embodiments, an organic EL layer having a five-layer laminate structure of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer is exemplified, but the organic EL layer may have a three-layer laminate structure of, for example, a hole injection layer/hole transport layer, a light-emitting layer, and an electron transport layer/electron injection layer.

In addition, in each of the above embodiments, an organic EL display device in which the first electrode is an anode and the second electrode is a cathode is exemplified, but the present invention can also be applied to an organic EL display device in which the layered structure of the organic EL layer is inverted, and the first electrode is a cathode and the second electrode is an anode.

In addition, in each of the above embodiments, an organic EL display device has been described as an example of a display device, but the present invention can be applied to a display device having a plurality of light-emitting elements driven by electric current, for example, a display device having QLEDs (Quantum-dot light emitting diodes), which are light-emitting elements that use a quantum dot-containing layer.

As described above, the present invention is useful for flexible display devices.

D Display area P Sub-pixel 9A First TFT (first thin film transistor)
9B Second TFT (second thin film transistor)
9a Initialization TFT (second thin film transistor)
9b Compensation TFT (second thin film transistor)
9c Writing TFT (first thin film transistor)
9d Driving TFT (first thin film transistor)
9e Power supply TFT (first thin film transistor)
9f Light Emission Control TFT (First Thin Film Transistor)
9g Anode discharge TFT (second thin film transistor)
10 Resin substrate (base substrate)
12a: Lower light shielding layer 12f: Source line (wiring)
12g power line (wiring)
13 Second base coat film (first inorganic insulating film)
14a: first semiconductor layer 14aa; first conductor region 14ab; second conductor region 14ac; first channel region 15: first gate insulating film (second inorganic insulating film)
16a: First gate electrode 17: First interlayer insulating film (third inorganic insulating film)
18a: First terminal electrode 18b: Second terminal electrode 18c: Third terminal electrode 18d: Fourth terminal electrode 19a: Second semiconductor layer 19aa: Third conductor region 19ab: Fourth conductor region 19ac: Second channel region 20: Second gate insulating film (fourth inorganic insulating film)
21a: second gate electrode 22: second interlayer insulating film (fifth inorganic insulating film)
23 Planarization film 24 Upper light-shielding layer 30a, 30b TFT layer (thin film transistor layer)
35 Organic EL element (organic electroluminescence element, light-emitting element)
40 Organic EL element layer (light emitting element layer)
45 Sealing film 50a, 50b Organic EL display device

Claims (7)

A base substrate;
a thin film transistor layer provided on the base substrate, the thin film transistor layer being formed by sequentially stacking a first metal film, a first inorganic insulating film, a first semiconductor film made of polysilicon, a second inorganic insulating film, a second metal film, a third inorganic insulating film, a third metal film, a second semiconductor film made of an oxide semiconductor, a fourth inorganic insulating film, and a fourth metal film;
a display device in which a first thin film transistor having a first semiconductor layer formed by the first semiconductor film and a second thin film transistor having a second semiconductor layer formed by the second semiconductor film are provided for each sub-pixel constituting a display area,
the first thin film transistor comprises: the first semiconductor layer in which a first conductor region and a second conductor region are defined so as to be spaced apart from each other and a first channel region is defined between the first conductor region and the second conductor region; a first gate electrode provided on the first semiconductor layer via the second inorganic insulating film and formed of the second metal film; and a first terminal electrode and a second terminal electrode provided by the third metal film so as to be spaced apart from each other and electrically connected to the first conductor region and the second conductor region, respectively;
the second thin film transistor comprises: the second semiconductor layer in which a third conductor region and a fourth conductor region are defined so as to be spaced apart from each other and a second channel region is defined between the third conductor region and the fourth conductor region; a second gate electrode provided on the second semiconductor layer via the fourth inorganic insulating film and formed of the fourth metal film; and a third terminal electrode and a fourth terminal electrode provided by the third metal film so as to be spaced apart from each other and electrically connected to the third conductor region and the fourth conductor region, respectively;
A display device, wherein a plurality of wirings extending parallel to each other are provided in the display area and made of the first metal film. 2. The display device according to claim 1,
The display device is characterized in that the wiring is a source line or a power supply line. 3. The display device according to claim 1,
A display device comprising: a lower light-shielding layer formed of the first metal film, provided on the base substrate side of the second semiconductor layer. The display device according to any one of claims 1 to 3,
The display device according to the present invention, wherein the thin film transistor layer includes a fifth inorganic insulating film and a planarizing film made of an organic resin material, which are laminated in this order on the fourth metal film. 5. The display device according to claim 4,
a light emitting element layer provided on the thin film transistor layer, in which a plurality of light emitting elements are arranged corresponding to a plurality of sub-pixels constituting the display region;
and a sealing film provided on the light-emitting element layer. 6. The display device according to claim 5,
a fifth metal film is provided between the fifth inorganic insulating film and the planarization film;
a fifth metal film formed on the first thin film transistor and the second thin film transistor on the light emitting element layer side, the fifth metal film being formed on the first thin film transistor and the second thin film transistor on the light emitting element layer side; 7. The display device according to claim 5,
The display device is characterized in that the light-emitting element is an organic electroluminescence element.